BLOCK DIAGRAM
FEATURES
DESCRIPTION
Rev.: F
Amendment: /0
Issue Date: October, 1998
The SY100S815 is a low skew 1-to-4 PECL differential
driver designed for clock distribution in new, high-
performance PECL systems. It accepts either a PECL
clock input or a TTL input by using the TTL enable pin T
EN
.
When the TTL enable pin is HIGH, the TTL input is enabled
and the PECL input is disabled. When the enable pin is set
LOW, the TTL input is disabled and the PECL input is
enabled.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the S815 shares a common set of "basic"
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50
, even if only one side is being used. In
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same V
CCO
as the pair(s) being used on that side) in order
to maintain minimum skew.
s
Quad PECL version of popular ECLinPS E111
s
Low skew
s
Guaranteed skew spec
s
TTL enable input
s
Selectable TTL or PECL clock input
s
Single +5V supply
s
Differential internal design
s
PECL I/O fully compatible with industry standard
s
Internal 75k
PECL input pull-down resistors
s
Available in 16-pin SOIC package
ClockWorksTM
SY100S815
SINGLE SUPPLY QUAD
PECL/TTL-TO-PECL
Pin
Function
E
IN
, E
IN
Differential PECL Input Pair
T
IN
TTL Input
T
EN
TTL Input Enable
Q
0
, Q
0
Q
3
, Q
3
Differential PECL Outputs
V
CC
PECL V
CC
(+5.0V)
V
EE
PECL Ground (0V)
PIN CONFIGURATION
PIN NAMES
1
2
3
4
5
6
7
8
15
16
14
13
12
11
10
9
V
CC
T
IN
Q
3
Q
2
Q
2
V
CCO
E
IN
T
EN
V
EE
Q
0
Q
0
Q
1
V
CCO
TOP VIEW
SOIC
Z16-1
Q
3
E
IN
Q
1
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
E
IN
E
IN
0
1
T
IN
T
EN
1
3
ClockWorksTM
SY100S815
Micrel
AC ELECTRICAL CHARACTERISTICS
(16)
NOTES:
1. Part-to-part skew is defined as Max. -- Min. value at the given temperature.
2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. V
PP
(min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The V
PP
(min.) is AC limited for
the S815, as a differential input as low as 50mV will still produce full PECL levels at the output.
6. V
CMR
is defined as the range within which the V
IH
level may vary, with the device still meeting the propagation delay specification. The V
IL
level must
be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to V
PP
(min.).
V
CC
= V
CCO
= +5.0V
5%
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
t
PLH
Propagation Delay to Output
(1)
ps
t
PHL
E
IN
(differential)
(2)
430
--
630
430
--
630
430
--
630
E
IN
(single-ended)
(3)
330
--
730
330
--
730
330
--
730
T
IN
350
--
950
350
--
950
350
--
950
t
skew
Within-Device skew
(4)
--
25
50
--
25
50
--
25
50
ps
V
PP
Minimum PECL
(5)
250
--
--
250
--
--
250
--
--
mV
Input Swing
V
CMR
PECL Common
(6)
1.6
--
0.4
1.6
--
0.4
1.6
--
0.4
V
Mode Range
t
r
Output Rise/Fall Times
275
375
600
275
375
600
275
375
600
ps
t
f
20% to 80%
Ordering
Package
Operating
Code
Type
Range
SY100S815ZC
Z16-1
Commercial
SY100S815ZCTR
Z16-1
Commercial
PRODUCT ORDERING CODE
4
ClockWorksTM
SY100S815
Micrel
16 LEAD SOIC .300" WIDE (Z16-1)
Rev. 03
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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