CLK
/EN
MR
Function
Z
L
L
Divide
ZZ
H
L
Hold Q
03
X
X
H
Reset Q
03
The SY100S839V is a low skew
2/4,
4/5/6 clock
generation chip designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The device can be driven
by either a differential or single-ended ECL/LVECL or, if
positive power supplies are used, PECL/LVPECL input
signal. In addition, by using the V
BB
output, a sinusoidal
source can be AC-coupled into the device. If a single-
ended input is to be used, the V
BB
output should be
connected to the /CLK input and bypassed to ground via
a 0.01
F capacitor. The V
BB
output is designed to act as
the switching reference for the input of the S839V under
single-ended input conditions. As a result, this pin can
only source/sink up to 0.5mA of current.
The common enable (/EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a
random state; the master reset (MR) input must be
asserted to ensure synchronization. For systems which
only use one S839V, the MR pin need not be exercised
as the internal divider designs ensures synchronization
between the
2/4, and the
4/5/6 outputs of a single
device.
PIN CONFIGURATION/BLOCK DIAGRAM
s
3.3V and 5V power supply option
s
50ps output-to-output skew
s
50% duty cycle outputs
s
Synchronous enable/disable
s
Master Reset for synchronization
s
Internal 75K
input pull-down resistors
s
Available in 20-pin SOIC package
TRUTH TABLE
DESCRIPTION
FEATURES
Rev.: A
Amendment: /0
Issue Date: May, 1999
2/4,
4/5/6 CLOCK
GENERATION CHIP
NOTE:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
ClockWorksTM
SY100S839V
FINAL
Pin
Function
CLK
Differential Clock Inputs
/EN
Synchronous Enable
MR
Master Reset
V
BB
Reference Output
Q
0,
Q
1
Differential
2/4 Outputs
Q
2,
Q
3
Differential
4/5/6 Outputs
DIVSEL
Frequency Select Input
PIN NAMES
DIVSELb1
DIVSELb0
Q
2,
Q
3
OUTPUTS
0
0
Divide by 4
0
1
Divide by 6
1
0
Divide by 5
1
1
Divide by 5
DIVSELa
Q
0,
Q
1
OUTPUTS
0
Divide by 2
1
Divide by 4
V
CC
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
V
EE
V
CC
EN
DIVSELb0
CLK
CLK
V
BB
MR
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
SOIC
Z20-1
DIVSELb1
DIVSELa
1
3
ClockWorksTM
SY100S839V
Micrel
T
A
= 40
C
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ. Max. Min.
Typ. Max. Min.
Typ. Max.
Unit
f
MAX
Maximum Toggle Frequency
1000
--
--
1000
--
--
1000
--
--
1000
--
--
MHz
t
PLH
Propagation Delay to Output
ps
t
PHL
CLK
Output (Diff.)
725
--
925
725
--
925
725
--
925
725
--
925
CLK
Output (S.E.)
675
--
975
675
--
975
675
--
975
675
--
975
MR
Output
600
--
900
600
--
900
610
--
910
630
--
930
t
skew
Within-Device Skew
(2)
Q
0
-- Q
3
--
--
50
--
--
50
--
--
50
--
--
50
ps
Part-to-Part
Q
0
-- Q
3
(Diff.)
--
--
200
--
--
200
--
--
200
--
--
200
t
S
Set-up Time
/EN
/CLK
250
--
--
250
--
--
250
--
--
250
--
--
ps
DIVSEL
CLK
400
--
--
400
--
--
400
--
--
400
--
--
t
H
Hold Time
/CLK
/EN
100
--
--
100
--
--
100
--
--
100
--
--
ps
CLK
DIVSEL
150
--
--
150
--
--
150
--
--
150
--
--
V
PP
Minimum Input Swing
(3)
CLK
250
--
--
250
--
--
250
--
--
250
--
--
mV
V
CMR
Common Mode Range
(4), (5)
-1.6
--
-0.4
-1.7
--
-0.4
-1.7
--
-0.4
-1.7
--
-0.4
V
t
RR
Reset Recovery Time
--
--
100
--
--
100
--
--
100
--
--
100
ps
t
PW
Minimum Pulse Width
CLK
500
--
--
500
--
--
500
--
--
500
--
--
ps
MR
700
--
--
700
--
--
700
--
--
700
--
--
tr
Output Rise/Fall Times
Q
280
--
550
280
--
550
280
--
550
280
--
550
ps
t
f
(20% --80%)
AC ELECTRICAL CHARACTERISTICS
(1)
V
EE
= V
EE
(min) to V
EE
(max); V
CC
= GND
NOTES:
1. Parametric values specified at:
-3.0V to -3.8V or -4.2V to -5.5V.
2. Skew is measured between outputs under identical transitions.
3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between V
PP
min. and 1V. The lower end of the CMR range varies 1:1 with V
EE
. The numbers in the spec table
assume a nominal V
EE
= 3.3V. Note for PECL operation, the V
CMR
(min) will be fixed at 3.3V IV
CMR
(min)I.
5. Duty Cycle: (Min. 48%; Max. 52%) } over temp.
5
ClockWorksTM
SY100S839V
Micrel
20 LEAD SOIC .300" WIDE (Z20-1)
Rev. 03
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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