Pin
Function
BUSEN
04
Bus Enable Inputs
D
0
D
4
Data Inputs
CLK
1
Bus Driver Clock Input
CLK
2
Receive Register Clock
MR
Master Reset
Q
0
Q
4
Bus Receive Outputs
BUS
04
Bus Outputs
DESCRIPTION
FEATURES
s
25
cut-off bus outputs
s
50
receiver outputs
s
Transmit and receive registers with separate clocks
s
1500ps max. delay from CLK
1
to Bus Outputs (BUS)
s
1500ps max. delay from CLK
2
to Receiver Outputs (Q)
s
Individual bus enable pins
s
Internal 75K
input pull-down resistors
s
Voltage and temperature compensation for improved
noise immunity
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 4.2V to 5.5V
s
Available in 28-pin PLCC package
The SY100S891 is a 5-bit registered transceiver
containing five bus transceivers with both transmit and
receive registers. The bus outputs (BUS
0
BUS
4
) are
specified for driving a 25 ohm bus and the receive outputs
(Q
0
Q
4
) are specified for driving a 50 ohm line. The
bus outputs have a normal high level output voltage and
a normal low level output voltage when the bus enable
(BUSEN
0
BUSEN
4
) is high. However, the output is
switched to a cut-off level when a bus-enable is low.
This cut-off level is sufficiently low that a relatively high
impedance is presented to the bus in order to minimize
reflections. There is one bus-enable for each bus driver;
a clock (CLK
1
) which is common to all five bus driver
registers; and a separate clock (CLK
2
) which is common
to all five receive registers. Data at the D inputs is clocked
to the Bus register by a positive transition of CLK
1
and
data on the bus is clocked into the Receiver register by
a positive transition of CLK
2
. A high on the Master Reset
clears all registers.
5-BIT REGISTERED
TRANSCEIVER
PIN CONFIGURATION
PIN NAMES
SY100S891
Rev.: E
Amendment: /0
Issue Date: August, 1998
TOP VIEW
PLCC
J28-1
26
27
28
1
2
3
4
18
17
16
15
14
13
12
Q
3
V
CC
Q
2
V
CCA
BUS
3
BUS
2
Q
1
25
24 23 22
21 20
19
5
6
7
8
9
10 11
V
EE
MR
CLK
1
BUSEN
2
D
1
CLK
2
D
2
Q
0
BUS
0
BUS
1
D
0
BUSEN
1
BUSEN
0
V
CCA
D
3
D
4
BUSEN
4
BUS
4
BUSEN
3
Q
4
V
CC
A
1
3
SY100S891
Micrel
DC ELECTRICAL CHARACTERISTICS
V
EE
= 4.2V to 5.5V unless otherwise specified; V
CC
= V
CCA
= GND
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
V
CUT
Cut-off Bus Output Voltage
2200
2160
2100
mV
V
IN
= V
IH
(Max.) or V
IL
(Min.)
Loading with
25
to 2.20V
V
OH
Output HIGH Voltage Bus
1025
955
880
mV
V
IN
= V
IH
(Max.) or V
IL
(Min.)
Loading with
V
OL
Output LOW Voltage Bus
1810
1705
1620
mV
25
to 2.0V
V
OHA
Output HIGH Voltage Bus
1035
--
--
mV
V
IN
= V
IH
(Min.) or V
IL
(Max.)
V
OLA
Output LOW Voltage Bus
--
--
1610
mV
V
OH
Output HIGH Voltage Receiver
1025
955
880
mV
V
IN
= V
IH
(Max.) or V
IL
(Min.)
Loading with
V
OL
Output LOW Voltage Receiver
1810
1705
1620
mV
50
to 2.0V
V
OHA
Output HIGH Voltage Receiver
1035
--
--
mV
V
IN
= V
IH
(Min.) or V
IL
(Max.)
V
OLA
Output LOW Voltage Receiver
--
--
1610
mV
V
IH
Input HIGH Voltage
1165
--
880
mV
Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage
1810
--
1475
mV
Guaranteed LOW Signal for All Inputs
I
IL
Input LOW Current
0.5
--
--
A
V
IN
= V
IL
(Min.)
I
IH
Input High Current
--
--
150
A
V
IN
= V
IH
(Max.)
I
EE
Power Supply Current
216
--
--
mA
Inputs Open
C
IN
Input Pin Capacitance
--
4
--
pF
C
OUT
Output Pin Capacitance
--
5
--
pF
5
SY100S891
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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