Rev.: E

Amendment: /0

Issue Date: May, 1998

125MHz TRIGGER
PROGRAMMABLE TIMING
EDGE VERNIER

SY604

DESCRIPTION

FEATURES

Micrel-Synergy's SY604 is an ECL-compatible timing vernier

(delay generator) whose time delay is programmed via an 8-
bit code which is loaded concurrently with the circuit trigger.
The SY604 is fabricated in Micrel-Synergy's proprietary
ASSETTM bipolar process.

This device can be retriggered at speeds up to 125MHz,

with a delay span as short as 4ns. At minimum span, the
resolution is 4ns/255 = 15.7ps per step. The delay span is
externally adjustable up to 40ns. The SY604 employs
differential TRIGGER inputs, and produces a differential
OUTPUT pulse; all other control signals are single-ended
ECL. Edge delay is specified by an 8-bit input which is loaded
into the device with the TRIGGER. The output pulse width will
typically be 3.5ns.

The SY604 is commonly used in Automatic Test Equipment

to provide precise timing edge placement; it is also found in
many instrumentation and communications applications.

Micrel-Synergy's circuit design techniques coupled with

ASSETTM technology result in not only ultra-fast performance,
but allow device operation at lower power dissipation than
competing technologies. Outstanding reliability is achieved in
volume production.

True 125MHz retrigger rate

Pin-compatible with Bt604

15ps delay resolution

Less than

1 LSB timing accuracy

Differential TRIGGER inputs

Delay spans from 4 to 40ns

Compatible with 10KH ECL logic

Lower power dissipation 350mW typical

Available in 28-pin plastic (PLCC) or metal (MLCC)
J-lead package

BLOCK DIAGRAM

PIN CONFIGURATION

LATCH

I/V

LINEAR

RAMP

GENERATOR

0 = STOP

1 = RUN

OUT

IEXT

D0 - D7

TRIG

PULSE

GEN

DAC

OUT

TRIG

EE1

COMP

NC
V

COMP

IEXT

10 11

TOP VIEW

PLCC

J28-1

25 24 23

21 20 19

EE1

TRIG

EE0

SY604

Micrel

D0 D7
Data input pins (ECL compatible). On the rising edge of TRIG,
a ramp is initiated whereupon D0-D7 are latched into the
device. D0 is the LSB. These inputs specify the amount of
delay from the rising edge of TRIG to the output pulse.

CE
Chip enable input (ECL compatible). CE must be a logical
zero on the rising edge of TRIG to enable the device to
respond to the trigger. If CE is floating, the trigger will always
be enabled.

TRIG, TRIG
Differential trigger inputs (ECL compatible). The rising edge
of TRIG is used to trigger the delay cycle if CE is a logical zero.
If CE is a logical one, no operation occurs. It is recommended
that triggering be performed with differential inputs.

PIN DESCRIPTION

OUT, OUT
Differential outputs (ECL compatible).

IEXT
Current reference pin. The amount of current sourced into this
pin determines the span of output delay. The voltage at IEXT
is typically 1.25V.

COMP1, COMP2
Compensation pins. A 0.1

F ceramic capacitor must be

connected between COMP1 and V

EE0

, and COMP2 and V

EE0

(see Figure 3).

Device power. All V

pins must be connected.

Device ground. All V

pins must be connected together.

A 1.36V (typical) output.

FUNCTIONAL DESCRIPTION

The output pulse generation cycle begins with the arrival of

TRIG shown in Figure 1. When TRIG transitions to a high and
CE is low, the values on D0 - D7 are latched, thereby setting
the DAC values. Simultaneously with the latching of D0 - D7,
the linear ramp generator is enabled.

Figure 1.

When the ramp level reaches that of the DAC, the

comparator initiates the pulse generator to produce an output
pulse of fixed width. The generation of an output pulse resets
the ramp and the cycle is ready to begin again.

TRIG

OUT

D0 - D7

DATA

SY604

Micrel

Symbol

Parameter

Min.

Typ.

Max.

MIn.

Typ.

Max.

Min.

Typ.

Max.

Unit

Input HIGH Voltage (10K)

-1170

-840

-1130

-810

-1070

-735

Input LOW Voltage (10K)

-1950

-1480

-1950

-1480

-1950

-1450

Output HIGH Voltage (10K)

-1020

-975

-840

-980

-920

-810

-920

-850

-735

Output LOW Voltage (10K)

-1950

-1755

-1630

-1950

-1750

-1630

-1950

-1720

-1600

Input High Current (Vin = V

max)

100

150

100

150

100

150

TRIG, TRIG

100

150

100

150

100

150

Input Low Current (Vin = V

min)

100

150

100

150

100

150

TRIG, TRIG

100

150

100

150

100

150

Output Delay Spans

Differential Linearity Error**

0.84

0.9

0.84

0.9

0.84

0.9

LSB

Integral Linearity Error**

1.16

1.25

0.89

1.0

0.89

1.0

Output Voltage

-1.44

-1.25

-1.44

-1.35

-1.25

-1.44

-1.25

EXT

for Tspans

Tspan = 4ns

1.80

2.38

2.80

1.80

2.38

2.80

1.80

2.38

2.80

Tspan = 5ns

1.45

1.85

2.40

1.45

1.85

2.40

1.45

1.85

2.40

Tspan = 10ns

0.70

0.93

1.20

0.70

0.93

1.20

0.70

0.93

1.20

Tspan = 15ns

0.45

0.62

0.80

0.45

0.62

0.80

0.45

0.62

0.80

Tspan = 20ns

0.34

0.46

0.60

0.34

0.46

0.60

0.34

0.46

0.60

Tspan = 30ns

0.20

0.30

0.40

0.20

0.30

0.40

0.20

0.30

0.40

Tspan with I

EXT

= 1.8 mA

(Tspan = Tmax - Tmin)

4.1

6.5

4.1

6.5

4.1

6.5

Tmin

Minimum Delay Time*

Data = 00, Tspan = 5ns

2.8

3.8

2.8

3.8

2.8

3.8

Tspan = 10ns

3.4

4.9

3.4

4.9

3.4

4.9

Tspan = 15ns

4.0

6.0

4.0

6.0

4.0

6.0

Tspan = 20ns

4.6

7.1

4.6

7.1

4.6

7.1

Tspan = 25ns

5.2

8.2

5.2

8.2

5.2

8.2

Tspan = 30ns

5.8

9.3

5.8

9.3

5.8

9.3

Supply Current

100

= +0°C

= +25°C

= +70°C

DC CHARACTERISTICS

(1)

NOTE:

1. 10K series circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test

socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Outputs are terminated through a 50

resistor

to -2.0 volts.

ABSOLUTE MAXIMUM RATING

(1)

Symbol

Parameter

Value

Unit

Power Supply (V

= 0V)

-8 to 0

Input Voltage

= 0V)

0 to V

OUT

Output Current

-- Continuous

-- Surge

100

Operating Temperature Range

0 to +85

°C

Operating Range

(2)

-5.7 to -4.2

NOTES:

1. Beyond which device life may be impaired.

2. Parametric values specified at 10E Series: - 4.75V to - 5.5V.

SY604

Micrel

AC CHARACTERISTICS

The information in this table is guaranteed but not 100% production tested.

See Figure 2 for a graphical representation.

Maximum Tspan (ns)

Minimum Trigger

Maintaining Linearity

Periods (ns)

1 LSB

ECL input values are -0.9 to -1.7V, with input rise/fall times

2ns,

measured between the 20% and 80% points. Timing reference
points at 50% for inputs and outputs.

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

MAX

Trigger Rate

(1)

125

MHz

Trigger Width High

2.0

1.0

2.0

1.0

2.0

1.0

Output Pulse Width High Time

2.5

3.5

4.5

2.5

3.5

4.5

2.5

3.5

4.5

Output Pulse Rise/Fall Time (20/80%)

550

750

550

750

550

750

Output Pulse Spacing

Span = 4ns @ 1 LSB

8.0

Minimum Delay Time vs. Tspan

T00 / ns (Tspan = 5 to 10ns)

125

220

125

220

125

220

ps/ns

Output Delay

1 LSB

Tspan (Tspan = Tmax - Tmin)

4.0

1 LSB

Resolution (Tspan / 225)

15.7

157

15.7

157

15.7

157

Tempo (5ns Span)

Tspan / °C

ps/°C

Tmin / °C

ps/°C

Power Supply Rejection

ps/V

(Data = 0-FF HEX, Tspan = 5ns)

CE Setup Time

2.0

CE Hold Time

1.5

WRITE Pulse Width High Time

2.0

D0 - D7 Setup Time

1.0

D0 - D7 Hold Time

1.5

= +0°C

= +25°C

= +70°C

Maximum Tspan and Trigger Rates

4.0

8.0

5.1

10.0

5.8

11.1

6.75

12.5

8.1

14.3

9.9

16.6

12.0

20.0

15.5

25.0

22.0

33.3

OUT and OUT loading with 50

to -2.0V. Typical values are

based on nominal temperature, i.e., and nominal voltage, i.e.,
-5.2V.

NOTE:

1. See chart below:

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