1
SY69753L
Micrel
3.3V, 125Mbps 155Mbps
CLOCK and DATA RECOVERY
SY69753L
Rev.: B
Amendment: /2
Issue Date:
September 2003
DESCRIPTION
FEATURES
s
Industrial temperature range (40
C to +85
C)
s
3.3V power supply
s
SONET/SDH/ATM compatible
s
Clock and data recovery for 125Mbps/155Mbps NRZ
data stream
s
Two on-chip PLLs: one for clock generation and
another for clock recovery
s
Selectable reference frequencies
s
Differential PECL high-speed serial I/O
s
Line receiver input: no external buffering needed
s
Link fault indication
s
100k ECL compatible I/O
s
Complies with Bellcore, ITU/CCITT and ANSI
specifications for OC-3 applications
s
Available in 32-pin EPAD-TQFP
The SY69753L is a complete Clock Recovery and Data
Retiming integrated circuit for OC-3/STS-3 applications
at 155Mbps NRZ. The device is ideally suited for SONET/
SDH/ATM applications and other high-speed data
transmission systems.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming
data stream. The VCO center frequency is controlled by
the reference clock frequency and the selected divide
ratio. On-chip clock generation is performed through the
use of a frequency multiplier PLL with a byte rate source
as reference.
The SY69753L also includes a link fault detection
circuit.
Data sheets and support documentation can be found on
Micrel's web site at www.micrel.com.
APPLICATIONS
s
Ethernet media converter
s
SONET/SDH/ATM OC-3
s
Proprietary architectures at 135Mbps to 180Mbps
BLOCK DIAGRAM
PHASE
DETECTOR
PHASE/
FREQUENCY
DETECTOR
CHARGE
PUMP
VCO
CHARGE
PUMP
VCO
LINK FAULT
DETECTION
DIVIDER
BY 8, 10, 16, 20
REFCLK
(TTL)
CD (PECL)
RDINN
RDINP
PLLR P/N
CLKSEL
(TTL)
RDOUTP
RCLKP
RCLKN
RDOUTN
PLLS P/N
DIVSEL 1/2
TCLKP
TCLKN
V
CC
V
CCA
V
CCO
GND
1
0
0
1
PHASE/
FREQUENCY
DETECTOR
LFIN
(TTL)
(PECL)
(PECL)
(PECL)
(TTL)
(PECL)
2
SY69753L
Micrel
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
RDINP
RDINN
NC
REFCLK
NC
NC
NC
RDOUTP
RDOUTN
VCCO
RCLKP
RCLKN
VCCO
TCLKP
TCLKN
9
10
11
12
13
14
15
16
CLKSEL
PLLRP
PLLRN
GND
GND
GND
A
PLLSN
PLLSP
32
31
30
29
28
27
26
25
DIVSEL2
CD
VCC
VCC
VCCA
VCCA
LFIN
DIVSEL1
Top View
EPAD-TQFP
H32-1
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Operating
Package
Part Number
Type
Range
Marking
SY69753LHI
H32-1
Industrial
SY69753LHI
SY69753LHI*
H32-1
Industrial
SY69753LHI
*Tape and Reel
INPUTS
RDINP, RDINN [Serial Data Input] Differential PECL
These built-in line receiver inputs are connected to the
differential receive serial data stream. An internal receive PLL
recovers the embedded clock (RCLK) and data (RDOUT)
information.
REFCLK [Reference Clock] TTL Input
This input is used as the reference for the internal frequency
synthesizer and the "training" frequency for the receiver PLL to
keep it centered in the absence of data coming in on the RDIN
inputs.
CD [Carrier Detect] PECL Input
This input controls the recovery function of the Receive PLL
and can be driven by the carrier detect output of optical modules
or from external transition detection circuitry. When this input is
HIGH the input data stream (RDIN) is recovered normally by the
Receive PLL. When this input is LOW the data on the inputs
RDIN will be internally forced to a constant LOW, the data outputs
RDOUT will remain LOW, the Link Fault Indicator output LFIN
forced LOW and the clock recovery PLL forced to look onto the
clock frequency generated from REFCLK.
DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs
These inputs select the ratio between the output clock frequency
(RCLK/TCLK) and the REFCLK input frequency as shown in the
"Reference Frequency Selection"
Table.
CLKSEL [Clock Select] TTL Inputs
This input is used to select either the recovered clock of the
receiver PLL (CLKSEL = HIGH) or the clock of the frequency
synthesizer (CLKSEL = LOW) to the TCLK outputs.
PIN DESCRIPTIONS
OUTPUTS
LFIN [Link Fault Indicator] TTL Output
This output indicates the status of the input data stream RDIN.
Active HIGH signal is indicating when the internal clock recovery
PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range of
the Receive PLL (1000ppm). LFIN is an asynchronous output.
RDOUTP, RDOUTN [Receive Data Output] Differential PECL
These ECL 100K outputs represent the recovered data from
the input data stream (RDIN). This recovered data is specified
against the rising edge of RCLK.
RCLKP, RCLKN [Clock Output] Differential PECL
These ECL 100K outputs represent the recovered clock used
to sample the recovered data (RDOUT).
TCLKP, TCLKN [Clock Output] Differential PECL
These ECL 100K outputs represent either the recovered clock
(CLKSEL = HIGH) used to sample the recovered data (RDOUT)
or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]
External loop filter pins for the clock synthesis PLL.
PLLRP, PLLRN [Clock Recovery PLL Loop Filter]
External loop filter pins for the receiver PLL.
POWER & GROUND
VCC
Supply Voltage(1)
VCCA
Analog Supply Voltage(1)
VCCO
Output Supply Voltage(1)
GND
Ground
N/C
No Connect
NOTE:
1. VCC, VCCA, VCCO must be the same value.
3
SY69753L
Micrel
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
) .................................. 0.5V to +5.0V
Input Voltage (V
IN
) .......................................... 0.5V toV
CC
Output Current (I
OUT
)
Continuous ......................................................... 50mA
Surge ................................................................ 100mA
Storage Temperature (T
S
) ....................... 65
C to +150
C
Operating Ratings
(Note 2)
Supply Voltage (V
CC
) .............................. +3.15V to +3.45V
Ambient Temperature (T
A
) ..................... 40
C to +85
C
Junction Temperature (T
J
) .................................. +125
C
Package Thermal Resistance, Note 3
EPAD-TQFP
(
JA
)
Still-Air ............................................................. 28
C/W
500lfpm ............................................................ 20
C/W
EPAD-TQFP
(
JC
) ................................................. 4
C/W
T
A
= 40
C to +85
C
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CC
Power Supply Voltage
3.15
3.3
3.45
V
I
CC
Power Supply Current
--
170
230
mA
DC ELECTRICAL CHARACTERISTICS
V
CC
= V
CCO
= V
CCA
= 3.3V
5%; T
A
= 40
C to + 85
C
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
V
CC
1.165
--
V
CC
0.880
V
V
IL
Input LOW Voltage
V
CC
1.810
--
V
CC
1.475
V
I
IL
Input LOW Current
V
IN
= V
IL
(Min.)
0.5
--
--
A
V
OH
Output HIGH Voltage
50
to V
CC
2V
V
CC
1.075
--
V
CC
0.830
V
V
OL
Output LOW Voltage
50
to V
CC
2V
V
CC
1.860
--
V
CC
1.570
V
V
CC
= V
CCO
= V
CCA
= 3.3V
5%; T
A
= 40
C to + 85
C
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
2.0
--
V
CC
V
V
IL
Input LOW Voltage
--
--
0.8
V
I
IH
Input HIGH Current
V
IN
= 2.7V, V
CC
= Max.
125
--
--
A
V
IN
= V
CC
, V
CC
= Max.
--
--
+100
A
I
IL
Input LOW Current
V
IN
= 0.5V, V
CC
= Max.
300
--
--
A
V
OH
Output HIGH Voltage
I
OH
= 0.4mA
2.0
--
--
V
V
OL
Output LOW Voltage
I
OL
= 4mA
--
--
0.5
V
I
OS
Output Short Circuit Current
V
OUT
= 0V (maximum 1sec)
15
--
100
mA
TTL DC ELECTRICAL CHARACTERISTICS
PECL 100K DC ELECTRICAL CHARACTERISTICS
Note 1.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG
conditions for extended periods may affect device reliability.
Note 2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3.
Numbers valid with proper thermal design of PCB and exposed pad soldered to island on PCB. Refer to Figure on page 9.
4
SY69753L
Micrel
V
CC
= V
CCO
= V
CCA
= 3.3V
5%; T
A
= 40
C to + 85
C
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
VCO
VCO Center Frequency
800
--
1100
MHz
f
VCO
VCO Center Frequency
Nominal
--
5
--
%
Tolerance
t
ACQ
Acquisition Lock Time
--
--
15
s
t
CPWH
REFCLK Pulse Width HIGH
4
--
--
ns
t
CPWL
REFCLK Pulse Width LOW
4
--
--
ns
t
DV
Data Valid
1/(2*f
RCLK
) 200
--
--
ps
t
DH
Data Hold
1/(2*f
RCLK
) 200
--
--
ps
t
ir
REFCLK Input Rise Time
--
0.5
2
ns
t
ODC
Output Duty Cycle (RCLK/TCLK)
45
--
55
% of UI
t
rskew
Recovered Clock Skew
200
--
+200
ps
t
r
, t
f
ECL Output Rise/Fall Time
50
to V
CC
2V
100
--
500
ps
(20% to 80%)
AC ELECTRICAL CHARACTERISTICS
5
SY69753L
Micrel
FUNCTIONAL DESCRIPTION AND CHARACTERISTICS
Clock Recovery
Clock Recovery, as shown in the block diagram generates
a clock that is at the same frequency as the incoming data
bit rate at the Serial Data input. The clock is phase aligned
by a PLL so that it samples the data in the center of the
data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30
s data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
Lock Detect
The SY69753L contains a link fault indication circuit which
monitors the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be forced to
lock to the local reference clock. This will maintain the correct
frequency of the recovered clock output under loss of signal
or loss of lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by more
than approximately 1000ppm, the PLL will be declared out
of lock. The lock detect circuit will poll the input data stream
in an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within approximately
1000ppm, the PLL will be declared in lock and the lock
detect output will go active.
Performance
The SY69753L PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the Bellcore
Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-
T Recommendations: G.958 document, when used with differential
inputs and outputs.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak-to-peak amplitude
of sinusoidal jitter applied on the input signal that causes an
equivalent 1dB optical/electrical power penalty. SONET input jitter
tolerance requirement condition is the input jitter amplitude which
causes an equivalent of 1dB power penalty.
Figure 1. Input Jitter Tolerance
OC/STS-N
f0
f1
f2
f3
ft
Level
(Hz)
(Hz)
(Hz)
(kHz)
(kHz)
3
10
30
300
6.5
65
15
1.5
0.40
f0
f1
f2
f4
ft
Sinusoidal Input
Jitter Amplitude
(UI p-p)
Frequency
-20dB/decade
-20dB/decade
A
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter on the
output OC-N/STS-N signal to the jitter applied on the input OC-N/
STS-N signal versus frequency. Jitter transfer requirements are
shown in Figure 2.
Jitter Generation
The jitter of the serial clock and serial data outputs shall not
exceed .01 U.I. rms when a serial data input with no jitter is
presented to the serial data inputs.
0.1
-20
fc
Jitter Transfer (dB)
Frequency
-20dB/decade
Acceptable
Range
Figure 2. Jitter Transfer
OC/STS-N
fc
P
Level
(kHz)
(dB)
3
500
0.1
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