DESCRIPTION

FEATURES

SY87724L

FINAL

Protocol transparent mux/demux operation up to
2.7GHz

Programmable to 4, 5, 8, or 10 bit parallel interfaces

Differential clock and serial inputs/outputs

Easily controlled by framer logic

Synchronous frame boundary indication

HSPC (High Speed PECL Compatible) inputs and
outputs

3.3V power supply

Available in 80-pin LQFP-PQ2 package

The SY87724L is a complete serial data multiplexer and

demultiplexer, capable of operating at up to 2.7GHz. The
device provides for muxing and demuxing to 4, 5, 8, or 10
bit wide buses.

The SY87724L can accept a synchronous code group or

octet boundary input, and uses this input for parallel data
alignment.

The SY87724L is manufactured in Micrel's high

performance ASSET2TM silicon bipolar process.

Micrel provides a complete protocol transparent solution

with the AnyRateTM SY87721L CDR/CMU SY87729L, and
the SY87724L integrated mux/demux.

3.3V AnyRateTM
MUX/DEMUX
Up to 2.7GHz

APPLICATIONS

OC-3, OC-12, OC-48, ATM, InfiniBand

Gigabit Ethernet

Fibre Channel, 2X Fibre Channel

SMPTE-259 and 292

Proprietary optical transport

ITU G. 975 Solutions

SYSTEM BLOCK DIAGRAM

Rev.: A

Amendment: /0

Issue Date:

September 2001

AnyRate is a trademark of Micrel, Inc.

DEMUX

TCLK

4, 5, 8, 10 bits

LOCK

RCLK

RDATA

SY87724L

POST AMP

TIA

PIN DIODE

FIBER

LASER

DIODE

FIBER

SY889x3

CMU

CDR

SY87721L

AnyRateTM

REF_CLK

SEL

One

REF_XTAL

SY87729L

SY889x2

AnyClockTM

LASER

DIODE

DRIVER

Fractional

Synthesizer

MUX

SY87724L

FINAL

Micrel

PIN CONFIGURATION

80-PIN

LQFP-PQ2

21 22 23 24 25 26 27 28 29 30 31 32 33

77 76 75 74 73 72 71 70 69 68 67 66 65

GND

VCC

SIZ1

SIZ2

MP1

MP2

MP3

MP4

34 35 36

MTXCLK+

SIZ0

MP0

MP5

MP6

MP7

VCCO

37 38 39 40

64 63 62 61

MP8

MP9

VCC

VCCO

GND

MSOUT+

MSOUT

LPBK

VCC

MPINCK+

MPINCK

VCCO

DFMIN+

DFMIN

DSIN+

DSIN

GND

VCC

GND

DCKIN+

DCKIN

VCCO

DP9

DP8

DP7

DP6

DP5

DP4

DP4+

DP3

DP3+

VCCO

DP2

DP2+

DP1

DP1+

VCC

MTXCLK

GND

MPF0+

MPF0

MPF1+

MPF1

MPF2+

MPF2

MPF3

MPF3+

MPF4+

MPF4

VCC

GND

VCCO

DPOUTCK+

DPOUTCK

DP0+

DP0

PIN NAMES

COMMON

LPBK TTL Input

This pin defines whether a device exhibits local loopback

or not, as per the following table. Loopback internally
connects mux serial out to demux serial in, thus the user
may expect mux side parallel data to appear on the demux
parallel output pins.

LPBK

Functioning

Loopback

Normal

SIZ0, SIZ1, SIZ2 TTL Input

These three signals determine the width of the parallel

output, as well as the width of parallel input. The following
table describes the parallel width options.

Width

SIZ0

SIZ1

SIZ2

(1)

Undefined

Note:

1. Pin 8 (SIZ2) should always be tied to a TTL logic level LOW.

SY87724L

FINAL

Micrel

DEMUX

DSIN

 Differential HSPC Input

This is the serial input to the SY87724L demux. It accepts

the serial data and converts it to parallel data. It is ignored
during loopback.

DCKIN

 Differential HSPC Input

This is the bit rate clock that feeds serial data into the

demux shift register. This signal also feeds the demux strobe
generator and primary divider, except during loopback.

DFMIN

 Differential HSPC Input

This is the frame alignment input signal. This signal resets

the primary divider, as well as the strobe generator. This
effectively sets the alignment for the parallel data being
demuxed. Usually, DFMIN

asserts one DCKIN

before a

parallel word boundary, and continues to assert one clock
before every boundary. However, DFMIN

need only occur

once for proper operation. Should DFMIN

assert at other

than a previously set boundary, the DPOUTCK

signal will

always occur later than would be expected. That is, there
will never be a short DPOUTCK

pulse.

DP0

through DP4

 Differential PECL Output

These signals may be used as either differential, or single-

ended. When converting to 4 or 5 bits, speed issues may
encourage the use of these signals differentially. When
converting to wider than 5 bits, these signals are to be used
single-ended. Please refer to the applications section for
further details.

DP5 through DP9 PECL Output

These are the rest of the parallel output bits, to be used

when converting to wider than 5 bits. Which bits are valid
depends on the values of SIZ0, SIZ1, and SIZ2. Please
refer to the table in the applications section for further details.

DPOUTCK

 Differential HSPC Output

This signal is used to strobe the DP0-9 data. It is used

differentially when converting to 4 or 5 bits, and is used
single-ended when converting to wider than 5 bits. The
clock rate of the line will be determined by the DCKIN
signal, and by the setting of the SIZ bits. This output always
provides valid differential logic levels.

MUX

MP0-9 PECL Input

These bits accept data for muxing wider than 5 bits.

MPINCK+, used single-ended, determines when this data
may change. Please refer to the table in the description for
which pins represent what bits for various widths.

MPF04

 Differential PECL Input

These signals are used when muxing 4 or 5 bits of parallel

data. MPINCK

determines when this data may change.

Please refer to the Mux table in the description for which
pins represent what bits for various widths.

MTXCLK

 Differential HSPC Input

This is the serial rate clock input to the mux. It determines

the rate at which serial data will be shifted out of the mux.

MSOUT

 Differential PECL Output

This signal is the serialized data output.

MPINCK

 Differential PECL Output

This signal indicates when the next set of parallel bits

may be presented to the SY87724L for muxing. For muxing
wider than 5 bits, MPINCK+ is used single-ended. These
signals always provide valid differential clock signals
regardless of single-ended or differential data mode.

OTHER

Supply Voltage

CCO

Output Supply Voltage

GND

Ground

These pins are reserved and are to be left
unconnected.

Note:

1. All differential outputs always provide valid differential logic levels regardless

of differential or single-ended use.

SY87724L

FINAL

Micrel

DESCRIPTION

General

The SY87724L MDM is designed to perform muxing and

demuxing at up to 2.7GHz speeds. The device can
simultaneously mux and demux up to 10 bits of full duplex
data. In addition, a full parallel-to-parallel loopback function
is implemented, such that parallel data out will loop back to
parallel data in, with the device internally connecting the
serial output to the serial input.
Narrow Demux

In this example, serial data is converted into 4 or 5 bit

wide data. Because this can result in very high data rates
on the parallel outputs, they are differential. The DFMIN

input indicates, synchronously with DCKIN

, and one clock

ahead, the start of a 4 or 5 bit boundary.

MDM

DP0-4

DPOUTCK

DSIN

DCKIN

DFMIN

Figure 1. Narrow Demux

Every DFMIN

assertion will trigger a new 4 or 5 bit

boundary. Should only one DFMIN

assertion occur, then

DPOUTCK

will continue to assert every 4 or 5 DCKIN

clocks. Should a subsequent DFMIN

assertion reset the 4

or 5 bit boundary, then DPOUTCK

will always result in a

longer assertion, not a shorter one.

For example, if a subsequent DFMIN

resets a 5 bit

boundary after the second bit in relation to a previous
boundary, then the next DPOUTCK

will always occur 7

DCKIN

later, never 2 DCKIN

later. For four bit output,

DP5

are not used.

Wide Demux

The more typical case will be to convert the serial data

stream into 8 or 10 bit wide data. Because the worst case
parallel transfer rate is on the order of 250 to 340 Mega-
transfers per second, single ended parallel output is
preferred. Thus, only the single-ended side of the differential
outputs is used.

This example is much like the narrow demux, except

now DFMIN

indicates 8 or 10 bit boundaries.

MDM

DP0-4+

DPOUTCK+

DSIN

DCKIN

DFMIN

DP5-9

Figure 2. Wide Demux

As in the narrow case, DPOUTCK

will never assert

twice in 8 or 10 DCKIN

cycles. Should a DFMIN

assertion

change the MDM's 8 or 10 bit boundary, DPOUTCK

assertion will be delayed and there will never be a short
assertion.

For 8 bit output, DP4

and DP9 are not used.

The following table summarizes the available bit widths.

The right column shows the parallel bits, in sequence from
first in serially, to last in.

Width

Sequence

DP0

, DP1

, DP2

, DP3

DP0

, DP1

, DP2

, DP3

, DP4

DP0+, DP1+, DP2+, DP3+, DP5, DP6, DP7, DP8

DP0+, DP1+, DP2+, DP3+, DP4+, DP5, DP6, DP7,
DP8, DP9

Narrow Mux

In this scenario, 4 or 5 bit wide parallel data is converted

to a serial bit stream. Because this can result in very high
data rates on the parallel inputs, they are differential. In this
mode of operation, there is no external synchronization,
and the MPINCK

signal pair has arbitrary phase with

respect to the MTXCLK

clock, which clocks the mux output

shift register.

MDM

MSOUT

MPF0-4

MPINCK

MTXCLK

Figure 4. Narrow Mux

MPINCK

indicates when MDM is ready to accept more

data. It is derived from MTXCLK

, with an arbitrary phase

relationship.

SY87724L

FINAL

Micrel

Wide Mux

The more typical case will be to convert 8 or 10 bit wide

parallel data words into a serial bit stream. Because the
worst case parallel input rate is on the order of 250 to 340
Mega-transfers per second, single ended parallel inputs are
used.

This scenario is much like the narrow mux case, except

now MPINCK+ clocks slower, for 8 or 10 bit parallel words.

MDM

MSOUT

MP0-9

MPINCK+

MTXCLK

Figure 5. Wide Mux

Note that the input data indication is now single ended,

and that completely different input pins are used, as
compared to the 4 or 5 bit case.

The following table summarizes the available bit widths.

The right column shows the parallel input bits, such as they
will appear in the serial output stream.

Width

Sequence

MPF0

, MPF1

, MPF2

, MPF3

MPF0

, MPF1

, MPF2

, MPF3

, MPF4

MP5, MP6, MP7, MP8, MP0, MP1, MP2, MP3

MP5, MP6, MP7, MP8, MP9, MP0, MP1, MP2, MP3,
MP4

Loopback

To ease system design, the SY87724L MDM has the

capability to loop parallel data in, through the mux, into the
demux, and back to parallel data out. This permits system
check-out through to the individual MDM device. Note that,
for a full check-out, some form of loopback further down the
serial stream is required.

Loopback is incorporated into MDM by modifying the

serial clock, data, and sync inputs to the demux stage.

During loopback, the source of serial information for the

demux is changed. The MSOUT

MTXCLK

and

MSYNOUT

are internally muxed to the DSIN

, DCKIN

and DFMIN

nodes of the demux section. The MSYNOUT

signal

has

the same characteristics as the DFMIN logic

expects.

This exercises the internal data path, both mux and

demux, for MDM, and also the control logic. The parallel
data presented to the parallel inputs will appear, some small
but unspecified time later, at the parallel outputs.

MSOUT

DFMIN

MP*

DP*

* Number of wires depends on the SIZX bits.

DCKIN

DSIN

SY87724L

FINAL

Micrel

Symbol

Parameter

Rating

Unit

Power Supply Voltage

0.5 to +3.8

Input Voltage

0.5 to V

(2)

OUT

ECL Output Current

--Continuous

--Surge

100

store

Storage Temperature Range

65 to +150

Operating Temperature Range

40 to +85

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied

at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended
periods may affect device reliability.

2. The maximum value is specified at V

up to V

= +6V.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Condition

Power Supply Voltage

3.15

3.3

3.45

Power Supply Current

650

750

= V

CCA

= 3.15V to 3.45V

DC ELECTRICAL CHARACTERISTICS

(1)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Condition

Input HIGH Voltage

1.810

Input Voltage

0.2

Differential Swing

(2)

Input LOW Current

0.5

= V

(Min)

Output HIGH Voltage

1.0

0.75

to V

Output LOW Voltage

1.55

1.25

to V

OSW

Output Voltage

0.3

Differential Swing

= V

CCA

= 3.15V to 3.45V

HSPC DC ELECTRICAL CHARACTERISTICS

(1)

NOTE:

1. Operating temperature range from 40

C to +85

NOTE:

1. Operating temperature range from 40

C to +85

2. This implies that the common mode range, V

CMR

, goes from V

(min) + V

/2 through V

(max) - V

/2.

SY87724L

FINAL

Micrel

Symbol

Parameter

Min.

Typ.

Max.

Unit

Condition

Input HIGH Voltage

1.165

0.880

Input LOW Voltage

1.810

1.475

Input LOW Current

0.5

= V

(Min)

Output HIGH Voltage

1.075

0.830

to V

Output LOW Voltage

1.860

1.570

to V

OSW

Output Voltage

0.6

Differential Swing

= V

CCA

= 3.15V to 3.45V

PECL DC ELECTRICAL CHARACTERISTICS

(1)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Condition

Input HIGH Voltage

2.0

Input LOW Voltage

0.8

Input HIGH Current

+20

= 2.7V, V

= Max.

+100

= V

, V

= Max.

Input LOW Current

300

= 0.5V, V

= Max.

= V

CCA

= 3.15V to 3.45V

TTL DC ELECTRICAL CHARACTERISTICS

(1)

NOTE:

1. Operating temperature range from 40

C to +85

NOTE:

1. Operating temperature range from 40

C to +85

SY87724L

FINAL

Micrel

Symbol

Parameter

Min.

Typ.

Max.

Unit

Condition

MAX

Maximum Operating Frequency

2.7

GHz

DCKPWH

Demux Clock Pulse Duty Cycle

DCKPWH

DSDS

Demux Serial Data Setup

200

DSDH

Demux Serial Data Hold

DSFS

Demux Serial Frame Setup

150

DSFH

Demux Serial Frame Hold

DPDP

Demux Parallel

+200

+800

Differential Propagation

DPSP

Demux Parallel

+200

+1200

Single-Ended Propagation

MCKPWH

Mux Clock Pulse Duty Cycle

MCKPWL

MPDS

Mux Parallel Differential Setup

(2)

cyc

+650

MPDH

Mux Parallel Differential Hold

(2)

cyc

+250)

MPSS

Mux Parallel Single-Ended Setup

(2)

cyc

+850

MPSH

Mux Parallel Single-Ended Hold

(2)

cyc

+50)

, t

Output Rise/Fall Times

to V

MCKOUT, MSOUT, MSYNOUT

100

120

(20% to 80%)

All Others

500

= V

CCA

= 3.15V to 3.45V

AC ELECTRICAL CHARACTERISTICS

NOTES:

1. Operating temperature range from 40

C to +85

2. T

cyc

= the period of the clock being fed into MTXCLK.

PRODUCT ORDERING CODE

Ordering

Package

Operating

Code

Type

Range

SY87724LH1

H80-1

Industrial

SY87724L

FINAL

Micrel

MICREL-SYNERGY

3250 SCOTT BOULEVARD

SANTA CLARA

CA 95054

USA

TEL

+ 1 (408) 980-9191

FAX

+ 1 (408) 914-7878

WEB

http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.

80 LEAD LQFP-PQ2 (DIE UP) (H80-1)

Rev. 00

+0.06

0.10
+0.002

0.004

+0.006

0.006

+0.15

0.15

+0.05

0.05

+0.002

0.002

+0.020

0.020

+0.5

0.5

+0.020

0.020

+0.5

0.5

Package

EP- Exposed Pad

Die

CompSide Island

Heat Dissipation

Heavy Copper Plane

Heat Dissipation

PCB Thermal Consideration for 80-Pin EPAD-TQFP Package

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