AnyClockTM

SY87729L

Micrel

DESCRIPTION

FEATURES

AnyClockTM

SY87729L

Fractional synthesizer from 10MHz to 365MHz from a
single 27MHz reference oscillator

Generates exactly the correct frequency for common
transport protocols with or without FEC

Directly enables SY87721L to lock onto any data rate
within its range

Exceeds BellCore and ITU jitter generation
specifications

Programmable via MicroWireTM interface

Available in 32-Pin EPAD-TQFP package

The SY87729L is a complete rate independent frequency

synthesizer integrated circuit. From a single reference
source, this device generates a differential PECL reference
frequency for Micrel's SY87721L 10Mbps to 2.7Gbps
combined CDR and CMU.

The SY87729L generates an exactly correct reference

frequency for common data transport protocols. This is
especially important in transponder applications, where a
standards compliant protocol data unit must be generated
downstream, even in the absence of any signal from the
associated upstream interface.

In addition, SY87729L will generate exactly correct

reference frequencies for common data transport protocols
augmented by forward error correction codes.

For proprietary applications, the SY87729L generates

reference frequencies guaranteed to enable the SY87721L
CDR to lock to any possible baud rate in its range.
SY87729L accepts configuration via a MicroWireTM interface.

Data sheets and support documentation can be found on

Micrel's web site at www.micrel.com.

3.3V AnyClockTM
(10MHz to 365MHz)
FRACTIONAL N SYNTHESIZER

APPLICATIONS

Metro access system

Transponders

Multiplexers: access, add drop mux

SONET/SDH/ATM-based transmission systems,
modules and test equipment

Broadband cross-connects

Fiber optic test equipment

Protocols supported:
OC-1, OC-3, OC-12, OC-48, ATM, Gigabit Ethernet,
Fast Ethernet, Fibre Channel, 2X Fibre Channel,
1394, InfiniBand, proprietary optical transport

Rev.: C

Amendment: /0

Issue Date:

September 2003

AnyClock and AnyRate are trademarks of Micrel, Inc.
MicroWire is a trademark of National Semiconductor.

AnyClockTM

AnyClockTM

SY87729L

Micrel

PIN NAMES

CLKOUT

�

� Differential PECL Output

Reference Clock Output. This is the synthesized clock

generated from REFCLK

�

. It can be used to supply a

reference clock to a data recovery device, such as Micrel's
SY87721L.

LOCKED � TTL Output

Lock Output. This indicates proper operation of all the

blocks in the clock synthesis chain. Logic high indicates
that SY87729L is generating the expected frequency at the
CLKOUT

�

output. Logic low indicates that one or more PLL

in the clock synthesis chain has yet to achieve proper lock.

REFCLK

�

� Differential PECL Input

Reference Clock Input. This is a clock derived from an

oscillator or other sufficiently accurate frequency source.
The frequency provided at this input determines, along with
the programming, what the output frequency at REFOUT

�

will be. Micrel recommends using a 27.000MHz frequency
source.

PROGCS � TTL Input

Program Interface Chip Select. This signal forms part of

the MicroWire interface. When active high, this signal permits
the acquisition of serial data. A falling edge on this input
causes SY87729L to re-acquire lock to a new frequency,
based on the program downloaded to it.

PROGSK � TTL Input

Program Interface Serial Clock. One bit of configuration

data is read in each clock cycle.

PROGDI � TTL Input

Program Interface Data In. One data bit is sampled on

each rising edge of PRGSK, while PROGCS is active high.

FNVCF

�

� Analog I/O

Fractional-N Filter. These pins connect to the output from

the fractional-N synthesizer charge pump, as well as the
input to the corresponding Voltage Controlled Oscillator
(VCO). A filter network, as described below, converts the
charge pump current to a voltage, and adjusts loop
bandwidth.

WRVCF

�

� Analog I/O

Wrapper Filter. These pins connect to the output from

the wrapper synthesizer charge pump, as well as the input
to the corresponding VCO. A filter network, as described
below, converts the charge pump current to a voltage, and
adjusts loop bandwidth.

VCC

Supply Voltage

VCCA

Analog Supply Voltage

VCCO

Output Supply Voltage

GND

Ground

GNDA

Analog Ground

These pins are to be left unconnected

PACKAGE/ORDERING INFORMATION

Ordering Information

Package

Operating

Marking

Part Number

Type

Range

Code

SY87729LHI

H32-2

Industrial

SY87729LHI

31 30 29 28 27 26 25

10 11 12 13

14 15 16

VCCA

REFCLK+

REFCLK�

PROGCS

PROGDI

PROGSK

VCCA

CLKOUT+

CLKOUT�

VCCO

VCC

GND

FNVCF+

FNVCF

�

VCF+

VCF

�

GND

VCC

GND

LOCKED

Top View

EPAD-TQFP

H32-1

32-pin EPAD-TQFP (H32-2)

AnyClockTM

SY87729L

Micrel

DESCRIPTION

General

The SY87729L AnyClockTM Fractional-N Synthesizer is

used in serial data streaming applications, where the
incoming data rate on a channel may vary, or where the
incoming data rate on a channel is unknown ahead of time.

In these situations, a valid output stream must still be

generated even in the absence of any edges on the
corresponding input stream. Until now, designers had to
resort to sub-optimal solutions such as providing multiple
reference oscillators. Beyond the potential noise and EMI
issues, the designer has no way to future proof his circuit,
as it would prove near impossible to pre-provision all the
reference frequencies that might be needed after
deployment, yet are unknown at this time.

The SY87729L solves this problem by generating exact

frequencies for common data streaming protocols, all from
one 27MHz reference. If any of these protocols include
overhead due to use of common digital wrappers, the
SY87729L still generates the exact frequency required,
including the overhead.

Besides generating reference rates for common protocols

directly, The SY87729L also generate reference frequencies
for Micrel's SY87721L CDR/CMU, such that it will reliably
recover data at any rate between 28Mbps and 2,700Mbps
without any gaps.

A simple 3-wire MicroWireTM bit-serial interface loads a

configuration that describes the desired output reference
frequency. All common microcontrollers support this
MicroWireTM interface. Those microcontrollers that don't
support this interface in hardware can easily emulate the
interface in firmware.

The large set of possible frequencies that the SY87729L

generates, are divided into three classes. First, the sets of
frequencies that match a particular data streaming protocol
are in the "protocol" category. Second, the set of frequencies
that are guaranteed to be near enough to any arbitrary data
rate such that the SY87721L will lock are in the "picket
fence" category. Third, the set of frequencies that do not fit
into either of the first two categories is in the third category,

The SY87729L generates these important reference

frequencies through two tandem PLL circuits. The first PLL
uses a modified fractional-N approach to generate a rational
ratio frequency. This PLL is capable of generating all protocol
data rates, except for those that include FEC or digital
wrapper overhead. A second, more traditional P/Q
synthesizer optionally adjusts the output frequency of the
first, fractional-N synthesizer, to accommodate these FEC
or digital wrapper data rates.

The bit serial interface conveys 32 bits of configuration

data from a microcontroller to SY87729L. This simple
interface consists of an active high chip select, a serial
clock (2MHz or less) and a serial data input. Each clock
cycle one bit of configuration data transfers to SY87729L.

Circuit Description

The heart of SY87729L is its fractional-N synthesizer, as

shown in Figure 1.

Phase-

Frequency

Detector/

Charge

Pump

VCO

P-1

Mux

Control

Loop Filter

Input

Reference

Frequency

REF

)

Output
Frequency
(f

FNOUT

)

Figure 1. Fractional-N Synthesizer Architecture

The two dividers in the feedback path always differ by

one count. That is, if one divider is set to divide by P = 5,
then the other divider divides by P-1 = 4 . The mux chooses
between the two based on the control circuit.

The idea behind the fractional-N approach is that every

input reference edge is used. Only those output edges that
are nearest to an input edge get fed back to the phase-
frequency comparator. In addition, the nearest output edges
are chosen in such a way that the net offset, over a number
of edges, zeroes out. It is the control circuit's job to drive
the mux such that only the "correct" edges get fed back.

In the above fractional-N circuit, if the output frequency

should be, for example, 5 times the input frequency, then P
is set to 5, and the control circuit sets the mux to only feed
back the output of the P divider.

If the output frequency should be, for example, 4

times

the input frequency, then the control circuit alternates evenly
between the P and the P-1 divider output. For every two
input edges (one to compare against P, and another to
compare against P-1), you will get 5 + 4 output edges,
yielding an output frequency 9/2 the input frequency.

Whereas P sets the integer part of the multiplication factor

from input to output frequency, the control circuit determines
the fractional part. By mixing the output of the P and P-1
dividers correctly, the control circuit can fashion any output
frequency from P-1 times the input to P times the input, as
long as that ratio can be expressed as a ratio of integers.

Электронный компонент: SY87729LHI