FEATURES

LVPECL or LVDS input to 22 LVPECL outputs

100K ECL compatible outputs

LVDS input includes 100

termination

Guaranteed AC parameters over voltage:

· > 2GHz f

MAX

(toggle)

· < 35ps max. ch-ch skew

Low voltage operation: 2.5V, 3.3V

Temperature range: 40

C to +85

Output enable pin

Available in a 64-Pin EPAD-TQFP

The SY89825U is a High Performance Bus Clock Driver

with 22 differential LVPECL output pairs. This part is
designed for use in low voltage (2.5V, 3.3V) applications
which require a large number of outputs to drive precisely
aligned, ultra low skew signals to their destination. The
input is multiplexed from either LVDS or LVPECL by the
CLK_SEL pin. The LVDS input includes a 100

internal

termination, thus eliminating the need for external
termination. The Output Enable (OE) is synchronous so
that the outputs will only be enabled/disabled when they
are already in the LOW state. This eliminates any chance
of generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.

The SY89825U features low pin-to-pin skew (35ps max.)

--performance previously unachievable in a standard
product having such a high number of outputs. The
SY89825U is available in a single space saving package
which provides a lower overall cost solution. In addition, a
single chip solution improves timing budgets by eliminating
the multiple device solution with their corresponding large
part-to-part skew.

PIN CONFIGURATION

2.5/3.3V 1:22 HIGH-PERFORMANCE,
LOW-VOLTAGE PECL BUS CLOCK DRIVER
& TRANSLATOR w/ INTERNAL TERMINATION

DESCRIPTION

ClockWorksTM

SY89825U

FINAL

APPLICATIONS

High-performance PCs

Workstations

Parallel processor-based systems

Other high-performance computing

Communications

Rev.: A

Amendment: /0

Issue Date:

September 2001

/Q5

VCCO

/Q0

/Q1

/Q2

/Q3

/Q4

/Q6

VCCO

NC
NC

VCCI

LVDS_CLK

/LVDS_CLK

CLK_SEL

LVPECL_CLK

/LVPECL_CLK

GND

OE
NC
NC

/Q21

Q21

VCCO

VCCO
Q7
/Q7
Q8
/Q8
Q9
/Q9
Q10
/Q10
Q11
/Q11
Q12
/Q12
Q13
/Q13
VCCO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64-Pin

EPAD-TQFP

(Top View)

/Q19

VCCO

Q14

/Q14

Q15

/Q15

Q16

/Q16

Q17

/Q17

Q18

/Q18

Q19

Q20

/Q20

VCCO

ClockWorksTM

SY89825U

Micrel

LOGIC SYMBOL

CLK_SEL

LVDS_CLK

/LVDS_CLK

LVPECL_CLK

/LVPECL_CLK

Q0 - Q21

/Q0 - /Q21

LEN

Pin

Function

LVDS_CLK,

Differential LVDS Inputs

/LVDS_CLK

(Internal 100

termination included)

LVPECL_CLK,

Differential LVPECL Inputs.

/LVPECL_CLK

CLK_SEL

Input CLK Select (LVTTL)

Output Enable (LVTTL)

, /Q

Differential LVPECL Outputs.
Terminate with 50

to V

-2V

GND

Ground

CCI

Power Supply. Connect to
V

on PCB. V

CCI

and V

CCO

are not

internally connected

CCO

Power Supply for Output Buffer.
Connect to V

CCI

on PCB. V

CCI

and

CCO

are not internally connected

PIN NAMES

(1)

CLK_SEL

 Q

 /Q

LOW

HIGH

LOW

HIGH

LVDS_CLK

/LVDS_CLK

LVPECL_CLK

/LVPECL_CLK

TRUTH TABLE

NOTE:

1. The OE (output enable) signal is synchronized with the low level of the

LVDS_CLK and LVPECL_CLK signal.

Signal

I/O

Level

LVDS_CLK, /LVDS_CLK

Input

LVDS

, /Q

Output

LVPECL

LVPECL_CLK, /LVPECL_CLK

Input

LVPECL

CLK_SEL, OE

Input

LVCMOS/LVTTL

SIGNAL GROUPS

ABSOLUTE MAXIMUM RATINGS

(1)

NOTE:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not

implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.

Symbol

Rating

Value

Unit

CCI

/ V

CCO

Pin Potential to Ground Pin

0.5 to +4.0

Input Voltage

0.5 to V

CCI

OUT

DC Output Current

Tstore

Storage Temperature

65 to +150

Package Thermal Resistance (Junction-to-Ambient)
With exposed pad soldered to GND

Still-Air (multi-layer PCB)

C/W

200lfpm (multi-layer PCB)

C/W

500lfpm (multi-layer PCB)

C/W

Exposed pad

not soldered to GND

Still-Air (multi-layer PCB)

C/W

200lfpm (multi-layer PCB)

C/W

500lfpm (multi-layer PCB)

C/W

Package Thermal Resistance

4.3

C/W

(Junction-to-Case)

ClockWorksTM

SY89825U

Micrel

DC ELECTRICAL CHARACTERISTICS

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Input Voltage Range

2.4

Differential Input Swing

100

Input Low Current

(1)

1.25

LVDS Differential Input Resistance

100

120

100

120

100

120

(LVDS_CLK to /LVDS_CLK)

LVDS Input (V

= 2.37V to 3.6V, GND = 0V)

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

CCI,

Power Supply

(1)

2.37

3.6

2.37

3.8

2.37

3.6

CCO

Total Supply Current

(2)

100

150

100

150

100

150

Power Supply

= 40

= +25

= +85

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Input HIGH Voltage

1.165

0.88

1.165

0.88

1.165

0.88

(Single ended)

Input LOW Voltage

1.945

1.625

1.945

1.625

1.945

1.625

Minimum Input Swing

(1)

600

LVPECL_CLK

CMR

Common Mode Range

(2)

1.5

0.4

1.5

0.4

1.5

0.4

LVPECL_CLK

Output HIGH Voltage

(3)

CCO

1.085 V

CCO

0.880 V

CCO

1.025 V

CCO

0.880 V

CCO

1.025 V

CCO

0.880

Output LOW Voltage

(3)

CCO

1.830 V

CCO

1.555 V

CCO

1.810 V

CCO

1.620 V

CCO

1.810 V

CCO

1.620

Input HIGH Current

150

Input LOW Current

0.5

LVPECL Input/Output (V

= 2.37V to 3.6V, GND = 0V)

NOTES:

1. The V

(min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.

2. V

CMR

is defined as the range within which the V

level may vary, with the device still meeting the propagation delay specification. The numbers in the table are

referenced to V

CCI

. The V

level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to V

(min.). The lower end of the

CMR range varies 1:1 with V

CCI

. The V

CMR

(min) will be fixed at 3.3V |V

CMR

(min)|.

3. Outputs loaded with 50

to V

-2V.

NOTES:

1. V

CCI

and V

CCO

must be connected together on the PCB such that they remain at the same potential. V

CCI

and V

CCO

are not internally connected on the die.

2. No load. Outputs floating.

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Input HIGH Voltage

2.0

Input LOW Voltage

0.8

Input HIGH Current

+20

250

+20

250

+20

250

Input LOW Current

600

LVCMOS/LVTTL Control Inputs (OE, CLK_SEL) (V

= 2.37V to 3.6V, GND = 0V)

NOTE:

1. For I

, both LVDS inputs are grounded.

ClockWorksTM

SY89825U

Micrel

NOTES:

1. Outputs loaded with 50

to V

2V. Airflow

300lfpm.

2. f

MAX

is defined as the maximum toggle frequency measured. Measured with a 750mV input signal, all loading with 50

to V

2V.

3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential

output signals.

4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same

voltage and temperature.

5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same

voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.

6. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,

set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures
outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.

AC ELECTRICAL CHARACTERISTICS

(1)

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

MAX

Max Toggle Frequency

(2)

GHz

PHL

Propagation Delay

PLH

(Differential)

(3)

LVPECL IN

0.600

1.2

0.600

0.900

1.2

0.600

1.2

LVDS IN

0.800

1.4

0.800

1.1

1.4

0.800

1.4

SKEW

Within-Device Skew

(4)

Part-to-Part Skew

(5)

100

200

100

200

100

200

S(OE)

OE Set-Up Time

(6)

1.0

H(OE)

OE Hold Time

(6)

0.5

Output Rise/Fall Time

300

600

300

450

600

300

600

(20% 80%)

(switchover)

Input Switchover

1.2

CLK_SEL-to-valid output

PRODUCT ORDERING CODE

Ordering

Package

Operating

Package

Code

Type

Range

Marking

SY89825UHI

H64-1

Industrial

SY89825UHI

= 2.37V to 3.6V, GND = 0V

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