SY89859U
Precision Low-Power 8:1 MUX with Internal
Termination and 1:2 LVPECL Fanout Buffer
Precision Edge is a registered trademark of Micrel, Inc.
MLF and
Micro
LeadFrame are trademarks of Amkor Technology, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
May 2005
M9999-052605
hbwhelp@micrel.com
or (408) 955-1690
General Description
The SY89859U is a low jitter, low-power, high-speed
8:1 multiplexer with a 1:2 differential fanout buffer
optimized for precision telecom and enterprise server
distribution applications. The SY89859U distributes
clock frequencies from DC to >2.5GHz, and data rates
to 2.5Gbps guaranteed over temperature and voltage.
The SY89859U differential input includes Micrel's
unique, 3-pin input termination architecture that
directly interfaces to any differential signal (AC- or
DC-coupled) as small as 100mV (200mVpp) without
level shifting or termination resistor networks in the
signal path. The outputs are 800mV, 100K-compatible
LVPECL with extremely fast rise/fall time guaranteed
to be less than 180ps.
The SY89859U features a patent-pending isolation
design that significantly improves on channel-to-
channel crosstalk-induced jitter performance.
The SY89859U operates from a 2.5V 5% or 3.3V
10% supply and is guaranteed over the full industrial
temperature range of 40C to +85C. The SY89859U
is part of Micrel's high-speed, Precision Edge
product
line.
All support documentation can be found on
Micrel's web site at:
www.micrel.com.
Precision Edge
Features
Selects between 1 of 8 inputs, and provides 2
precision, low skew 100K-compatible LVPECL
output copies
Low power: 150mW typ. (2.5V)
Guaranteed AC performance over temperature and
voltage:
DC to >2.5Gbps
DC to >2.5GHz
<690ps propagation delay
<180ps
t
r
/t
f
time
<20ps
skew
(output-to-output)
Unique, patent-pending channel-to-channel
isolation design provides superior crosstalk
performance
Ultra-low jitter design:
<1ps
RMS
random jitter
<10ps
PP
deterministic jitter
<10ps
PP
total jitter (clock)
<1ps
RMS
cycle-to-cycle jitter
<0.7ps
RMS
crosstalk-induced jitter
Unique, patented input termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
Power supply 2.5V 5% or 3.3V 10%
40C to +85C industrial temperature range
Available in 44-pin (7mm x 7mm) MLFTM package
Applications
Data communication systems
All SONET/SDH data/clock applications
All Fibre Channel applications
All Gigabit Ethernet applications
Micrel, Inc.
SY89859U
May 2005
M9999-052605
hbwhelp@micrel.com
or (408) 955-1690
2
Functional Block Diagram
Micrel,
Inc.
SY89859U
May 2005
M9999-052605
hbwhelp@micrel.com
or (408) 955-1690
3
Ordering Information
(1)
Part Number
Package Type
Operating
Range
Package Marking
Lead
Finish
SY89859UMG
MLF-44
Industrial
SY89859U with Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY89859UMGTR
(2)
MLF-44
Industrial
SY89859U with Pb-Free bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
44-Pin MLF
TM
(MLF-44)
Truth Table
SEL2 SEL1 SEL0
Q
/Q
L L L
IN0
/IN0
L L H
IN1
/IN1
L H L
IN2
/IN2
L H H
IN3
/IN3
H L L
IN4
/IN4
H L H
IN5
/IN5
H H L
IN6
/IN6
H H H
IN7
/IN7
Micrel,
Inc.
SY89859U
May 2005
M9999-052605
hbwhelp@micrel.com
or (408) 955-1690
4
Pin Description
Pin Number
Pin Name
Pin Function
20, 18
16, 14
13, 11
9, 7
5, 3
1, 43
42, 40
38, 36
IN0, /IN0
IN1, /IN1
IN2, /IN2
IN3, /IN3
IN4, /IN4
IN5, /IN5
IN6, /IN6
IN7, /IN7
Differential Inputs: These input pairs are the differential signal inputs to the device.
Inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each pin of
a pair internally terminates to a VT pin through 50. Note that these inputs will default
to an indeterminate state if left open. Please refer to the "Input Interface Applications"
section for more details.
19, 15
12, 8
4, 44
41, 37
VT0, VT1
VT2, VT3
VT4, VT5
VT6, VT7
Input Termination Center-Tap: Each side of the differential input pair terminates to a
VT pin. The VT pins provide a center-tap to a termination network for maximum
interface flexibility. See "Input Interface Applications" section for more details. For a
CML or LVDS inputs, the VT pin is left floating.
17
10
2
39
VREF-AC0
VREF-AC1
VREF-AC2
VREF-AC3
Reference Voltage: These outputs bias to V
CC
1.2V. They are used when AC
coupling the inputs (IN, /IN). For AC-coupled applications, connect VREF-AC to the
VT pin and bypass with a 0.01F low ESR capacitor to VCC. See "Input Interface
Applications" section for more details.
21
22
35
SEL0
SEL1
SEL2
The single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexer.
Note that this input is internally connected to a 25k pull-up resistor and will default
to a logic HIGH state if left open. The threshold voltage is V
TH
= V
CC
/2.
24, 27, 29, 32
VCC
Positive Power Supply. Bypass with 0.1F||0.01F low ESR capacitors and place as
close to each VCC pin as possible.
25, 26
30, 31
Q0, /Q0
Q1, /Q1
Differential Outputs: These 100K-compatible LVPECL output pairs are the outputs of
the device. Unused output pairs may be left open. Each output is designed to drive
800mV into 50 terminated to V
CC
2V.
23, 28, 33
GND
Exposed Pad
Ground. GND and exposed pad must both be connected to the same ground plane.
Micrel,
Inc.
SY89859U
May 2005
M9999-052605
hbwhelp@micrel.com
or (408) 955-1690
5
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .......................... 0.5V to +4.0V
Input Voltage
SEL0, SEL1, SEL2 .......................... 0.5V to V
CC
IN0, /IN0, IN1, /IN1,.../IN7, /IN7 ...... 0.5V to V
CC
LVPECL Output Current (I
OUT
)
Continuous................................................50mA
Surge ......................................................100mA
Termination Current
Source or sink current
VT0, VT1, VT2,...VT7.............................100mA
Input Current
Source or sink current
IN0, /IN0, IN1, /IN1,...IN7, /IN7 ................50mA
VREF Output Current
VREF-AC0, VREF-AC1..., VREF-AC3.......2mA
Lead Temperature (soldering, 20 sec.) .......... +260C
Storage Temperature (T
s
) ................. 65C to 150C
Operating Ratings
(2)
Supply Voltage (V
CC
).................. +2.375V to +2.625V
.................................................+3.0V to +3.6V
Ambient Temperature (T
A
)................ 40C to +85C
Package Thermal Resistance
(3)
MLFTM
(
JA
)
Still-Air ................................................ 24C/W
MLFTM
(
JB
)
Junction-to-Board ............................... 12C/W
DC Electrical Characteristics
(4)
T
A
= 40C to +85C, unless otherwise stated.
Symbol Parameter
Condition
Min
Typ
Max
Units
2.375
2.5
2.625
V
V
CC
Power
Supply
3.0
3.3
3.6
V
I
CC
Power Supply Current
No load, max. V
CC
60
85
mA
R
IN
Input Resistance (IN-to-V
T
)
45 50 55
R
DIFF_IN
Differential Input Resistance
(IN-to-/IN)
90 100 110
V
IH
Input High Voltage
(IN, /IN)
Note 5
V
CC
1.6
V
CC
V
V
IL
Input Low Voltage
(IN, /IN)
0
V
IH
0.1 V
V
IN
Input Voltage Swing
(IN, /IN)
See Figure 1a.
0.1 1.7
V
V
DIFF_IN
Differential Input Voltage Swing
|IN-to-/IN|
See Figure 1b.
0.2
V
V
T_IN
IN-to-V
T
(IN, /IN)
1.28
V
V
REF-AC
Output Reference Voltage
V
CC
1.3 V
CC
1.2 V
CC
1.1 V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
JA
and
JB
values are determined for a 4-layer board in still-air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V
IH
(min), not lower than 1.2V.
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