1
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
s
Two matched-delay outputs:
Bank A: undivided pass-through (QA)
Bank B: programmable divide by
2, 4, 8, 16 (QB0, QB1)
s
Matched delay: all outputs have matched delay,
independent of divider setting
s
Guaranteed AC performance:
>2.5GHz f
MAX
<250ps t
r
/t
f
<670ps t
pd
(matched delay)
<15ps within-device skew
s
Low jitter design
<1ps
rms
cycle-to-cycle jitter
<10ps
pp
total jitter
s
Power supply 3.3V or 2.5V
s
Unique patent-pending input termination and VT pin
for DC-coupled and AC-coupled inputs: any
differential inputs (LVPECL, LVDS, CML, HSTL)
s
TTL/CMOS inputs for select and reset
s
100K EP compatible LVPECL outputs
s
Parallel programming capability
s
Wide operating temperature range: 40
C to +85
C
s
Available in 16-pin (3mm
3mm) MLFTM package
FEATURES
APPLICATIONS
s
OC-3 to OC-192 SONET/SDH applications
s
Transponders
s
Oscillators
s
SONET/SDH line cards
1
Rev.: C
Amendment: /0
Issue Date:
June 2004
The SY89871U is a 2.5V/3.3V LVPECL output precision
clock divider capable of accepting a high-speed differential
clock input (AC or DC-coupled) CML, LVPECL, HSTL or
LVDS clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked lower speed version of the input clock (Bank B).
Available divider ratios are 2, 4, 8 and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A V
REF-AC
reference is included for AC-coupled applications.
The SY89871U includes two phase-matched output
banks. Bank A (QA) is a frequency-matched copy of the
input. Bank B (QB0, QB1) is a divided down output of the
input frequency. Bank A and Bank B maintain a matched
delay independent of the divider setting.
All support documentation can be found on Micrel's web
site at www.micrel.com.
FUNCTIONAL BLOCK DIAGRAM
Precision EdgeTM
Precision EdgeTM
SY89871U
2.5GHz ANY DIFF. IN-TO-LVPECL
PROGRAMMABLE CLOCK DIVIDER/
FANOUT BUFFER W/INTERNAL TERMINATION
TYPICAL PERFORMANCE
Precision Edge is a trademark of Micrel, Inc.
Micro
LeadFrame and MLF are trademarks of Amkor Technology, Inc.
IN
50
50
/IN
S0
S1
QB1
/QB1
QB0
/QB0
QA
/QA
/RESET
V
T
V
REF-AC
Divided
by
2, 4, 8
or 16
Decoder
/QB0
QB0
/QA
QA
QA@622MHz and QB@155.5MHz
4
622MHz
Output
155.5MHz
Output
2
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Operating
Package
Part Number
Type
Range
Marking
SY89871UMI
MLF-16
Industrial
871U
SY89871UMITR
(1)
MLF-16
Industrial
871U
Note:
1. Tape and Reel.
Pin Number
Pin Name
Pin Function
1, 2, 3, 4
QB0, /QB0
Differential Buffered Output Clocks: This differential output is a divided-down version of
QB1, /QB1
the input frequency and has a matched output delay with Bank A. Divided by 2, 4, 8, or 16.
See "Truth Table." Unused output pairs may be left floating.
5, 6
QA, /QA
Differential Buffered Undivided Output Clock.
7, 14
VCC
Positive Power Supply: Bypass with 0.1
F
0.01
F low ESR capacitors.
8
/RESET
Output Reset: Internal 25k
pull-up. Logic LOW will reset the divider select. See "Truth
Table." Input threshold is V
CC
/2.
12, 9
IN, /IN
Differential Input: Internal 50
termination resistors to VT input. See "Input Interface
Applications" section.
10
VREF-AC
Reference Voltage: Equal to V
CC
1.4V (approx.), and used for AC-coupled applications.
Maximum sink/source current is 0.5mA. See "Input Interface Applications" section.
11
VT
Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise,
see "Input Interface Application" section.
13
GND
Ground.
15, 16
S1, S0
Select Pins: See "Truth Table." LVTTL/CMOS logic levels. Internal 25k
pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is V
CC
/2.
PIN DESCRIPTION
1
2
3
4
12
11
10
9
16 15 14 13
5
6
7
8
QB0
/QB0
QB1
/QB1
IN
VT
VREF-AC
/IN
GND
VCC
S1
S0
/RESET
VCC
/QA
QA
16-Pin MLFTM (MLF-16)
/RESET
S1
S0
Bank A Output
Bank B Outputs
1
0
0
Input Clock
Input Clock
2
1
0
1
Input Clock
Input Clock
4
1
1
0
Input Clock
Input Clock
8
1
1
1
Input Clock
Input Clock
16
0
X
X
Input Clock
QB = LOW, /QB = HIGH
TRUTH TABLE
3
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .................................. 0.5V to +4.0V
Input Voltage (V
IN
) ............................... 0.5V to V
CC
+0.3V
PECL Output Current (I
OUT
)
Continuous ......................................................... 50mA
Surge ................................................................ 100mA
V
T
Current (I
VT
) ......................................................
100mA
Input Current IN, /IN (I
IN
) ..........................................
50mA
V
REF-AC
Sink/Source Current (I
VREF-AC
)
(3) ....................
2mA
Lead Temperature (soldering, 10 sec.) ..................... 220
C
Storage Temperature (T
S
) ....................... 65
C to +150
C
Operating Ratings
(2)
Supply Voltage (V
CC
) ............................ +2.375V to +3.63V
Ambient Temperature (T
A
) ......................... 40
C to +85
C
Package Thermal Resistance
(4)
MLFTM
(
JA
)
Still-Air ............................................................. 60
C/W
500lfpm ............................................................ 54
C/W
MLFTM
(
JB
)
Junction-to-board ............................................ 32
C/W
T
A
= 40
C to +85
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CC
Power Supply Voltage
2.37
3.60
V
I
CC
Power Supply Current
No load, max V
CC
.
50
75
mA
R
IN
Differential Input Resistance,
80
100
120
(IN, /IN)
V
IH
Input HIGH Voltage, (IN, /IN)
Note 6
0.1
V
CC
+0.3
V
V
IL
Input LOW Voltage, (IN, /IN)
Note 6
0.3
V
CC
+0.2
V
V
IN
Input Voltage Swing
Notes 6, 7
0.1
3.6
V
V
DIFF_IN
Differential Input Voltage Swing
Notes 6, 7, 8
0.2
V
|I
IN
|
Input Current, (IN, /IN)
Note 6
45
mA
V
REF-AC
Reference Voltage
Note 9
V
CC
1.525 V
CC
1.425 V
CC
1.325
V
Notes:
1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional
operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Due to the internal termination (see "Input Stucture Buffer") the input current depends on the applied voltages at IN, /IN and V
T
inputs. Do not apply
a combination of voltages that causes the input current to exceed the maximum limit.
7. See "Timing Diagram" for V
IN
definition. V
IN
(max.) is specified when V
T
is floating.
8. See "Typical Operating Characteristics" section for V
DIFF
definition.
9. Operating using V
IN
is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin.
DC ELECTRICAL CHARACTERISTICS
(5)
4
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
V
CC
= 3.3V
10% or 2.5V
5%; T
A
= 40
C to +85
C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
2.0
V
V
IL
Input LOW Voltage
0.8
V
I
IH
Input HIGH Current
125
20
A
I
IL
Input LOW Current
300
A
Note:
10. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameters are for
V
CC
= 2.5V. They vary 1:1 with V
CC
.
LVTTL/LVCMOS DC ELECTRICAL CHARACTERISTICS
(10)
V
CC
= 3.3V
10% or 2.5V
5%; T
A
= 40
C to +85
C, R
L
= 50
to V
CC
2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OH
Output HIGH Voltage
V
CC
1.145 V
CC
1.020 V
CC
0.895
V
V
OL
Output LOW Voltage
V
CC
1.945 V
CC
1.820 V
CC
1.695
V
V
OUT
Output Voltage Swing
550
800
1050
mV
V
DIFF_OUT
Differential Output Voltage Swing
1.10
1.6
210
V
(100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS
(10)
5
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
TIMING DIAGRAM
V
IN
Swing
/RESET
IN
/IN
/QB
QB
QA
/QA
t
PD
t
RR
V
CC/2
V
OUT
Swing
V
CC
= 3.3V
10% or 2.5V
5%; T
A
= 40
C to +85
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Output Toggle Frequency
Output Swing
400mV
2.5
GHz
Maximum Input Frequency
Note 12
3.2
GHz
t
PLH
Differential Propagation Delay
Input Swing < 400mV
460
580
710
ps
t
PHL
IN-to-QA or QB
Input Swing
400mV
420
550
670
ps
t
SKEW
Within-Device Skew (Differential)
Note 13
7
15
ps
QB0-to-QB1
Within-Device Skew (Differential)
Note 13
12
30
ps
QA-to-QB
Part-to-Part Skew (Differential)
Note 13
250
ps
T
jitter
Cycle-to-Cycle Jitter
Note 14
1
ps
rms
Total Jitter
Note 15
10
ps
pp
t
RR
Reset Recovery Time
600
ps
t
r
,
t
f
Output Rise/Fall Times
70
150
250
ps
(20% to 80%)
Notes:
11. Measured with 400mV input signal, 50% duty cycle, all loading with 50
to V
CC
2V, unless otherwise stated.
12. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output
2,
4,
8,
16) can accept an input frequency
>3GHz, while Bank A will be slew rate limited.
13. Skew is measured between outputs under identical transitions.
14. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
jitter_cc
=T
n
T
n+1
,
where T is the time between rising edges of the output signal.
15. Total jitter definition: with an ideal clock input, of frequency
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS
(11)
6
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
TYPICAL OPERATING CHARACTERISTICS
V
CC
= 3.3V, V
IN
= 400mV, T
A
= 25
C, unless otherwise stated.
0
100
200
300
400
500
600
700
800
900
0
500
1000
1500
2000
2500
3000
3500
QA AMPLITUDE (mV)
FREQUENCY (MHz)
QA Output Amplitude
vs. Frequency
0
100
200
300
400
500
600
700
800
900
0
200 400 600 800 1000 1200
PROPAGATION DELAY (ps)
INPUT SWING (mV)
IN to Q Propagation Delay
vs. Input Swing
300
400
500
600
700
-40 -20 0
20 40 60 80 100 120
PROPAGATION DELAY (ps)
TEMPERATURE (
C)
IN to Q Propagation Delay
vs. Temperature
1.25GHz Output
TIME (100ps/div.)
Output Swing
(100mV/div
.)
/Q
Q
2.5GHz Output
TIME (100ps/div.)
Output Swing
(100mV/div
.)
/Q
Q
622MHz Output
TIME (1ns/div.)
Output
Swing
(200mV/div
.)
/QB0
QB0
/QA
QA
155.5MHz Output
QA@622MHz and QB@155.5MHz
4
7
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING
INPUT BUFFER STRUCTURE
V
CC
GND
50
50
IN
V
T
/IN
1.86k
1.86k
1.86k
1.86k
Figure 2a. Simplified Differential Input Buffer
SY89871U
V
CC
GND
S0
S1
/RESET
R
25k
R
Figure 2b. Simplified TTL/CMOS Input Buffer
V
IN,
V
OUT
800mV
(typical)
1600mV (typical)
V
DIFF_IN
,
V
DIFF_OUT
Figure 1a. Single-Ended Swing
Figure 1b. Differential Swing
8
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
INPUT INTERFACE APPLICATIONS
CML
IN
/IN
VT
NC
GND
SY89871U
V
CC
V
CC
V
REF-AC
NC
Figure 3a. DC-Coupled CML
Input Interface
CML
IN
/IN
VT
GND
SY89871U
V
CC
V
CC
V
REF-AC
V
CC
0.01
F
Figure 3b. AC-Coupled CML
Input Interface
PECL
IN
/IN
VT
GND
SY89871U
V
CC
V
CC
V
REF-AC
NC
0.01F
V
CC
Note:
For 3.3V, R
pd
= 50
.
For 2.5V, R
pd
= 19
.
R
pd
Figure 3c. DC-Coupled PECL
Input Interface
V
CC
0.01F
PECL
IN
/IN
V
T
GND
SY89871U
V
CC
V
CC
GND
V
REF-AC
R
pd
R
pd
Note:
For 3.3V, R
pd
= 100
.
For 2.5V, R
pd
= 50
.
Figure 3d. AC-Coupled PECL
Input Interface
LVDS
IN
/IN
VT
NC
GND
SY89871U
V
CC
V
CC
V
REF-AC
NC
Figure 3e. LVDS
Input Interface
HSTL
IN
/IN
VT
GND
SY89871U
V
CC
V
CC
GND
NC
V
REF-AC
Figure 3f. HSTL
Input Interface
Part Number
Function
Data Sheet Link
SY89874U
2.5GHz Any Diff. In-to-LVPECL Programmable
http://www.micrel.com/product-info/products/sy89874u.shtml
Clock Divider and 1:2 Fanout Buffer
w/Internal Termination
MLFTM Application Note
http://www.amkor.com/products/notes_papers/mlf_appnote.pdf
HBW Solutions New Products and Applications
http://www.micrel.com/product-info/products/solutions.shtml
RELATED PRODUCT AND SUPPORT DOCUMENTATION
9
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
LVPECL OUTPUT TERMINATION RECOMMENDATIONS
R2
82
R2
82
Z
O
= 50
Z
O
= 50
+3.3V
+3.3V
V
t
= V
CC
--2V
R1
130
R1
130
+3.3V
Figure 4a. Parallel TerminationThevenin Equivalent
Note:
1. For +2.5V systems: R1 = 250
, R2 = 62.5
.
Z = 50
Z = 50
50
50
50
+3.3V
+3.3V
"source"
"destination"
R
b
C1 (optional)
0.01
F
V
CC
Figure 4b. Three-Resistor "YTermination"
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. R
b
resistor sets the DC bias voltage, equal to V
T
. For +3.3V systems R
b
= 46
to 50
. For +2.5V systems R
b
= 19
.
4. C1 is an optional bypass capacitor intended to compensate for any t
r
/t
f
mismatches.
+3.3V
+3.3V
Z
O
= 50
R2
82
+3.3V
+3.3V
R1
130
R1
130
R2
82
V
t
= V
CC
--2V
Q
/Q
R3
1k
R4
1.6k
V
t
= V
CC
--1.3V
Figure 4d. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. For +2.5V systems: R1 = 250
, R2 = 62.5
, R3 = 1.25k
, R4 = 1.2k
.
10
Precision EdgeTM
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
16 LEAD
MicroLeadFrameTM (MLF-16)
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heavy Copper Plane
Heavy Copper Plane
V
EE
V
EE
Heat Dissipation
PCB Thermal Consideration for 16-Pin MLFTM Package
(Always solder, or equivalent, the exposed pad to the PCB)
3.00BSC
2.75BSC
0.50 DIA
3.00BSC
12
max
SEATING
PLANE
2.75BSC
16
1
1
2
3
4
N
2
3
4
0.85
+0.15
0.65
0.65
+0.15
0.65
0.01
+0.04
0.01
0.23
+0.07
0.05
0.01
+0.04
0.01
0.42
+0.18
0.18
0.42
+0.18
0.18
0.23
+0.07
0.05
1.60
+0.10
0.10
PIN 1 ID
0.5 BSC
1.5 REF
0.42
+0.18
0.18
1.60
+0.10
0.10
0.40
+0.05
0.05
0.20 REF.
0.5BSC
SECTION "C-C"
SCALE: NONE
FOR EVEN TERMINAL/SIDE
TOP VIEW
BOTTOM VIEW
1. DIMENSIONS ARE IN mm.
2. DIE THICKNESS ALLOWABLE IS 0.305mm MAX.
3. PACKAGE WARPAGE MAX 0.05mm.
4. THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.20mm AND 0.25mm FROM TIP.
5. APPLIES ONLY FOR TERMINALS
C C
CL
4
Rev. 02
Package Notes:
1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form.
2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC.
1849 FORTUNE DRIVE
SAN JOSE, CA 95131
USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
2004 Micrel, Incorporated.
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