July 2000
ML2330
*
Selectable Dual 3V/3.3V/5V 8-Bit DACs
1
FEATURES
s
3V 10%, 3.3 10% or 5V 10% operation
s
Low supply current (3.5mA max)
s
Individual and full power down (down to 1A)
s
10Mb/s three-wire serial interface, compatible to SPI
and Microwire
s
8-pin SOIC package
s
Available in Extended Commercial temperature range
(20C to 70C) and Industrial temperture range
(40C to 85C)
s
Guaranteed monotonicity
GENERAL DESCRIPTION
The ML2330 Selectable Dual 3V/3.3V/5V 8-bit DACs are
dual voltage output digital-to-analog converters which can
be independently programmed, or powered down to
conserve power. The devices are intended for use in
portable or low power 3V systems where space is critical.
Programming access to the DACs is provided over a high
speed (10Mb/s), 3-wire serial interface which is compatible
to the SPITM and MicrowireTM data formats. In addition to
independent programming of the DAC output voltages,
each device may be powered down, independent of the
other DAC, to conserve power. Each DAC draws 2mA
maximum quiescent current when operating, and typically
less than 1A when powered down.
The device comes in an 8-pin SOIC package and in a
special Extended Commercial temperature range (20C
to 70C) or Industrial temperture range (40C to 85C).
BLOCK DIAGRAM
DAC A
R
E
G
CONTROL
AND
TIMING
VREF
DAC B
R
E
G
S
CLK
D
IN
CS
D
OUT
OUT B
OUT A
GND
VCC
POWER
DOWN
20k
20k
3
1
2
8
7
6
5
4
*Some Packages Are End Of Life Or Obsolete
ML2330
2
PIN CONFIGURATION
PIN DESCRIPTION
PIN NAME
FUNCTION
1
D
IN
Data In
2
S
CLK
Serial Clock
3
CS
Chip Select
4
D
OUT
Data Out
5
GND
Ground
6
OUT B
Output of DAC B
7
OUT A
Output of DAC A
8
V
CC
Positive Supply
ML2330
8-Pin SOIC (S08)
V
CC
OUT A
OUT B
GND
1
2
3
4
8
7
6
5
D
IN
S
CLK
CS
D
OUT
TOP VIEW
ML2330
3
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V
CC
) ................................................ 6.0V
GND ............................................... 0.3V to V
CC
+ 0.3V
Logic Inputs .................................... 0.3V to V
CC
+ 0.3V
Input Current per Pin ............................................ 25mA
Storage Temperature ................................ 65C to 150C
Package Dissipation at T
A
= 25C ........................ 750mW
Lead Temperature (Soldering 10 sec.)
SOIC .................................................................... 150C
OPERATING CONDITIONS
Supply Voltage (V
CC
)
ML2330ES2 ............................................... 3V 10%
ML2330ES3 ............................................ 3.3V 10%
ML2330ES5 ............................................... 5V 10%
Temperature Range
ML2330ES ............................................. 20C to 70C
ML2330IS .............................................. 40C to 85C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, T
A
= T
MIN
to T
MAX
, V
CC
= Operating Supply Voltage Range, f
CLK
= 10MHz R
L
= 1k,
(R
L
= 2k
W for V
CC
= 5V), C
L
= 100pF (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Converter
Resolution
8
bits
Integral Linearity Error
ILE
1.5
LSB
Differential Linearity Error
DLE
1
LSB
Offset Error
V
CC
= 3.3V or 3.0V
E Suffix
10
20
30
mV
I Suffix
5
20
35
mV
V
CC
= 5V
E Suffix
15
25
35
mV
I Suffix
10
25
40
mV
Gain Error
5
%FS
Analog Output
Output Drive Current
I
OUTPP
Full scale output
2
mA
Power Supply Rejection Ratio
PSRR
@00 & FF
40
dB
Digital and DC
Logic Input Low
V
IL
V
CC
= 3V, 3.3V, or 5V
0.8
V
Logic Input High
V
IH
V
CC
= 3V or 3.3V
2.0
V
V
CC
= 5V
2.8
V
Logic Input Low Current
I
IL
V
IN
= GND
1
A
Logic Input High Current
I
IH
V
IN
= V
CC
1
A
Logic Output Low
V
OL
I = 3.2mA
0.4
V
Logic Output High
V
OH
I = 0.4mA
2.4
V
Supply Current
I
CC
R
L
=
2.5
3.5
mA
Power Down Current
All digital inputs at
V
CC
= 3V
3
A
static 0V or V
CC
V
CC
= 5V
5
A
AC Performance
Settling Time
t
S
1/2 LSB
5
10
s
Slew Rate
1.4
V/s
Crosstalk
60
dB
Note 1: Limits are guaratneed by 100% testing, sampling or correlation with worst case test conditions.
ML2330
4
TIMING CHARACTERISTICS
(Serial Interface)
V
CC
= Operating Supply Voltage Range, C
L
= 50pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Converter
CS Fall to S
CLK
Setup Time
t
CSS
20
ns
S
CLK
Rise to CS
Rise Hold Time
t
CSH
50
ns
D
IN
to S
CLK
Rise Setup Time
t
DS
20
ns
D
IN
to S
CLK
Rise Hold Time
t
DH
20
ns
S
CLK
Frequency
f
CLK
10
MHz
S
CLK
Duty Cycle
40
60
%
S
CLK
to D
OUT
Valid
t
DO
V
CC
= 3.3V or 5V
30
60
ns
V
CC
= 3V
45
90
ns
Figure 1c. Interface Timing
CS
S
CLK
D
IN
D
OUT
*
*D
OUT
is the data from previous input.
A1
A0
P1
P0
D7
D6
D5
D4
D3
D2
D1
D0
D0
A1
A0
P1
P0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 1a. Connections for Microwire.
Figure 1b. Connections for SPI.
S
CLK
D
IN
D
OUT
CS
SK
SO
SI
I/O
ML2330
MICROWIRE
PORT
2
1
4
3
D
OUT
S
CLK
D
IN
CS
MISO
MOSI
SCK
I/O
ML2330
SPI
PORT
4
1
2
3
ML2330
5
The 4-bit address/control code configures the DAC as
shown in Table 1.
A1
A0
Function
0
0
No operation
0
1
Select control bits and DAC A
1
0
Select control bits and DAC B
1
1
Select control bits and both DACs
Table 1.1 Address Selection
P1
P0
Function
0
0
Normal
0
1
Power down DAC A
1
0
Power down DAC B
1
1
Power down entire chip
Table 1.2 Power Down Selection
DAC OPERATION
The DACs are implemented using an array of equal
current sources that are decoded linearly for the four most
significant bits to improve differential linearity and to
reduce output glitch around major carries. A voltage
difference between on-board bandgap reference voltage
and GND is converted to a reference current using an
internal resistor to set up the appropriate current level in
the DACs. The DACs output current is then converted to a
voltage output by an output buffer and a resistive network.
The matching among the on-chip resistors preserves the
gain accuracy between these conversions.
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The ML2330 communicates with microprocessors through
a synchronous, full-duplex, 3-wire interface (figure 1A &
B). At power on, the control registers are cleared and both
DACs have high impedance outputs. Data timing shown
in Figure 1C is sent MSB-first and can be transmitted in
one 4-bit and one 8-bit packet or in one 12-bit word. If a
16-bit control word is used, the first four bits are ignored.
The serial clock (S
CLK
) synchronizes the data transfer. Data
is transmitted and received simultaneously. Figure 2 shows
detailed serial interface timing. Note that the clock should
be low between updates. D
OUT
does not go into a high
impedance state if the clock idles or CS is high.
Serial data is clocked into the data registers in MSB-first
format, with the address and configuration information
preceding the actual DAC data. Data is sampled on the
S
CLK
's rising edge while CS is low. Data at D
OUT
is
clocked out 12.5 clock cycles later, on the S
CLK
's falling
edge.
Chip Select (CS) must be low to enable the read or write
operation. If CS is high, the interface is disabled and D
OUT
remains unchanged. CS must go low at least 10ns before
the first clock pulse to properly clock in the first bit. With
CS low, data is clocked into the ML2330's internal shift
register on the rising edge of the external serial clock. S
CLK
can be driven at rates up to 10MHz.
SERIAL INPUT DATA FORMAT AND
CONFIGURATION CODES
The 12-bit serial input format shown in Figure 3 comprises
two DAC address bits (A1, A0), two power down control
bits (P1, P0) and eight bits of data (D7 . . . D0).
DOUT
A1 A0 P1 D7 . . . D0
DIN
Figure 3. Serial Input Format
Figure 2. Detail Interface Timing
CS
S
CLK
D
IN
D
OUT
t
CSS
t
DS
t
DH
t
DO
t
CSH
ML2330
6
VOLTAGE REFERENCE
A bandgap voltage reference is incorporated on the
ML2330. It is trimmed for zero temperature coefficient at
25C to minimize output voltage drift over the specified
operating temperature range.
OUTPUT BUFFER AND GAIN SETTING
The output buffer converts the DAC output current to a
voltage output using a resistive network. The outputs can
swing from GND +0.02V to either 2.02V (3V) or 4.02V
(5V). The DAC transfer function is:
V
K DATA
OUT
=
+
256
0 02
.
where K = 2 if V
CC
= 3V and K = 4 if V
CC
= 5V
In the 3V operation, the amplifier outputs will settle to
1/2LSB in 10s when loads are greater than 1k (2k for
5V operation) and capacitive loads smaller than 100pF.
GAIN ERROR
The graph below shows how gain error varies with
temperature when V
CC
= 3.3V.
POWER DOWN MODE
There are three power-down modes in the ML2330. By
clearing the control bits P1-P0 (Table 3.2), the entire chip
will be powered down with a supply current less than
5A. Individual DACs can also be powered down to save
power (1.75mA per DAC).
40
20
0
20
40
60
80
100
TEMPERATURE ( C)
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
GAIN ERROR (%)
Gain Error vs Temperature
ML2330
7
PART NUMBER
V
CC
TEMPERATURE RANGE
PACKAGE
ML2330ES2
3V
20C to 70C
8-Pin SOIC (S08)
ML2330ES3 (End Of Life)
3.3V
20C to 70C
8-Pin SOIC (S08)
ML2330ES5 (End Of Life)
5V
20C to 70C
8-Pin SOIC (S08)
ML2330IS2
3V
40C to 85C
8-Pin SOIC (S08)
ML2330IS3 (Obsolete)
3.3V
40C to 85C
8-Pin SOIC (S08)
ML2330IS5
5V
40C to 85C
8-Pin SOIC (S08)
PHYSICAL DIMENSIONS
inches (millimeters)
SEATING PLANE
0.148 - 0.158
(3.76 - 4.01)
PIN 1 ID
0.228 - 0.244
(5.79 - 6.20)
0.189 - 0.199
(4.80 - 5.06)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.015 - 0.035
(0.38 - 0.89)
0.059 - 0.069
(1.49 - 1.75)
0.004 - 0.010
(0.10 - 0.26)
0.055 - 0.061
(1.40 - 1.55)
8
0.006 - 0.010
(0.15 - 0.26)
0 - 8
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
Package: S08
8-Pin SOIC
5/6/97 Printed in U.S.A.
ORDERING INFORMATION
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or
design. Micro Linear does not assume any liability arising out of the application or use of any product
described herein, neither does it convey any license under its patent right nor the rights of others. The
circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no
warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of
others, and will accept no responsibility or liability for use of any application herein. The customer is urged
to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017;
5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
DS2330-01
PDF 
ZIP