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Электронный компонент: ML2713CH

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GENERAL DESCRIPTION
The ML2713 combined with the ML2712 forms an
FSK (Frequency Shift Keying) 2.4 GHz radio chipset
for systems based on IEEE802.11 and other wireless
communication protocols using the 2.4HGz ISM band.
The ML2713 is the complete IF section of Micro Linear's
2.4GHz frequency hopping, half duplex radio transceiver
chipset. The chip's down conversion super-heterodyne
receiver circuit contains an image reject down-convert
mixer, a limiter, a discriminator, a receive data filter and
a tracking A/D converter. The chips transmit circuit
contain a 6 bit D/A converter to digitally modulate the IF,
an anti alias filter and an image reject up-convert mixer.
FEATURES
n Highly integrated IF transceiver
n Data rates up to 4Mbps
n Integrated discriminator and filter alignment circuits
n High signal to noise ratio at the discriminator output
n Received signal strength indicator (RSSI)
n D/A Converter for digitally generated IF
n Low sleep mode current - typically less than 1mA
n 3.0V to 5.5V operation
n Fast 10msec switch time between transmit and receive
modes
n 48 Pin TQFP, 7mm body
ML2731
Bias
Controller
Transmit
Power
Amplifier
R. C.
Loop
Filter
Control
Circuits
DC
Reg
Quad &
Filter
Auto Align
Discrim-
inator
2LO Loop
Filter &
Tank Circuit
1LO Loop
Filter &
Tank Circuit
+
DAC
Data Filter
Rx Out
D/A
Input
Control
Interface
32MHz
Clock
Baseband
Controller
(e.g., MSM7730B)
Reference
Frequency
Input
ML2713
DC
Restore
3
6
Image Reject Rx IF
Downconverter
Image Reject Tx
IF Upconverter
ML2712
Tx Regulator
Output
2LO
Input
RSSI
Limiter
APPLICATIONS
n 2.4GHz FSK radios
n PC Card and FlashCard Wireless Transceivers
n Systems based on IEEE802.11 1Mbps and 2Mbps
Standard
n TDMA Radio IF circuits
SIMPLIFIED BLOCK DIAGRAM
ML2713 Radio IF Transceiver
January, 2000
PRELIMINARY DATASHEET
PRELIMINARY
ML2713
2
January, 2000
PRELIMINARY DATASHEET
PRELIMINARY
TABLE OF CONTENTS
WARRANTY
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness
of the contents of this publication and reserves the right to make changes to specifications and product
descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any
patents or other intellectual property rights is granted by this document. The circuits contained in this
document are offered as possible applications only. Particular uses or applications may invalidate some of
the specifications and/or product descriptions contained herein. The customer is urged to perform its own
engineering review before deciding on a particular application. Micro Linear assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear
products including liability or warranties relating to merchantability, fitness for a particular purpose, or
infringement of any intellectual property right. Micro Linear products are not designed for use in medical,
life saving, or life sustaining applications.
Micro Linear 2000. is a registered trademark of Micro Linear Corporation. All other trademarks are the
property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611;
4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017;
5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167;
5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168;
5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723;
5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
General Description ................................................................................................................................................... 1
Applications ............................................................................................................................................................... 1
Features ...................................................................................................................................................................... 1
Simplified Block Diagram .......................................................................................................................................... 1
Block Diagram ........................................................................................................................................................... 3
Pin Configuration ....................................................................................................................................................... 4
Pin Descriptions ......................................................................................................................................................... 4
Functional Description ............................................................................................................................................... 7
Introduction .............................................................................................................................................................. 7
Operational Modes .................................................................................................................................................. 8
Mode Control ........................................................................................................................................................... 8
Filter Align Mode ..................................................................................................................................................... 8
Receive Mode ......................................................................................................................................................... 12
Sleep Mode .............................................................................................................................................................. 14
Test Mode Control .................................................................................................................................................... 14
Absolute Maximum Ratings ........................................................................................................................................ 15
Electrical Characteristics ............................................................................................................................................ 15
Operating Conditions ................................................................................................................................................. 15
Physical Dimensions .................................................................................................................................................. 20
Ordering Information .................................................................................................................................................. 20
ML2713
3
January, 2000
PRELIMINARY DATASHEET
PRELIMINARY
BLOCK DIAGRAM
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ML2713
4
January, 2000
PRELIMINARY DATASHEET
PRELIMINARY
TOP VIEW
ML2713
48-Pin TQFP (H48-7)
NC
DPS
DPSB
VCC4
REG
MS2
BPO
BPOB
GND
1IF
1IF
VCC2
DD4
DD3
DD2
DD1
DD0
VCC1
VCC2
CMO
GND
VCC3
NC
NC
13 14 15
NC
DD5
SLICE
MS1
VDC
DFO2
DFI2
DFO1
DFI1
GND
DISCO
MS3
RS
TS
LOE
GND
RSSI
GND
BPI
BPIB
VCC2
2LO
LON2
VCC2
16 17
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
PIN DESCRIPTIONS
POWER AND GROUND
6, 7
VCC1
POWER
Voltage supply for digital I/O circuits. VCC1 should be greater than or
equal to VCC2, VCC3, and VCC4 in normal operation
21, 24, 25 VCC2
POWER
Voltage supply for receive image reject down-converter and transmit
image reject up-converter
10
VCC3
POWER
Voltage supply for D/A converter, comparator, mode control, and
alignment circuits
33
VCC4
POWER
Voltage supply for limiters, discriminator, data filter, and transmit
regulator
9
GND
GND
Ground for VCC1
18, 28
GND
GND
Ground for VCC2
16
GND
GND
Ground for VCC3
39
GND
GND
Ground for VCC4
CONTROL
13
RS
I (CMOS)
Receive mode enable. This CMOS input is referenced to VCC1 and has
an on-chip pull-up. See Table 1 for operation
14
TS
I (CMOS)
Transmit mode enable. This CMOS input is referenced to VCC1 and has
an on-chip pull-up. See Table 1 for operation.
15
LOE
I (CMOS)
Chip enable and filter align control. This CMOS input is referenced to
VCC1 and has an on-chip pull up. The pin must be low for the IC to
operate in either transmit, receive or align modes. See Table 1 for
operation
Pin #
Signal Name
I/O Type
Description
PIN CONFIGURATION
ML2713
5
January, 2000
PRELIMINARY DATASHEET
PRELIMINARY
PIN DESCRIPTIONS (CONTINUED)
Pin #
Signal Name
I/O Type
Description
CONTROL (continued)
45
MS1
MODE SELECT
Auto filter alignment disable. Tie to VCC4 to disable the on-chip filter
alignment. Tie to ground for normal operation
31
MS2
MODE SELECT
Receive A/D converter disable. Tie MS2 to VCC2 to disable the on-chip
comparator and D/A converter in the receive mode. The D/A will still
be enabled in the transmit mode. Tie to ground for normal operation
37
MS3
MODE SELECT
Test mode control pin. Tie this pin to ground at all times
RECEIVE
8
CMO
O (CMOS)
Comparator output. Active in receive mode, this CMOS output that is
referenced to VCC1 and has a nominal drive capability of 10mA
17
RSSI
O(ANLG)
Receive Signal Strength Indicator. This output has a nominal 1Volt
range. The RSSI voltage decreases with increasing received signal
level. The RSSI output has a 10k source impedance. It is referred to
VCC2
46
SLICE
I(CMOS)
DC time constant restore control. This input controls whether VDC is in
the hold or acquire mode. A high on this pin puts VDC in the acquire
mode, low puts VDC in the hold mode. This CMOS input is referred to
VCC1
RECEIVE AND TRANSMIT
47
DD5
I (CMOS)
Six data inputs to Digital to Analog Converter. Inputs are not latched.
DD5 is the most significant bit (MSB).
1
DD4
I (CMOS)
DD4
2
DD3
I (CMOS)
DD3
3
DD2
I (CMOS)
DD2
4
DD1
I (CMOS)
DD1
5
DD0
I (CMOS)
DD0 is the least significant bit (LSB)
22
2LO
23
2LOB
I(ANLG)
2LO input. These pins are connected to a differential input stage that is
connected in a common base configuration. A pull-down resistor with a
nominal value of 4k is required on each pin to bias this input. The pull
down resistors are included on the ML2712 and do not need to be added
if that chip is used. The nominal differential input impedance is 200
W
26
1IF
27
1IFB
I/O(ANLG)
Receive 1IF input and transmit 2IF output. These pins are bi-directional
I/O are connected to the receive input amplifier and transmit output
amplifier. These pins have a nominal differential impedance of 340
W
set by on-chip resistances
TRANSMIT
32
REG
O (ANLG)
Transmit regulator output. This output of the on-chip regulator is
enabled in transmit mode. The nominal output voltage of the regulator
is 2.8V and drives current up to 25mA. The pin requires a de-coupling
capacitor with a nominal value 100nF
FILTERS - RECEIVE
35
DPS
34
DPSB
ANLG
Discriminator phase shift. These pins connect to the external
discriminator phase shift filter. These pins have a nominal differential
impedance of 600
W set by on-chip resistors