February 1998
ML4621
Data Quantizer
GENERAL DESCRIPTION
The ML4621 data quantizer is a low noise, wideband
monolithic IC designed specifically for signal recovery
applications in fiber-optic receiver systems. It contains a
two stage wideband limiting amplifier which is capable
of accepting an input signal as low as 2mV with a 55dB
dynamic range. This high level of sensitivity is achieved
by using a DC restoration feedback loop which nulls any
offset voltage produced in the limiting amplifier.
The output stage is a high speed comparator circuit with
both TTL and ECL outputs. An enable pin is included for
added control.
The minimum signal discriminator circuit provides a link
monitor function with a user selectable reference voltage.
This circuit monitors the peaks of the input signal and
provides a logic level output indicating when the input
falls below an acceptable level. This output can be used
to disable the quantizer and/or drive an LED, providing a
visible link status.
BLOCK DIAGRAM
(Pin Configuration Shown is for PLCC Version)
FEATURES
s
50MHz minimum bandwidth for data rates of up to
100MBd
s
Can be powered by either 5V providing TTL level
outputs, or -5.2V providing ECL level outputs
s
Low noise design: 25V RMS over 50MHz noise
bandwidth
s
Adjustable link monitor function
s
Wide 55dB input dynamic range
s
10ns minimum input pulse
1
21
18
VIN+
VIN
VDC
VREF
VTHADJ
GND
VCC TTL
GND TTL
TTL OUT
CMP ENABLE
VCC
CPEAK
ISET
INOM
CF1
VOUT+
VOUT
A1
A2
DC
AMP
ECL
CMP
TTL
CMP
FILTER
REF
THRESHOLD
GENERATOR
CF2
MINIMUM
SIGNAL
DISCRIMINATOR
CMP+
ECL+
ECL
CMP
ECL LINK MON
TTL LINK MON
22
6
5
8
23
27
26
24
28
19
20
3
1
2
17
16
10
11
13
9
12
14
Please See ML4622/ML4624 for New Designs
ML4621
2
PIN CONFIGURATION
1
2
3
4
5
6
7
24
23
22
21
20
19
18
ECL LINK MON
TTL LINK MON
CMP ENABLE
VIN
VIN+
VDC
CF2
CF1
VOUT
VOUT+
CMP+
CMP
VCC
INOM
ISET
CPEAK
VREF
VTH ADJ
GND
TTL OUT
VCC TTL
GND TTL
ECL+
ECL
TOP VIEW
ML4621
24-Pin Narrow DIP (P24N)
8
9
10
11
12
17
16
15
14
13
4
3
2
1
28
27
26
12
13
14
15
16
17
18
TOP VIEW
ML4621
28-Pin PLCC (Q28)
VIN
VIN+
NC
VDC
CF2
CF1
VOUT
V
OUT
+
CMP+
CMP
NC
ECL
ECL+
GND TTL
NC
CPEAK
VREF
VTH ADJ
GND
TTL OUT
VCC TTL
NC
CMP ENABLE
TTL LINK MON
ECL LINK MON
V
CC
I NOM
I SET
25
24
23
22
21
20
19
5
6
7
8
9
10
11
ML4621
3
PIN DESCRIPTION
(Pin Number in Parenthesis is for DIP Version)
PIN
NAME
FUNCTION
1 (1)
ECL LINK MON ECL link monitor output. Signal
is low when the V
IN
+ and V
IN
inputs exceed the minimum
threshold set by a voltage on
V
TH
ADJ. Signal is high when
input signal level is below that
threshold.
2 (2)
TTL LINK MON TTL link monitor output. Same
logic function as the ECL LINK
MON. Capable of driving a
10mA LED indicator. This pin is
normally tied to CMP ENABLE.
3 (3)
CMP ENABLE
Low voltage at this TTL input
enables both the ECL and TTL
outputs. A high TTL voltage
disables the comparator output
with ECL+ high, ECL low, and
TTL OUT high.
5 (4)
V
IN
This input should be capacitively
coupled to the input source or to
ground. (Input resistance is
approximately 8k
).
6 (5)
V
IN
+
This input should be capacitively
coupled to the input source or to
ground. (Input resistance is
approximately 8k
).
8 (6)
VDC
An external capacitor on this pin
integrates an error signal which
nulls the offset of the input
amplifier. If the DC feedback
loop is not being used, this pin
should be connected to V
REF
.
9 (7)
CF2
A capacitor from this pin to
ground controls the maximum
bandwidth of the amplifier to
accommodate lower operating
frequencies.
10 (8) CF1
The capacitor on this pin should
match the one on CF2.
11 (9) V
OUT
-
Negative output of the amplifier,
which is normally tied to CMP.
12 (10) V
OUT
+
Positive output of the amplifier,
which is normally tied to CMP+.
13 (11) CMP+
Comparator input pin. Open base
configuration relies on the DC
bias of the amp output to set
proper DC operating voltage.
Reestablish voltage if filtering is
used between V
OUT
+ and CMP+.
PIN
NAME
FUNCTION
14(12) CMP
Comparator input pin. Open base
configuration relies on the DC
bias of the amp output to set the
proper DC operating voltage.
Reestablish voltage if filtering is
used between V
OUT
and CMP.
16(13) ECL
ECL comparator negative output.
17(14) ECL+
ECL comparator positive outout.
18(15) GND TTL
Negative supply for the TTL
comparator stage. If the TTL
output is not necessary, connect
GND TTL and V
CC
TTL to V
CC
.
19(16) V
CC
TTL
Positive supply for the TTL
comparator stage. If the TTL
output is not necessary, connect
GND TTL and V
CC
TTL to V
CC
.
20(17) TTL OUT
TTL data output (totem pole type
output stage).
21(18) GND
Negative supply. Connect to
5.2V for ECL operation, or to
source ground for TTL operation.
22(19) V
TH
ADJ
This input sets the minimum
amplitude of the input signal
required to cause the link
monitors to go low.
23(20) V
REF
A 2.5V reference with respect to
GND.
24(21) C
PEAK
A capacitor from this pin to GND
determines the link monitor
response time.
26(22) I
SET
Current into an internal diode
connected between this pin and
GND is turned around and pulled
from C
PEAK
. This pin is normally
connected to I
NOM
.
27(23) I
NOM
Sets a current of approximately
125A when connected to I
SET
.
28(24) V
CC
Positive supply. Connect to
source ground for ECL operation,
or to 5V for TTL operation.
ML4621
4
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
CC
= 5V 5%, GND = 0V, T
A
= Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
CC1
V
CC
Supply Current
V
CC
TTL = GND TTL = V
CC
65
100
mA
I
CC2
V
CC
Supply Current
V
CC
TTL = V
CC
70
110
mA
(TTL OUT Enabled)
GND TTL = GND
I
V
REF
V
REF
Output Current
5.0
0.5
mA
V
REF
Reference Voltage
2.40
2.55
2.65
V
A
V
A1, A2 Amplifier Gain
V
IN
= 5mV
75
V/V
V
IN
Input Signal Range
2
1400
mV
P-P
V
TH
ADJ
External Voltage at V
TH
ADJ to set V
TH
1
2.5
V
Range
V
OS
Input Offset
VDC = V
REF
(DC Loop Inactive)
3
mV
E
N
Input Referred Noise
50MHz BW
25
V
BW
3dB Bandwidth
50
65
MHz
V
IN
PW
Minimum Input Pulsewidth
10
ns
R
IN
Input Resistance
V
IN
+, V
IN
8
k
t
PD
AMP
Amplifier Propagation Delay Time
From V
IN
+, V
IN
to V
OUT
+, V
OUT
4
8
ns
V
IN
+, = 10mV
P-P
t
PD
ECL
ECL Comparator Propagation Delay Time
From CMP+, CMP to ECL+, ECL
4
8
ns
V
IN
+, = 10mV
P-P
t
PD
TTL
TTL Comparator Propagation Delay Time
From ECL+, ECL to TTL OUT
4
8
ns
V
IN
+, = 10mV
P-P
R
V
TH
ADJ
V
TH
ADJ Input Resistance
6.8
k
I
V
OUT
V
OUT
+, V
OUT
Output Current
3
mA
I
CMP
CMP+, CMP Leakage Current
25
A
VCM
CMP
CMP+, CMP Common Mode Range
GND + 2
V
CC
1
V
ECL V
OH
ECL+, ECL Output High Voltage
With 200
Load Tied to V
CC
2V
3.90
4.30
V
T
A
= 25C
ECL V
OL
ECL+, ECL Output Low Voltage
With 200
Load Tied to V
CC
2V
3.11
3.38
V
T
A
= 25C
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
V
CC
GND ................................................ 0.3V to 7.0V
V
CC
TTL GND TTL ................................... 0.3V to 7.0V
GND ............................................... 0.3V to V
CC
+ 0.3V
Junction Temperature .............................................. 150C
Storage Temperature Range ..................... 65C to 150C
Lead Temperature (Soldering, 10 sec) ..................... 260C
Thermal Resistance (
JA
)
24 Pin Narrow PDIP ......................................... 54C/W
28 Pin PLCC ..................................................... 68C/W
OPERATING CONDITIONS
Temperature Range ....................................... 0C to 70C
5.2V Supply Range ...................................... 5.2V 5%
+5V Supply Range ......................................... 5.0V 5%
ML4621
5
ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
A
V
ECL
ECL CMP Gain
100
V/V
TTL V
OH
TTL Output High Voltage
V
CC
TTL = 5V, I
OH
= 50A
2.4
V
TTL V
OL
TTL Output Low Voltage
V
CC
TTL = 5V, I
OL
= 2mA
0.4
V
TTL V
IH
TTL Input High Voltage Level
2.0
V
TTL V
IL
TTL Input Low Voltage Level
0.8
V
TTL I
IH
TTL Input High Current Level
V
IH
= 2.4V
50
50
A
TTL I
IL
TTL Input Low Current Level
V
IH
= 0.4V
1.6
0
mA
I
NOM
I
NOM
= I
SET
125
A
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
PDF 
ZIP