PWR
GND
3
1
L1
V
BAT
V
IN
GND
V
L
C
OUT
2
8
REGULATION
&
SHUTDOWN
CONTROL
FROM POWER
MANAGEMENT
FEEDBACK
5
V
OUT
SHDN
6
BOOST
CONTROL
*C
IN
V
OUT
4
SENSE
R
1
R
2
C
FF*
August 2000
ML4775
Adjustable Output Low Voltage
Boost Regulator with Shutdown
1
*Optional
BLOCK DIAGRAM
GENERAL DESCRIPTION
The ML4775 is a boost regulator designed for DC to DC
conversion in 1 to 3 cell battery powered systems. The
combination of BiCMOS process technology, internal
synchronous rectification, variable frequency operation,
and low supply current make the ML4775 ideal for 1 cell
applications. The ML4775 is capable of start-up with input
voltages as low as 1V, and the output voltage can be set
anywhere between 2.5V and 5.5V by an external resistor
divider connected to the SENSE pin.
Unlike regulators using external Schottky diodes, the
ML4775 isolates the load from the battery when the
SHDN pin is high. This is accomplished by an integrated
synchronous rectifier which eliminates the need for an
external Schottky diode and provides a lower forward
voltage drop, resulting in higher conversion efficiency.
In addition, low quiescent battery current and variable
frequency operation result in high efficiency even at light
loads. The ML4775 requires a minimum number of
external components to build a very small regulator circuit
capable of achieving conversion efficiencies in excess of
90%.
FEATURES
s
Guaranteed start-up and operation at 1V input
s
Pulse Frequency Modulation and Internal Synchronous
Rectification for high efficiency
s
Isolates the load from the input during shutdown
s
Minimum external components
s
Low ON resistance internal switching FETs
s
Micropower operation
s
Adjustable output voltage (2.5V to 5.5V)
2
ML4775
PIN CONNECTION
PIN DESCRIPTION
PIN
NO.
NAME
FUNCTION
1
VIN
Battery input voltage
2
SHDN
Pulling this pin high shuts down the
regulator, isolating the load from the
input
3
GND
Analog signal ground
4
SENSE
Programming pin is for setting the
output voltage
PIN
NO.
NAME
FUNCTION
5
VOUT
Boost regulator output
6
VL
Boost inductor connection
7
N/C
No connection
8
PWR GND Return for the NMOS output
transistor
ML4775
8-Pin SOIC (S08)
1
2
3
4
8
7
6
5
VOUT
COMP
VREF
BURST
GND
VL
BURST
VIN
TOP VIEW
3
ML4775
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VIN = Operating Voltage Range, TA = Operating Temperature Range (Note 1).
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNITS
SUPPLY
VIN Quiescent Current
VIN = VOUT 0.2 V
55
65
A
VIN = 4.8V, SHDN = VIN
20
30
A
VOUT Quiescent Current
8
12
A
VL Quiescent Current
1
A
PFM REGULATOR
Pulse Width (TON)
8.9
10
11.1
s
SENSE Comparator
194
200
206
mV
Threshold Voltage (VSENSE)
Load Regulation
See Figure 1
VIN = 1.2V, IOUT - 20mA
4.85
5.0
5.15
V
VIN = 2.4V, IOUT - 105mA
4.85
5.0
5.15
V
Undervoltage Lockout Threshold
0.85
1
V
SHUTDOWN
Input Bias Current
100
100
nA
Shutdown Threshold
180
200
220
mV
Shutdown Hysteresis
50
70
mV
OPERATING CONDITIONS
Temperature Range
ML4775CS ................................................ 0C to 70C
ML4775ES ............................................ 20C to 70C
VIN Operating Range
ML4775CS .................................. 1.0V to VOUT 0.2V
ML4775ES .................................. 1.1V to VOUT 0.2V
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.
VOUT .......................................................................... 7V
Voltage on any other pin ..... GND 0.3V to VOUT +0.3V
Peak Switch Current, I(PEAK) .................................... 1.5A
Average Switch Current, I(AVG) ............................ 300mA
Junction Temperature ............................................. 150C
Storage Temperature Range .................... 65C to 150C
Lead Temperature (Soldering 10 sec.) .................... 260C
Thermal Resistance (
qJA) ................................... 160C/W
Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
4
ML4775
Figure 2. PFM Regulator Block Diagram.
Figure 1. Application Test Circuit.
I
OUT
100
F
100
F
V
IN
27
H
(Sumida CD75)
V
OUT
V
IN
SHDN
GND
SENSE
PWR GND
N/C
V
L
V
OUT
39pF
4k
96k
+
6
V
IN
10
s
ONE SHOT
START-UP
R
S
Q
V
L
L1
Q2
A2
A1
200mV
Q1
R1
R2
5
C
OUT
+
V
OUT
+
V
OUT
SHUTDOWN
Q3
4
SENSE
5
ML4775
FUNCTIONAL DESCRIPTION
The ML4775 combines Pulse Frequency Modulation
(PFM) and synchronous rectification to create a boost
converter that is both highly efficient and simple to use.
A PFM regulator charges a single inductor for a fixed
period of time and then completely discharges before
another cycle begins, simplifying the design by
eliminating the need for conventional current limiting
circuitry. Synchronous rectification is accomplished by
replacing an external Schottky diode with an on-chip
PMOS device, reducing switching losses and external
component count.
REGULATOR OPERATION
A block diagram of the boost converter is shown in
Figure 2. The circuit remains idle when V
OUT
is at or
above the desired output voltage, drawing 55A from
V
IN
, and 8A from V
OUT
through the feedback resistors
R1 and R2. When V
OUT
drops below the desired output
level, the output of amplifier A1 goes high, signaling the
regulator to deliver charge to the output. Since the
output of amplifier A2 is normally high, the flip-flop
captures the A1 set signal and creates a pulse at the gate
of the NMOS transistor Q1. The NMOS transistor will
charge the inductor L1 for 10s, resulting in a peak
current given by:
I
T
V
L
s V
L
L PEAK
ON
IN
IN
(
)
=
1
10
1
(1)
For reliable operation, L1 should be chosen so that
I
L(PEAK)
does not exceed 1.5A.
When the one-shot times out, the NMOS transistor
releases the V
L
pin, allowing the inductor to fly-back and
momentarily charge the output through the body diode
of PMOS transistor Q2 in series with shutdown transistor
Q3. But, as the voltage across the PMOS transistor
changes polarity, its gate will be driven low by the
current sense amplifier A2, causing Q2 to short out its
body diode. The inductor then discharges into the load
through Q2. The output of A2 also serves to reset the
flip-flop and one-shot in preparation for the next
charging cycle. A2 releases the gate of Q2 when its
current falls to zero. If V
OUT
is still low, the flip-flop will
immediately initiate another pulse. The output capacitor
(C1) filters the inductor current, limiting output voltage
ripple. Inductor current and one-shot waveforms are
shown in Figure 3.
SHUTDOWN
The ML4775 output can be shut down by pulling the
SHDN pin high. When SHDN is high, the regulator stops
switching, the control circuitry is powered down, and
the body diode of the PMOS synchronous rectifier is
disconnected from the output, allowing the output
voltage to drop below the input voltage. This feature is
unique to the ML4775, as most boost regulators use
external Schottky diode rectifier which cannot be
disconnected during shutdown. Leaving the Schottky
diode connected causes excess power dissipation in the
load during shutdown because the Schottky conducts
whenever the output voltage drops 300mV below the
input voltage.
DESIGN CONSIDERATIONS
INDUCTOR
Selecting the proper inductor for a specific application
usually involves a trade-off between efficiency and
maximum output current. Choosing too high a value will
keep the regulator from delivering the required output
current under worst case conditions. Choosing too low a
value causes efficiency to suffer. It is necessary to know
the maximum required output current and the input
voltage range to select the proper inductor value. The
maximum inductor value can be estimated using the
following formula:
L
V
T
V
I
MAX
IN MIN
ON MIN
OUT
OUT MAX
=
(
)
(
)
(
)
2
2
(2)
where
h is the efficiency, typically between 0.8 and 0.9.
Note that this is the value of inductance that just barely
delivers the required output current under worst case
conditions. A lower value may be required to cover
inductor tolerance, the effect of lower peak inductor
currents caused by resistive losses, and minimum dead
time between pulses.
Another method of determining the appropriate inductor
value is to make an estimate based on the typical
performance curves given in Figures 4 and 5. Figure 4
shows maximum output current as a function of input
voltage for several inductor values. These are typical
performance curves and leave no margin for inductance
and ON-time variations. To accommodate worst case
conditions, it is necessary to derate these curves by at
least 10% in addition to inductor tolerance.
For example, a two cell to 5V application requires 80mA
of output current while using an inductor with 15%
tolerance. The output current should be derated by 25%
to 100mA to cover the combined inductor and ON-time
tolerances. Assuming that 2V is the end of life voltage of
a two cell input, Figure 4 shows that with a 2V input, the
ML4775 delivers 100mA with a 27H inductor.
Figure 3. PFM Inductor Current Waveforms and Timing.
Q(ONE SHOT)
Q1 ON
Q1 ON
Q2
ON
Q2
ON
INDUCTOR
CURRENT
Q1 & Q2 OFF
6
ML4775
1.0
3.0
I
OUT
(mA)
2.0
400
300
200
100
0
0
V
IN
(V)
ML4775 (V
OUT
= 3.3V)
4.0
5.0
L = 27H
L = 15H
L = 56H
1.0
3.0
I
OUT
(mA)
2.0
400
300
200
100
0
0
V
IN
(V)
ML4775 (V
OUT
= 5V)
4.0
5.0
L = 27H
L = 15H
L = 56H
Figure 4. Output Current vs Input Voltage.
Figure 5. Typical Efficiency as a Function of V
IN
.
1.0
3.0
4.0
EFFICIENCY (%)
2.0
100
90
80
70
60
50
0
V
IN
(V)
ML4775 (V
OUT
= 5V)
5.0
L = 56
H
L = 27
H
L = 15
H
1.0
3.0
EFFICIENCY (%)
2.0
100
90
80
70
60
50
0
V
IN
(V)
ML4775 (V
OUT
= 3.3V)
L = 56
H
L = 27
H
L = 15
H
In the two cell application previously described, a
maximum input voltage of 3V would give a peak current
of 1.2A. When comparing various inductors, it is
important to keep in mind that suppliers use different
criteria to determine their ratings. Many use a
conservative current level, where inductance has
dropped to 90% of its normal level. In any case, it is a
good idea to try inductors of various current ratings with
the ML4775 to determine which inductor is the best
choice. Check efficiency and maximum output current,
and if a current probe is available, look at the inductor
current to see if it looks like the waveform shown in
Figure 3. For additional information, see Applications
Note 29, "Choosing an Inductor for Your ML4861
Application."
Suitable inductors can be purchased from the following
suppliers:
Coilcraft
(708) 639-6400
Coiltronics
(407) 241-7876
Dale
(605) 665-9301
Sumida
(708) 956-0666
Figure 5 shows efficiency under the conditions used to
create Figure 4. It can be seen that efficiency is mostly
independent of input voltage and is closely related to
inductor value. This illustrates the need to keep the
inductor value as high as possible to attain peak system
efficiency. As the inductor value goes down to 15H, the
efficiency drops to between 70% and 75%. With 56H,
the efficiency approaches 90% and there is little room
for improvement. At values greater than 100H, the
operation of the synchronous rectifier becomes
unreliable because the inductor current is so small that it
is difficult for the control circuitry to detect.
After the appropriate inductor value is chosen, it is
necessary to find the minimum inductor current rating
required. Peak inductor current is determined from the
following formula:
I
T
V
L
L PEAK
ON MAX
IN MAX
MIN
(
)
(
)
(
)
=
(3)
7
ML4775
Again, a low ESR capacitor (such as tantalum) is
recommended.
DRIVING THE SHDN INPUT
Unlike other boost regulators which use external
Schottky diodes, the ML4775 has the ability to isolate
the load from the battery input when the SHDN pin is
high. Since there may be no other voltage available
when the regulator is in shutdown, the SHDN input
threshold is set well below the minimum V
IN
voltage.
SHDN can be driven directly from an open collector
device with a high value pull-up resistor to V
IN
. If SHDN
is driven from a TTL or CMOS output device, a resistor
divider should be used to prevent the SHDN input high
level from exceeding V
IN
, and to ensure the SHDN input
low level is below the 200mV threshold.
SETTING THE OUTPUT VOLTAGE
The adjustable output can be set to any voltage between
2.5V and 5.5V by connecting a resistor divider to the
SENSE pin as shown in the block diagram. The resistor
values R
1
and R
2
can be calculated using the following
equation:
V
R
R
R
OUT
=
+
0 2
1
2
2
.
(
)
(5)
The value of R
2
should be 40k or less to minimize bias
current errors. R
1
is then found by rearranging the
equation:
R
R
V
OUT
1
2
0 2
1
=
-
.
(6)
It is important to note that the accuracy of these resistors
directly affects the accuracy of the output voltage. The
SENSE pin threshold variation is 3%, and the
tolerances of R
1
and R
2
will add to this to determine the
total output variation.
In some applications, input noise may cause output
ripple to become excessive due to "pulse grouping,"
where the charge-discharge pulses are not evenly
spaced in time. In such cases it may be necessary to add
a small 20pF to 100pF ceramic feedforward capacitor
(C
FF
) from the V
IN
pin to the SENSE pin.
LAYOUT
Good PC board layout practices will ensure the proper
operation of the ML4775. Important layout
considerations include:
Use adequate ground and power traces or planes
Keep components as close as possible to the ML4775
Use short trace lengths from the inductor to the V
L
pin
and from the output capacitor to the V
OUT
pin
Use a single point ground for the ML4775 ground
pins, and the input and output capacitors
OUTPUT CAPACITOR
The choice of output capacitor is also important, as it
controls the output ripple and optimizes the efficiency of
the circuit. Output ripple is influenced by three
capacitor parameters: capacitance, ESR, and ESL. The
contribution due to capacitance can be determined by
looking at the change in capacitor voltage required to
store the energy delivered by the inductor in a single
charge-discharge cycle, as determined by the following
formula:
V
T
V
L C
V
V
OUT
ON
IN
OUT
IN
=
-
2
2
2
(
)
(4)
For a 2.4V input, and 5V output, a 27H inductor, and
a 47F capacitor, the expected output ripple due to
capacitor value is 87mV.
Capacitor Equivalent Series Resistance (ESR) and
Equivalent Series Inductance (ESL), also contribute to
the output ripple due to the inductor discharge current
waveform. Just after the NMOS transistor turns off, the
output current ramps quickly to match the peak inductor
current. This fast change in current through the output
capacitor's ESL causes a high frequency (5ns) spike that
can be over 1V in magnitude. After the ESL spike settles,
the output voltage still has a ripple component equal
to the inductor discharge current times the ESR. This
component will have a sawtooth shape and a peak value
equal to the peak inductor current times the ESR. ESR
also has a negative effect on efficiency by contributing
I-squared R losses during the discharge cycle.
An output capacitor with a capacitance of 100F, an
ESR of less than 0.1, and an ESL of less than 5nH is a
good general purpose choice. Tantalum capacitors
which meet these requirements can be obtained from the
following suppliers:
Matsuo
(714) 969-2491
Sprague
(603) 224-1961
If ESL spikes are causing output noise problems, an EMI
filter can be added in series with the output.
INPUT CAPACITOR
Unless the input source is a very low impedance battery,
it will be necessary to decouple the input with a
capacitor with a value of between 47F and 100F. This
provides the benefits of preventing input ripple from
affecting the ML4775 control circuitry, and it also
improves efficiency by reducing I-squared R losses
during the charge and discharge cycles of the inductor.
8
ML4775
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4775CS
0C to 70C
8-Pin SOIC (S-08)
ML4775ES
20C to 70C
8-Pin SOIC (S-08)
ORDERING INFORMATION
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
DS4775-01
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
PHYSICAL DIMENSIONS
inches (millimeters)
SEATING PLANE
0.148 - 0.158
(3.76 - 4.01)
PIN 1 ID
0.228 - 0.244
(5.79 - 6.20)
0.189 - 0.199
(4.80 - 5.06)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.015 - 0.035
(0.38 - 0.89)
0.059 - 0.069
(1.49 - 1.75)
0.004 - 0.010
(0.10 - 0.26)
0.055 - 0.061
(1.40 - 1.55)
8
0.006 - 0.010
(0.15 - 0.26)
0 - 8
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
Package: S08
8-Pin SOIC
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