May 1997
ML4818
*
Phase Modulation/Soft Switching Controller
1
GENERAL DESCRIPTION
The ML4818 is a complete phase modulation control IC
suitable for full bridge soft switching converters. Unlike
conventional PWM circuits, the phase modulation
technique allows for zero-voltage switching transitions
and square wave drive across the transformer. The IC
modulates the phases of the two sides of the bridge to
control output power.
The ML4818 can be operated in current mode. The delay
times for the outputs are externally programmable to
allow the zero-voltage switching transitions to take place.
Pulse-by-pulse current limit, integrating fault detection,
and soft start reset are provided. The under-voltage
lockout circuit features a 6V hysteresis with a low starting
current to allow off-line start up with a low power bleed
resistor. A shutdown function powers down the IC, putting
it into a low quiescent state.
* Some Packages Are Obsolete)
10
13
11
2
3
5
8
9
12
4
24
20
16
17
22
21
14
*
I
LIM
RC
RESET
SOFT START
INV
E/A OUT
C
T
RAMP
R
T
CLOCK
SHUTDOWN
V
REF
V
CC
A2 OUT
A1 OUT
B1 OUT
B2 OUT
R
DELAY
GND
REFERENCE
AND
UNDER-VOLTAGE
LOCKOUT
+
T FLIP
FLOP
T
Q
Q
S
Q
R
OSC
Q
+
MOD
+
ERROR
AMP
V+
I
1
+5V
3V
Q
R
S
+
1V
DELAY
V
CC
DELAY
V
CC
DELAY
V
CC
DELAY
INHIBIT
OUTPUTS
*PINS 1, 6, 7, 15, 18, 19 AND 23 ARE GND
0.7V
I
2
+
R
S
FEATURES
s
Full bridge phase modulation zero voltage switching
circuit with programmable ZV transition times
s
Constant frequency operation to 500kHz
s
Current mode operation
s
Cycle-by-cycle current limiting with integrating fault
detection and restart delay
s
Precision buffered 5V reference (+1%)
s
Four 1.5A peak current totem-pole output drivers
s
Under-voltage lockout circuit with 6V hysteresis
s
Power DIP package allows higher dissipation
BLOCK DIAGRAM
2
ML4818
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
GND
Ground
2
C
T
Timing capacitor for oscillator
3
RAMP
Non-inverting input to main
comparator. Connected to current
sense resistor for current mode
4
I
LIM
Current limit sense pin. Normally
connected to current sense resistor
5
E/A OUT
Output of error amplifier and input
to PWM comparator
6,7
GND
Ground and substrate
8
INV
Inverting input to error amp
9
SOFT START
Normally connected to soft start
capacitor
10
SHUTDOWN Pulling this pin low puts the IC into
a power down mode and turns off
all outputs. This pin is internally
pulled up to V
REF
.
11
R
T
Resistor which sets discharge
current for oscillator timing
capacitor
PIN
NAME
FUNCTION
12
RC
RESET
Timing elements for Integrating fault
detection and reset delay circuits
13
CLOCK
Oscillator output
14
R
DELAY
Resistor to ground on this pin
programs the amount of delay from
the time an output turns off until its
complementary output turns on
15
GND
Ground
16
A2 OUT
High current totem pole output A1
17
A1 OUT
High current totem pole output A2
18,19 GND
Ground and substrate
20
V
CC
Positive supply for the IC
21
B2 OUT
High current totem pole output B1
22
B1 OUT
High current totem pole output B2
23
GND
Ground
24
V
REF
Buffered output for the 5V voltage
reference
PIN CONNECTION
V
REF
GND
B1 OUT
B2 OUT
V
CC
GND
GND
A1 OUT
A2 OUT
GND
R
DELAY
CLOCK
GND
C
T
RAMP
I
LIM
E/A OUT
GND
GND
INV
SOFT START
SHUTDOWN
R
T
RC
RESET
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
24-Pin Power DIP
GND
C
T
RAMP
I
LIM
E/A OUT
GND
GND
INV
SOFT START
SHUTDOWN
R
T
RC
RESET
V
REF
GND
B1 OUT
B2 OUT
V
CC
GND
GND
A1 OUT
A2 OUT
GND
R
DELAY
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TOP VIEW
24-Pin SOIC
3
ML4818
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
V
CC
........................................................................... 30V
Output Driver Current, Source or Sink
DC ....................................................................... 0.5A
Pulse (0.5
s) ........................................................ 1.5A
Analog Inputs
(C
T
, RAMP, I
LIM
, E/A OUT, INV,
SOFT START, RC
RESET
) ............................... 0.3V to 6V
CLOCK Output Current (R
T
) ....................................5mA
Error Amplifier Output Current (E/A OUT) ................ 5mA
SOFT START Sink Current ..................................... 50 mA
Oscillator Charging Current (C
T
) .............................5mA
Junction Temperature ............................................. 150
C
Storage Temperature Range ..................... 65
C to 150
C
Lead Temperature (Soldering 10 Sec)...................... 260
C
Thermal Resistance (
JA
)
Plastic Power DIP ............................................ 40
C/W
Plastic SOIC ..................................................... 80
C/W
OPERATING CONDITIONS
Operating Temperature Range ....................... 0
C to 70
C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
CC
= 15V, R
T
= 12.7k
, C
T
= 250pF, R
CLK
= 3k
, R
DELAY
= 5k
,
T
A
= Operating Temperature Range (Note 1).
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNITS
OSCILLATOR
Initial Accuracy
T
A
= 25
C
410
450
525
kHz
Voltage Stability
12V < V
CC
< 25V
0.3
%/V
Temperature Stability
0.2
%
Total Variation
line, temp.
375
525
kHz
C
T
Discharge Current
V
CT
= 2V
4.7
5.5
6.3
mA
Clock Out High
2.4
3.1
6
V
Clock Out Low
0
0.4
V
Ramp Peak
0
4.1
V
Ramp Valley
1.5
5
V
Ramp Valley to Peak
0
2.6
5
V
REFERENCE
Output Voltage
T
A
= 25
C, I
O
= 1mA
4.95
5.0
5.05
V
Line Regulation
12V < V
CC
< 25V
20
2
20
mV
Load Regulation
1mA < I
O
< 10mA
20
3
20
mV
Temperature Stability
.2
mV/
C
Total Variation
4.85
5.15
V
Output Noise Voltage
10Hz to 10kHz
50
mV
Long Term Stability
T
J
= 125
C, 1000 hrs
5
25
mV
Short Circuit Current
V
REF
= 0V
20
50
mA
ERROR AMPLIFIER
Input Offset Voltage
40
30
mV
Input Bias Current
3
0.6
3
A
Input Offset Current
0.1
1
A
Open Loop Gain
1 < V
O
< 4V
70
75
dB
PSRR
12 < V
CC
< 25V
65
80
dB
4
ML4818
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNITS
ERROR AMPLIFIER (Continued)
Output Sink Current
V
EA OUT
= 1V
1
3.2
mA
Output Source Current
V
EA OUT
= 5.1V
0.5
2.2
20
mA
Output High Voltage
I
EA OUT
= 0.5mA
5.0
5.5
6.0
V
Output Low Voltage
I
EA OUT
= 1mA
0.8
V
Unity Gain Bandwidth
2.0
2.8
MHz
Slew Rate
8.5
V/
s
PHASE MODULATOR
RAMP Bias Current
V
RAMP
= 2.5V
1
10
A
EA OUT Zero DC Threshold
V
RAMP
= 0V
0.4
0.6
0.9
V
t
PD
, RAMP to Output
50
80
ns
t
DELAY
C
L
= 1nF
99
200
250
ns
R
DELAY
Voltage
4
4.3
5
V
SOFT START
Charge Current
V
SOFT START
= 4V
15
25
30
A
Discharge Current
V
SOFT START
= 1V
10
20
30
mA
CURRENT LIMIT/SHUTDOWN
I
LIM
Bias Current
0V < V
ILIM
< 4V
10
1
10
A
Current Limit Threshold
V
SHUTDOWN
= 0V
0.92
1.02
1.12
V
t
PD
, I
LIM
50
ns
RC
RESET
Shutdown Threshold
3.15
3.4
3.65
V
RC
RESET
Restart Threshold
1.0
1.3
1.6
V
RC
RESET
Charging Current
V
ILIM
=2V, V
RCRESET
= 1.5V
400
523
1000
A
SHUTDOWN Threshold
2.0
2.4
2.8
V
SHUTDOWN Input Bias Current
V
SHUTDOWN
= 0
100
25
10
A
OUTPUT
Output Low Level
I
OUT
= 20mA
0.1
0.4
V
I
OUT
= 200mA, T
A
= 25
C
0.7
2.8
V
Output High Level
I
OUT
= 20mA
12.0
13.5
V
I
OUT
= 200mA, T
A
= 25
C
11.0
13.0
V
Rise/Fall Time
C
L
= 1000pF
50
75
ns
UNDER-VOLTAGE LOCKOUT
Start Threshold
15.5
16.5
17.2
V
Stop Threshold
9.25
10.2
10.7
V
SUPPLY
Start Up Current
V
CC
< 15.8V
3
4
mA
I
CC
V
INV
= 4V, V
RAMP
= V
ILIM
= 0V,
C
L
= 1nF, T
A
= 25
C (Note 2)
60
70
mA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: V
CC
must be brought above the UVLO start voltage (17.2V) before dropping to V
CC
= 15V to ensure start-up.
5
ML4818
FUNCTIONAL DESCRIPTION
PHASE MODULATOR
Power is controlled by modulating the switching phase on
sides A and B of the full H-bridge converter (Figure 1).
Power is delivered to the output through the transformer
secondary. The power conversion process is described by
the following sequence and illustrated by the timing
diagram of Figure 2:
1. A2 and B1 are high (Q1 and Q2 are on), beginning
the power conversion cycle.
2. After the
MOD comparator trips, B1 goes low
turning off Q2. The parasitic drain-to-source
capacitances of Q2 and Q4 charge to +VIN. This
forces the drain-to-source voltage across Q3 to 0V.
3. B2 now goes high after t
DELAY
(set by R
DELAY
). Since
Figure 2. Phase Modulation control waveforms (Shaded areas indicate a power cycle).
B2
B1
A2
A1
I
LIM
R
SENSE
T
B
Q3
Q2
Q4
Q1
T
A
TRANSFORMER
L
LEAKAGE
B
A
+VIN
ML4818
Figure 1. Simplified diagram of Phase Modulated power Outputs.
the voltage across Q3 is now 0V, B2 turns Q3 on at
zero voltage.
4. The CLOCK now goes high turning A2 off. During
this period, Q1 and Q2 and Q4 are off. The
transformer leakage current discharges the drain-to-
source capacitance on Q4 until there is 0V across it.
5. A1 will remain low for a period defined by t
DELAY
,
then it goes high. The voltage across Q4 is now 0V
as A1 turns it on at zero voltage.
6. The previous sequence is now repeated with the
opposite polarity on all outputs (see Figure 2).
The above sequence is then repeated but with the
opposite polarity on all outputs.
t
DELAY
t
DELAY
t
DELAY
t
DELAY
t
DELAY
t
PD1
t
PD1
t
DELAY
t
PD1
C
T
CLOCK
A2
A1
B1
B2
B
A
6
ML4818
The ML4818 can also be used in current mode by sensing
load current on the RAMP input (pin 3).
The four output delay timers are programmed via an
external R
DELAY
resistor as shown below. This resistor
value should be no less than 1k
. Expressing R
DELAY
in
k
the delay, in ns is:
T
R
DELAY
DELAY
=
+
33
45
(1)
The ML4818 contains special logic circuits to provide for
voltage mode feed-forward and lock out long pulses into
the internal logic. This prevents instability from occuring
when the
Comparator trips in voltage mode.
3
RAMP
S
R
Q
MOD
OUTPUT
OSC
Q
R
Figure 3. Voltage Feed-Forward Circuit.
The collector of Q
R
in figure 3 is high only during a power
cycle. When the power cycle terminates, RAMP is pulled
low. In voltage mode operation, a capacitor is connected
from RAMP to GND with a resistor from RAMP to V
IN
to
provide input voltage feed forward.
OSCILLATOR
The ML4818 oscillator charges the external capacitor, C
T
,
with a current (I
SET
) equal to 5/R
T
. When the C
T
voltage
reaches the upper threshold (Ramp Peak), the comparator
changes state, turning on the current sink which
discharges C
T
to the lower threshold (Ramp Valley). The
C
T
pin is clamped to Ramp Valley by Q1 (Figure 5) to
prevent inaccuracy due to undershoot on C
T
.
To use the CLOCK output for driving external synch-
ronization circuitry, a pull-down resistor is required from
CLOCK to GND.
11
+
2
13
5V
CLOCK
OUT
5V
5.5mA
1.7V
R
T
I
SET
C
T
I
SET
250
Q1
Figure 5. Ocillator Block Diagram
For frequencies of less than 500kHz, oscillator frequency
can be set by using the following formulae:
f
C R
C
OSC
T T
T
=
+
1
0 52
500
.
(2)
ERROR AMPLIFIER
The ML4818 error amplifier is a 2.5MHz bandwidth,
8.5V/
s slew rate op-amp with provision for limiting the
positive output voltage swing (output inhibit line) to
implement the soft start function. The error amplifier
output source current is limited to 4.5mA.
CLOCK
T
D
C
T
RAMP PEAK
RAMP VALLEY
T
C
Figure 4. Ocillator Timing Diagram
7
ML4818
120
100
80
60
40
20
0
180
135
90
45
0
0
100
1k
10k
100k
1M
10M
FREQUENCY
GAIN
PHASE (Degrees)
GAIN
PHASE
POWER
GND
Q1
Q2
OUT
V
CC
V
CC
Figure 7. Power Driver Simplified Schematic.
Figure 6. Error Amplifier Open-Loop Gain and
Phase vs. Frequency.
7
6
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OUTPUT CURRENT (A)
SATURATION DROP (V)
SOURCE
SINK
~ ~
15
10
5
100
200
100
200
10nF
1nF
1nF
10nF
t
F
t
R
(ns)
OUTPUT VOLTAGE (V)
Figure 9. Output Rise/Fall Time.
Figure 8. Output Drive Saturation Voltage vs.
Output Current.
OUTPUT DRIVER STAGE
The ML4818 has four high current high speed totem pole
output drivers each capable of 1.5A peak output, designed
to quickly switch the gates of capacitive loads, such as
power MOSFET transistors. Figure 8 illustrates the
saturation characteristics of the ouput drive transistors
shown in Figure 7. Typical rise and fall time characteristics
of the output drivers are illustrated with capacitive loads
of 1nF and 10nF in Figure 9.
8
ML4818
Figure 10. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.
C
RST
+
R
RST
12
+
9
4
INHIBIT
OUTPUT
UNDER-VOLTAGE
LOCKOUT
CLOCK
3.4V
1.3V
RC
RESET
R
SENSE
R1
C1
V+
I2
S
Q
R
TERMINATE
PWM CYCLE
V+
I
1
SOFT START
I
SWITCH
C
SS
I
LIM
1V
1V
3.4V
V(PIN 4)
V(PIN 12)
1V
3.4V
V(PIN 4)
V(PIN 12)
Figure 11c, 11d. I
LIMIT
and Resulting RC
RESET
Waveforms During Load Surge.
Figure 11a, 11b. I
LIMIT
and Resulting RC
RESET
Waveforms During Short Circuit.
CURRENT LIMIT, FAULT DETECTION AND SOFT START
Current limit is implemented when the current sensed on
I
LIM
reaches the 1V limit. At this point, the PWM cycle is
terminated. The flip flop (Figure 10) turns on the current
source to charge C
RST
and remains on for the duration of
the clock period. When C
RST
has charged to 3.4V, a soft
start reset occurs. The number of times the PWM cycle is
terminated due to over-current is "remembered" on C
RST
.
Over time, C
RST
is discharged by R
RST
providing a
measure of "forgetting" when the over-current condition
no longer occurs. This integrating fault detection is useful
in differentiation between short circuit and load surge
conditions.
Since the per cycle charge on RC
RESET
is proportional to
how early in the power cycle the over-current occurs, a
reset will occur more quickly under output short circuit
conditions (Figures 11a and 11b) than during a load surge
(Figures 11c and 11d).
When the soft start reset occurs, the output is inhibited
and the soft start capacitor is discharged. The output will
remain off until C
RST
discharges to 1.3V through R
RST
,
providing a reset delay. When the IC restarts, the error
amplifier output voltage is limited to the voltage at SOFT
START, thus limiting the duty cycle.
9
ML4818
UNDER-VOLTAGE LOCKOUT
On power up, when V
CC
is below 16V, the IC draws very
little current (1.1mA typ.) and V
REF
is disabled. When V
CC
rises above 16V, the IC becomes active and V
REF
is
enabled and will stay in that condition until V
CC
falls
below 10.2V. (see Figure 12).
INHIBIT
OUTPUTS
+
+
20
24
INTERNAL
BIAS
4V
TO LOGIC
CIRCUITS
5V
V
REF
9V
V
CC
POWER
DOWN
Figure 12. Under-Voltage Lockout and
Reference Circuits.
Figure 13. Supply Current vs. Temperature (
C).
70
68
66
64
62
60
58
56
54
52
50
75
25
25
75
125
175
TEMPERATURE
SUPPLY CURRENT (mA)
Figure 15.
JA
as a Function of I (see figure 15).
50
30
20
0
2
I : HEAT SINK DIMENSION (INCHES)
40
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Figure 14. PC Board Copper Area Used as a Heat Sink.
APPLICATIONS
The application circuit shown in Figure 16 features the
ML4818 in a primary-side controlled voltage mode
application with voltage feed-forward. Input voltage is
rectified 120VAC (nominal). Feed-forward is provided by
the RAMP pin via the resistor connected to the high
voltage input. Current is sensed through sense transformer
T4.
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
0.555"
I
I
I
I
THERMAL INFORMATION
The ML4818 is offered in a Power DIP package. This
package features improved thermal conduction through
the leadframe. Much of the heat is conducted through the
center 4 grounded leads. Thermal dissipation can be
improved with this package by using copper area on the
board to function as a heat sink. Increasing this area can
reduce the
JA
(see figures 14 and 15), increasing the
power handling capability of the package. Additional
improvement may be obtained by using an external heat
sink (available from Staver).
10
ML4818
7.5k
, 1/4W
4.3k
, 1/4W
ML4818
220pF
100k
5.1k
1/4W
1000pF
100k
1/4W
1N5818
T2
39
1/4W
1N4148
IRF840
T4
5.1
, 1/4W
T1
45T
SCHOTTKY
DIODE
15H
1N5818
1
F
100
F
25V
+
1k
,1/4W
V
OUT
,
15V, 13A
+
1k
POT
IC2
MOC8102
V
CC
510
1/4W
330k
1/4W
+
+
680
F,
200V
4 x 1N5406,
3A, 600V
240k
1/4W
5A, 250V
AC IN
J1
120VAC220VAC JUMPER
+HV
0.1
F
0.01
F
1kV
1
F
100
F
25V
+
82k
, 1W
V
CC
T1
200H
680pF
T3
MUR150
1
F
470pF
1
F
1
F
240k
, 1/4W
IRF840
0.33
F
630V
IRF840
1
F
IRF840
FUSE
240k
1/4W
680
F,
200V
MUR150
5.1
, 1/4W
120pF
10T
1N5818
T3
10T
1N5818
10T
2 x IN5248
80T
1T
2 x IN5248
5.1
, 1/4W
5.1
, 1/4W
10T
10T
10T
4T
4T
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
470pF
4T
4T
T2
Figure 16. Offline Full Bridge Converter.
11
ML4818
SEATING PLANE
0.240 - 0.270
(6.09 - 6.86)
PIN 1 ID
0.295 - 0.325
(7.49 - 8.26)
1.240 - 1.260
(31.49 - 32.01)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
24
0 - 15
1
0.050 - 0.065
(1.27 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.070 MIN
(1.77 MIN)
(4 PLACES)
Package: P24N
24-Pin Narrow PDIP
PHYSICAL DIMENSIONS
inches (millimeters)
12
ML4818
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4818CP
0
C to 70
C
Power DIP (P24)
ML4818CS
0
C to 70
C
SOIC (S24W)
(Obsolete)
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
DS4818-01
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
PHYSICAL DIMENSIONS
inches (millimeters)
SEATING PLANE
0.291 - 0.301
(7.39 - 7.65)
PIN 1 ID
0.398 - 0.412
(10.11 - 10.47)
0.600 - 0.614
(15.24 - 15.60)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.022 - 0.042
(0.56 - 1.07)
0.095 - 0.107
(2.41 - 2.72)
0.005 - 0.013
(0.13 - 0.33)
0.090 - 0.094
(2.28 - 2.39)
24
0.009 - 0.013
(0.22 - 0.33)
0 - 8
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
Package: S24
24-Pin SOIC
Micro Linear 1997
Micro Linear
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
PDF 
ZIP