1
May 1997
ML4822
*
ZVS Average Current PFC Controller
GENERAL DESCRIPTION
The ML4822 is a PFC controller designed specifically for
high power applications. The controller contains all of the
functions necessary to implement an average current
boost PFC converter, along with a Zero Voltage Switch
(ZVS) controller to reduce diode recovery and MOSFET
turn-on losses.
The average current boost PFC circuit provides high
power factor (>98%) and low Total Harmonic Distortion
(THD). Built-in safety features include undervoltage
lockout, overvoltage protection, peak current limiting, and
input voltage brownout protection.
The ZVS control section drives an external ZVS MOSFET
which, combined with a diode and inductor, soft switches
the boost regulator. This technique reduces diode reverse
recovery and MOSFET switching losses to reduce EMI and
maximize efficiency.
*This Part Is End Of Life As Of August 1, 2000
FEATURES
s
Average current sensing, continuous boost, leading
edge PFC for low total harmonic distortion and near
unity power factor
s
Built-in ZVS switch control with fast response for high
efficiency at high power levels
s
Average line voltage compensation with brownout
control
s
Current fed gain modulator improves noise immunity
and provides universal input operation
s
Overvoltage comparator eliminates output "runaway"
due to load removal
s
UVLO, current limit, and soft-start
s
Precision 1% reference
BLOCK DIAGRAM
(Pin configuration shown for 14-pin package)
Q
S
R
+
1
14
VEAO
VEA
2.5V
FB
4
IAC
5
VRMS
+
3
ISENSE
8
GND
2
IEAO
+
IEA
R+
R
+
6
RTCT
OSC
GAIN
MODULATOR
S
R
Q
+
2.7V
FB
1V
12
VCC
VCCZ
13.5V
ZVS OUT
11
Q
S
R
Q
PFC OUT
9
PWR GND
10
OVP
I LIMIT
REF
13
ZV SENSE
7
+
VCCZ
REF
Q
ML4822
2
PIN CONFIGURATION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1 (1)
VEAO
Transconductance voltage error
amplifier output.
2 (2)
IEAO
Transconductance current error
amplifier output.
3 (3)
I
SENSE
Current sense input to the PFC
current limit comparator.
4 (4)
I
AC
PFC gain modulator reference input.
5 (5)
V
RMS
Input for RMS line voltage
compensation.
6 (6)
R
T
C
T
Connection for oscillator frequency
setting components.
7 (7)
ZV SENSE
Input to the high speed zero voltage
crossing comparator.
PIN DESCRIPTION
(Pin number in parentheses is for 16-pin package)
8 (10) GND
Analog signal ground.
9 (11) PWR GND Return for the PFC and ZVS driver
outputs.
10 (12) ZVS OUT ZVS MOSFET driver output.
11 (13) PFC OUT PFC MOSFET driver output.
12 (14) V
CC
Shunt-regulated supply voltage.
13 (15) REF
Buffered output for the internal
7.5V reference.
14 (16) FB
Transconductance voltage error
amplifier input.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VEAO
IEAO
ISENSE
IAC
VRMS
RTCT
ZV SENSE
N/C
FB
REF
VCC
PFC OUT
ZVS OUT
PWR GND
GND
N/C
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VEAO
IEAO
ISENSE
IAC
VRMS
RTCT
ZV SENSE
FB
REF
VCC
PFC OUT
ZVS OUT
PWR GND
GND
TOP VIEW
ML4822
16-Pin SOIC (S16W)
ML4822
14-Pin DIP (P14)
ML4822
3
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Shunt Regulator Current (I
CC
) ................................. 55mA
Peak Driver Output Current ...............................
500mA
Analog Inputs ................................................... 0.3 to 7V
Junction Temperature ............................................. 150
C
Storage Temperature Range ..................... 65
C to 150
C
Lead Temperature (Soldering, 10 sec) ..................... 150
C
Thermal Resistance (
JA
)
Plastic DIP ....................................................... 80
C/W
Plastic SOIC ....................................................110
C/W
OPERATING CONDITIONS
Temperature Range
ML4822CX ................................................ 0
C to 70
C
ML4822IX .............................................. 40
C to 85
C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, R
T
= 52.3k
, C
T
= 470pF, T
A
= Operating Temperature Range (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE ERROR AMPLIFIER
Input Voltage Range
0
7
V
Transconductance
V
NON-INV
= V
INV
, VEAO = 3.75V
50
70
120
Feedback Reference Voltage
V
EAO
= V
FB
2.4
2.5
2.6
V
Open Loop Gain
60
75
dB
PSRR
V
CCZ
3V < V
CC
< V
CCZ
0.5V
60
75
dB
Output Low
0.65
1
V
Output High
6.0
6.7
V
Source Current
V
IN
=
0.5V, V
OUT
= 6V
40
80
A
Sink Current
V
IN
=
0.5V, V
OUT
= 1.5V
40
80
mA
CURRENT ERROR AMPLIFIER
Input Voltage Range
1.5
2
V
Transconductance
V
NON-INV
= V
INV
, IEAO = 3.75V
130
195
310
Input Offset Voltage
3
15
mV
Open Loop Gain
60
75
dB
PSRR
V
CCZ
3V < V
CC
< V
CCZ
0.5V
60
75
dB
Output Low
0.65
1
V
Output High
6.0
6.7
V
Source Current
V
IN
=
0.5V, V
OUT
= 6V
40
80
A
Sink Current
V
IN
=
0.5V, V
OUT
= 1.5V
40
80
A
OVP COMPARATOR
Threshold Voltage
2.6
2.7
2.8
V
Hysteresis
80
120
150
mV
I
SENSE
COMPARATOR
Threshold Voltage
0.8
1.0
1.15
V
Delay to Output
150
300
ns
ML4822
4
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ZV SENSE COMPARATOR
Propagation Delay
100mV Overdrive
50
ns
Threshold Voltage
7.35
7.5
7.65
V
Input Capacitance
6
pF
GAIN MODULATOR
Gain (Note 2)
I
IAC
= 100mA, V
VRMS
= 0V,
V
FB
= 0V
0.36
0.51
0.66
I
IAC
= 50mA, V
VRMS
= 1.2V,
V
FB
= 0V
1.20
1.72
2.24
I
IAC
= 100
A, V
VRMS
= 1.8V,
V
FB
= 0V
0.55
0.78
1.01
I
IAC
= 100
A, V
VRMS
= 3.3V,
V
FB
= 0V
0.14
0.20
0.26
Bandwidth
I
IAC
= 250
A
10
MHz
Output Voltage
V
FB
= 0V, V
VRMS
= 1.15V,
I
IAC
= 250
A
0.72
0.8
0.9
V
OSCILLATOR
Initial Accuracy
T
A
= 25
C
74
80
86
kHz
Voltage Stability
V
CCZ
3V < V
CC
< V
CCZ
0.5V
1
%
Temperature Stability
2
%
Total Variation
Line, temperature
72
88
kHz
Ramp Valley to Peak Voltage
2.5
V
Dead Time
100
300
450
ns
C
T
Discharge Current
4.5
7.5
9.5
mA
REFERENCE
Output Voltage
T
A
= 25
C, I
REF
= 1mA
7.425
7.5
7.575
V
Line Regulation
V
CCZ
3V < V
CC
< V
CCZ
0.5V
2
10
mV
Load Regulation
1mA < I
REF
, < 20mA
2
15
mV
Temperature Stability
0.4
%
Total Variation
Line, load, and temperature
7.395
7.605
V
Long Term Stability
T
j
= 125
C, 1000 hours
5
25
mV
Short Circuit Current
V
CC
< V
CCZ
0.5V, V
REF
= 0V
15
40
100
mA
PFC COMPARATOR
Minimum Duty Cycle
V
IEAO
> 6.7V
0
%
Maximum Duty Cycle
V
IEAO
< 1.2V
90
95
%
ML4822
5
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MOSFET DRIVER OUTPUTS
Output Low Voltage
I
OUT
= 20mA
0.3
0.8
V
I
OUT
= 100mA
0.6
3.0
V
I
OUT
= 10mA, V
CC
= 8V
0.8
1.5
V
Output High Voltage
I
OUT
= 20mA
9.5
10.3
V
I
OUT
= 100mA
9
10.3
V
Output Rise/Fall Time
C
L
= 1000pF
40
ns
UNDERVOLTAGE LOCKOUT
Threshold Voltage
V
CCZ
0.9 V
CCZ
0.6 V
CCZ
0.2
V
Hysteresis
2.5
2.8
3.2
V
SUPPLY
Shunt Voltage (V
CCZ
)
I
CC
=25mA
12.8
13.5
14.2
V
Load Regulation
25mA < I
CC
< 55mA
150
300
mV
Total Variation
Load and temperature
12.4
14.6
V
Start-up Current
V
CC
< 12.3V
0.7
1.1
mA
Operating Current
V
CC
= V
CCZ
0.5V
22
28
mA
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2:
Gain = K x 5.3 V; K = (I
GAINMOD
I
OFFSET
) x I
AC
x (V
EAO
1.5)
1
.
ML4822
6
FUNCTIONAL DESCRIPTION
Switching losses of wide input voltage range PFC boost
converters increase dramatically as power levels increase
above 200 watts. The use of zero-voltage switching (ZVS)
techniques improves the efficiency of high power PFCs by
significantly reducing the turn-on losses of the boost
MOSFET. ZVS is accomplished by using a second, smaller
MOSFET, together with a storage element (inductor) to
convert the turn-on losses of the boost MOSFET into
useful output power.
The basic function of the ML4822 is to provide a power
factor corrected, regulated DC bus voltage using
continuous, average current-mode control. Like Micro
Linear's family of PFC/PWM controllers, the ML4822
employs leading-edge pulse width modulation to reduce
system noise and permit frequency synchronization to a
trailing edge PWM stage for the highest possible DC bus
voltage bandwidth. For minimization of switching losses,
circuitry has been incorporated to control the switching of
the ZVS FET.
THEORY OF OPERATION
Figure 1 shows a simplified schematic of the output and
control sections of a high power PFC circuit. Figure 2
shows the relationship of various waveforms in the circuit.
Q1 functions as the main switching FET and Q2 provides
the ZVS action. During each cycle, Q2 turns on before
Q1, diverting the current in L1 away from D1 into L2. The
current in L2 increases linearly until at t
2
it equals the
current through L1. When these currents are equal, L1
ceases discharging current and is now charged through L2
and Q2. At time t
2
, the drain voltage of Q1 begins to fall.
The shape of the voltage waveform is sinusoidal due to
the interaction of L2 and the combined parasitic
capacitance of D1 and Q1 (or optional ZVS capacitor
C
ZVS
). At t
3
, the voltage across Q1 is sufficiently low that
the controller turns Q2 off and Q1 on. Q1 then behaves
as an ordinary PFC switch, storing energy in the boost
inductor L1. The energy stored in L2 is completely
discharged into the boost capacitor via D2 during the Q1
off-time and the value of L2 must be selected for
discontinuous-mode operation.
COMPONENT SELECTION
Q1 Turn-Off
Because the ML4822 uses leading edge modulation, the
PFC MOSFET (Q1) is always turned off at the end of each
oscillator ramp cycle. For proper operation, the internal
ZVS flip-flop must be reset every cycle during the
oscillator discharge time. This is done by automatically
resetting the ZVS comparator a short time after the drain
voltage of the main Q has reached zero (refer to Figure 1
sense circuit). This sense circuit terminates the ZVS on
time by sensing the main Q drain voltage reaching zero. It
is then reset by way of a resistor pull-up to V
CC
(R6). The
advantage of this circuit is that the ZVS comparator is not
reset at the main Q turn off which occurs at the end of the
clock cycle. This avoids the potential for improper reset of
the internal ZVS flip-flop.
Another concern is the proper operation of the ZVS
comparator during discontinuous mode operation (DCM),
which will occur at the cusps of the rectified AC
waveform and at light loads. Due to the nature of the
voltage seen at the drain of the main boost Q during DCM
operation, the ZVS comparator can be fooled into forcing
the ZVS Q on for the entire period. By adding a circuit
which limits the maximum on time of the ZVS Q, this
problem can be avoided. Q3 in Figure 1 provides this
function.
Figure 1. Simplified PFC/ZVS Schematic.
11
10
9
8
7
12
C3
33pF
C4
330pF
C5
C1
C2
D1
D2
L1
C
ZVS(OPT)
+
Q1
Q3
Q2
R1
PFC OUT
ZVS OUT
PWR GND
V
CC
13 V
REF
V
REF
ZV SENSE
GND
ML4822
MAX ZVS
ON TIME LIMIT
L2
R6
22k
R3
22k
R2
R4
51k
R5
220
ML4822
7
Q1 Turn-On
The turn-on event consists of the time it takes for the
current through L2 to ramp to the L1 current plus the
resonant event of L2 and the ZVS capacitor. The total
event should occur in a minimum of 350450ns, but can
be longer at the risk of increasing the total harmonic
distortion. Setting these times equal should minimize
conducted and radiated emissions.
t
Q1(OFF)
= t
IL2
+ t
RES
= 400ns
(1)
Where I
L2
is equal to I
L1
.
The value of L2 is calculated to remain in discontinuous-
mode:
L
V
V
t
P
BUS
RMS MIN
IL
OUT
2
2
2
=
(
)
(2)
The resonant event occurs in 1/4 of a full sinusoidal cycle.
For example, when a 1/4 cycle occurs in 200ns, the
frequency is 1.25MHz.
f
L
C
t
RES
ZVS
RES
=
=
1
2
2
1
4
(3)
Rearranging and solving for L2:
L
t
C
RES
ZVS
2
4
2
2
=
(4)
The resonant capacitor (C
ZVS
) value is found by setting
equations 2 and 4 equal to each other and solving for
C
ZVS
.
C
t
P
V
V
t
ZVS
RES
OUT
BUS
RMS MIN
IL
=
4
2
2
2
2
(
)
(5)
APPLICATION
Figure 3 displays a typical application circuit for a 500W
ZVS PFC supply. Full design details are covered in
application note 33, ML4822 Power Factor Correction
With Zero Voltage Resonant Switching.
Figure 2. Timing Diagrams
t
2
t
3
t
1
A. SYSTEM
CLOCK
(INTERNAL)
B. RTCT
C. ZVS GATE (Q2)
D. VDS (Q2)
E. PFC GATE (Q1)
F. VDS (Q1)
G. I
L2
ML4822
8
Figure 3. ML4822 Scematic
1
2
3
4
5
6
7
1
2
3
4
14
13
12
11
10
9
8
8
7
6
5
VEAO
IEAO
I
SENSE
I
AC
V
RMS
R
T
C
T
ZV SENSE
FB
REF
V
CC
PFC OUT
ZVS OUT
PWR GND
GND
ML4822
LINE
F1
8AMP
250VAC
C14
0.47
F
250VAC
250JB6L
R13
402k
1%
R23
402k
1%
R12
453k
1%
R22
453k
1%
R14
100k
1%
C6
0.47
F
16V
C2
470pF
1600V
C4
0.1
F
50V
L1
420uH @ 10A
n = 57
R15
16.2k
1%
R4
10k
R3
10
R6
10k
R10
102k
1%
R8
93.1k
1%
R9
93.1k
1%
R5
39k
2W
R7
47
R29
10k
R26
22k
R16
8.25k
1%
R27
220
R19
10k
R17
220k
D10
BYV26C
R24
22k
R25
51k
C22
100pF
C20
2.2nF
50V
C19
330pF
50V
C18
33pF
50V
Q3
2N7000
L1
n = 2.5
D11
BYM 12-50
C16
1
F
50V
C5
1
F
50V
C11
0.
068
F
50V
C12
2.2nF
50V
C13
100pF
50V
C8
2.2
F
50V
C7
0.68
F 50V
C15
1500
F
25V
C17
1
F
50V
D12
BYM12-50
D8
PRLL5819
D9
PRLL5819
1N4148
R21
39k
2W
R20
93.1k
1%
R11
2.37k
1%
R2
10
C3
1000pF
50V
400VDC RTN
400VDC
D6
D1N4747
D4
BYV26C
D5
D1N4747
L2
8.5
@ 14A
D1
HFA15TB60
D2
HFA08TB60
Q1
IRFP460
Q2
IRF830
D3
MUR460
R1
3.3k
3W
C21
0.1
F
200V
C10
1
F
50V
C1
330
F
450V
C9
1
F
50V
R18
0.0732 5W
1%
D13
1N5401
D7
1N5401
B1
NEUTRAL
NC
IN A
V
S RTN
IN B
NC
OUT A
V
S
OUT B
+
TC4427
ML4822
11
PHYSICAL DIMENSIONS
inches (millimeters)
SEATING PLANE
0.240 - 0.260
(6.09 - 6.61)
PIN 1 ID
0.295 - 0.325
(7.49 - 8.25)
0.740 - 0.760
(18.79 - 19.31)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
14
0 - 15
1
0.050 - 0.065
(1.27 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.070 MIN
(1.77 MIN)
(4 PLACES)
Package: P14
14-Pin PDIP
ML4822
10
DS4822-01
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4822CP
0
C to 70
C
14-Pin PDIP (P14)
(EOL)
ML4822CS
0
C to 70
C
16-Pin Wide SOIC (S16W)
(EOL)
ML4822IP
40
C to 85
C
14-Pin PDIP (P14)
(EOL)
ML4822IS
40
C to 85
C
16-Pin Wide SOIC (S16W)
(EOL)
SEATING PLANE
0.291 - 0.301
(7.39 - 7.65)
PIN 1 ID
0.398 - 0.412
(10.11 - 10.47)
0.400 - 0.414
(10.16 - 10.52)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.022 - 0.042
(0.56 - 1.07)
0.095 - 0.107
(2.41 - 2.72)
0.005 - 0.013
(0.13 - 0.33)
0.090 - 0.094
(2.28 - 2.39)
16
0.009 - 0.013
(0.22 - 0.33)
0 - 8
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
Package: S16W
16-Pin Wide SOIC
PHYSICAL DIMENSIONS
inches (millimeters)
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
Micro Linear 1997
Micro Linear
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
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