June 1998

ML4824

Power Factor Correction and PWM Controller Combo

GENERAL DESCRIPTION

The ML4824 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching
FETs, and results in a power supply that fully complies
with IEC1000-2-3 specification. The ML4824 includes
circuits for the implementation of a leading edge, average
current, "boost" type power factor correction and a trailing
edge, pulse width modulator (PWM).

The device is available in two versions; the ML4824-1
(f

PWM

= f

PFC

) and the ML4824-2 (f

PWM

= 2 x f

PFC

Doubling the switching frequency of the PWM allows the
user to design with smaller output components while
maintaining the best operating frequency for the PFC. An
over-voltage comparator shuts down the PFC section in the
event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brown-
out protection. The PWM section can be operated in
current or voltage mode at up to 250kHz and includes a

duty cycle limit to prevent transformer saturation.

FEATURES

Internally synchronized PFC and PWM in one IC

Low total harmonic distortion

Reduces ripple current in the storage capacitor between
the PFC and PWM sections

Average current, continuous boost leading edge PFC

Fast transconductance error amp for voltage loop

High efficiency trailing edge PWM can be configured
for current mode or voltage mode operation

Average line voltage compensation with brownout
control

PFC overvoltage comparator eliminates output
"runaway" due to load removal

Current fed gain modulator for improved noise immunity

Overvoltage protection, UVLO, and soft start

VEAO

IEAO

VFB

IAC

VRMS

ISENSE

RAMP 1

OSCILLATOR

OVP

PFC ILIMIT

UVLO

VREF

PULSE WIDTH MODULATOR

POWER FACTOR CORRECTOR

2.5V

7.5V

REFERENCE

VCC

VCCZ

VEA

IEA

PFC OUT

2.7V

1V

RAMP 2

PWM OUT

VDC

DC ILIMIT

VCC

DUTY CYCLE

LIMIT

2.5V

VFB

VIN OK

GAIN

MODULATOR

VCCZ

x 2

(-2 VERSION ONLY)

3.5k

1.25V

50µA

13.5V

DC ILIMIT

BLOCK DIAGRAM

*Some Packages Are Obsolete

ML4824

PIN CONFIGURATION

PIN DESCRIPTION

PIN

NAME

FUNCTION

DC I

LIMIT

PWM current limit comparator input

GND

Ground

PWM OUT PWM driver output

PFC OUT

PFC driver output

Positive supply (connected to an
internal shunt regulator)

REF

Buffered output for the internal 7.5V
reference

PFC transconductance voltage error
amplifier input

VEAO

PFC transconductance voltage error
amplifier output

PIN

NAME

FUNCTION

IEAO

PFC transconductance current error
amplifier output

PFC gain control reference input

SENSE

Current sense input to the PFC current
limit comparator

RMS

Input for PFC RMS line voltage
compensation

Connection point for the PWM soft start
capacitor

PWM voltage feedback input

RAMP 1

Oscillator timing node; timing set
by R

RAMP 2

When in current mode, this pin
functions as as the current sense input;
when in voltage mode, it is the PWM
input from PFC output (feed forward
ramp).

IEAO

IAC

ISENSE

VRMS

VDC

RAMP 1

RAMP 2

VEAO

VFB

VREF

VCC

PFC OUT

PWM OUT

GND

DC ILIMIT

TOP VIEW

ML4824

16-Pin PDIP (P16)

16-Pin Wide SOIC (S16W)

ML4824

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Shunt Regulator Current .................................. 55mA

SENSE

Voltage ..................................................3V to 5V

Voltage on Any Other Pin ... GND 0.3V to V

CCZ

+ 0.3V

REF ............................................................................................

20mA

Input Current .................................................... 10mA

Peak PFC OUT Current, Source or Sink ................ 500mA
Peak PWM OUT Current, Source or Sink .............. 500mA
PFC OUT, PWM OUT Energy Per Cycle .................. 1.5µJ

Junction Temperature .............................................. 150°C
Storage Temperature Range ..................... 65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................... 260°C
Thermal Resistance (

)

Plastic DIP ....................................................... 80°C/W
Plastic SOIC ................................................... 105°C/W

OPERATING CONDITIONS

Temperature Range

ML4824CX ................................................. 0°C to 70°C
ML4824IX .............................................. 40°C to 85°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, I

= 25mA, R

= 52.3k

, C

= 470pF, T

= Operating Temperature Range (Note 1)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VOLTAGE ERROR AMPLIFIER

Input Voltage Range

Transconductance

NON INV

= V

INV

, VEAO = 3.75V

120

Feedback Reference Voltage

2.46

2.53

2.60

Input Bias Current

Note 2

-0.3

1.0

µA

Output High Voltage

6.0

6.7

Output Low Voltage

0.6

1.0

Source Current

= ±0.5V, V

OUT

= 6V

µA

Sink Current

= ±0.5V, V

OUT

= 1.5V

µA

Open Loop Gain

Power Supply Rejection Ratio

CCZ

- 3V < V

< V

CCZ

- 0.5V

CURRENT ERROR AMPLIFIER

Input Voltage Range

1.5

Transconductance

NON INV

= V

INV

, VEAO = 3.75V

130

195

310

Input Offset Voltage

Input Bias Current

0.5

1.0

µA

Output High Voltage

6.0

6.7

Output Low Voltage

0.6

1.0

Source Current

= ±0.5V, V

OUT

= 6V

µA

Sink Current

= ±0.5V, V

OUT

= 1.5V

µA

Open Loop Gain

Power Supply Rejection Ratio

CCZ

- 3V < V

< V

CCZ

- 0.5V

ML4824

ELECTRICAL CHARACTERISTICS

(Continued)

SMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

OVP COMPARATOR

Threshold Voltage

2.6

2.7

2.8

Hysteresis

115

150

PFC I

LIMIT

COMPARATOR

Threshold Voltage

0.8

1.0

1.15

(PFC I

LIMIT

- Gain Modulator Output)

100

190

Delay to Output

150

300

DC I

LIMIT

COMPARATOR

Threshold Voltage

0.97

1.02

1.07

Input Bias Current

±0.3

±1

µA

Delay to Output

150

300

OK COMPARATOR

Threshold Voltage

2.4

2.5

2.6

Hysteresis

0.8

1.0

1.2

GAIN MODULATOR

Gain (Note 3)

= 100µA, V

RMS

= V

= 0V

0.36

0.55

0.66

= 50µA, V

RMS

= 1.2V, V

= 0V

1.20

1.80

2.24

= 50µA, V

RMS

= 1.8V, V

= 0V

0.55

0.80

1.01

= 100µA, V

RMS

= 3.3V, V

= 0V

0.14

0.20

0.26

Bandwidth

IAC = 100µA

MHz

Output Voltage

= 250µA, V

RMS

= 1.15V,

0.74

0.82

0.90

= 0V

OSCILLATOR

Initial Accuracy

= 25°C

kHz

Voltage Stability

CCZ

- 3V < V

< V

CCZ

- 0.5V

Temperature Stability

Total Variation

Line, Temp

kHz

Ramp Valley to Peak Voltage

2.5

Dead Time

PFC Only

270

370

470

Discharge Current

RAMP 2

= 0V, V

RAMP 1

= 2.5V

4.5

7.5

9.5

REFERENCE

Output Voltage

= 25°C, I(V

REF

) = 1mA

7.4

7.5

7.6

Line Regulation

CCZ

- 3V < V

< V

CCZ

- 0.5V

Load Regulation

1mA < I(V

REF

) < 20mA

Temperature Stability

0.4

Total Variation

Line, Load, Temp

7.35

7.65

Long Term Stability

= 125°C, 1000 Hours

ML4824

ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PFC

Minimum Duty Cycle

IEAO

> 4.0V

Maximum Duty Cycle

IEAO

< 1.2V

Output Low Voltage

OUT

= -20mA

0.4

0.8

OUT

= -100mA

0.8

2.0

OUT

= 10mA, V

= 8V

0.7

1.5

Output High Voltage

OUT

= 20mA

10.5

OUT

= 100mA

9.5

Rise/Fall Time

= 1000pF

PWM

Duty Cycle Range

ML4824-1

0-44

0-47

0-50

ML4824-2

0-37

0-40

0-45

Output Low Voltage

OUT

= -20mA

0.4

0.8

OUT

= -100mA

0.8

2.0

OUT

= 10mA, V

= 8V

0.7

1.5

Output High Voltage

OUT

= 20mA

10.5

OUT

= 100mA

9.5

Rise/Fall Time

= 1000pF

SUPPLY

Shunt Regulator Voltage (V

CCZ

)

12.8

13.5

14.2

CCZ

Load Regulation

25mA < I

< 55mA

±100

±300

CCZ

Total Variation

Load, Temp

12.4

14.6

Start-up Current

= 11.8V, C

= 0

0.7

1.0

Operating Current

< V

CCZ

- 0.5V, C

= 0

Undervoltage Lockout Threshold

Undervoltage Lockout Hysteresis

2.7

3.0

3.3

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Includes all bias currents to other circuits connected to the V

pin.

Note 3: Gain = K x 5.3V; K = (I

GAINMOD

- I

OFFSET

) x I

x (VEAO - 1.5V)

-1

ML4824

FUNCTIONAL DESCRIPTION

The ML4824 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM's line regulation. In
either mode, the PWM stage uses conventional trailing-
edge duty cycle modulation, while the PFC uses leading-
edge modulation. This patented leading/trailing edge
modulation technique results in a higher useable PFC error
amplifier bandwidth, and can significantly reduce the size
of the PFC DC buss capacitor.

The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor). The
PWM section of the ML4824-1 runs at the same frequency
as the PFC. The PWM section of the ML4824-2 runs at
twice the frequency of the PFC, which allows the use of
smaller PWM output magnetics and filter capacitors while
holding down the losses in the PFC stage power
components.

In addition to power factor correction, a number of
protection features have been built into the ML4824. These
include soft-start, PFC over-voltage protection, peak
current limiting, brown-out protection, duty cycle limit,
and under-voltage lockout.

POWER FACTOR CORRECTION

Power factor correction makes a non-linear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to
the line voltage, so the power factor is unity (one). A
common class of non-linear load is the input of most
power supplies, which use a bridge rectifier and capacitive
input filter fed from the line. The peak-charging effect
which occurs on the input filter capacitor in these supplies
causes brief high-amplitude pulses of current to flow from
the power line, rather than a sinusoidal current in phase
with the line voltage. Such supplies present a power factor
to the line of less than one (i.e. they cause significant
current harmonics of the power line frequency to appear
at their input). If the input current drawn by such a supply
(or any other non-linear load) can be made to follow the
input voltage in instantaneous amplitude, it will appear
resistive to the AC line and a unity power factor will be
achieved.

To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the
input voltage, a way must be found to prevent that device
from loading the line except in proportion to the
instantaneous line voltage. The PFC section of the ML4824
uses a boost-mode DC-DC converter to accomplish this.
The input to the converter is the full wave rectified AC line
voltage. No bulk filtering is applied following the bridge
rectifier, so the input voltage to the boost converter ranges
(at twice line frequency) from zero volts to the peak value
of the AC input and back to zero. By forcing the boost

converter to meet two simultaneous conditions, it is
possible to ensure that the current which the converter
draws from the power line agrees with the instantaneous
line voltage. One of these conditions is that the output
voltage of the boost converter must be set higher than the
peak value of the line voltage. A commonly used value is
385VDC, to allow for a high line of 270VAC

rms

. The other

condition is that the current which the converter is
allowed to draw from the line at any given instant must be
proportional to the line voltage. The first of these
requirements is satisfied by establishing a suitable voltage
control loop for the converter, which in turn drives a
current error amplifier and switching output driver. The
second requirement is met by using the rectified AC line
voltage to modulate the output of the voltage control loop.
Such modulation causes the current error amplifier to
command a power stage current which varies directly with
the input voltage. In order to prevent ripple which will
necessarily appear at the output of the boost circuit
(typically about 10VAC on a 385V DC level) from
introducing distortion back through the voltage error
amplifier, the bandwidth of the voltage loop is deliberately
kept low. A final refinement is to adjust the overall gain of
the PFC such to be proportional to 1/V

, which linearizes

the transfer function of the system as the AC input voltage
varies.

Since the boost converter topology in the ML4824 PFC is
of the current-averaging type, no slope compensation is
required.

PFC SECTION

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
ML4824. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms
line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:

1) A current representing the instantaneous input voltage

(amplitude and waveshape) to the PFC. The rectified AC
input sine wave is converted to a proportional current
via a resistor and is then fed into the gain modulator at
I

. Sampling current in this way minimizes ground

noise, as is required in high power switching power
conversion environments. The gain modulator responds
linearly to this current.

2) A voltage proportional to the long-term rms AC line

voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
modulator at V

RMS

. The gain modulator's output is

inversely proportional to V

RMS2

(except at unusually

low values of V

RMS

where special gain contouring takes

over, to limit power dissipation of the circuit
components under heavy brownout conditions). The
relationship between V

RMS

and gain is called K, and is

illustrated in the Typical Performance Characteristics.

ML4824

3) The output of the voltage error amplifier, VEAO. The

gain modulator responds linearly to variations in this
voltage.

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:

VEAO

GAINMOD

RMS

(1)

More exactly, the output current of the gain modulator is
given by:

VEAO

GAINMOD

= ´

(

. )

where K is in units of V

-1

Note that the output current of the gain modulator is
limited to

200µA.

Current Error Amplifier

The current error amplifier's output controls the PFC duty
cycle to keep the average current through the boost
inductor a linear function of the line voltage. At the
inverting input to the current error amplifier, the output
current of the gain modulator is summed with a current
which results from a negative voltage being impressed
upon the I

SENSE

pin (current into I

SENSE

/3.5k

The negative voltage on I

SENSE

represents the sum of all

currents flowing in the PFC circuit, and is typically derived
from a current sense resistor in series with the negative
terminal of the input bridge rectifier. In higher power
applications, two current transformers are sometimes used,
one to monitor the I

of the boost MOSFET(s) and one to

monitor the I

of the boost diode. As stated above, the

inverting input of the current error amplifier is a virtual
ground. Given this fact, and the arrangement of the duty
cycle modulator polarities internal to the PFC, an increase
in positive current from the gain modulator will cause the
output stage to increase its duty cycle until the voltage on
I

SENSE

is adequately negative to cancel this increased

current. Similarly, if the gain modulator's output decreases,
the output duty cycle will decrease, to achieve a less
negative voltage on the I

SENSE

pin.

Cycle-By-Cycle Current Limiter

The I

SENSE

pin, as well as being a part of the current

feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection flip-
flop is reset by the clock pulse at the start of the next PFC
power cycle.

FUNCTIONAL DESCRIPTION

(Continued)

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

VEAO

IEAO

VFB

IAC

VRMS

ISENSE

2.5V

VEA

IEA

VREF

PFC

OUTPUT

GAIN

MODULATOR

Overvoltage Protection

The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to V

. When the

voltage on V

exceeds 2.7V, the PFC output driver is shut

down. The PWM section will continue to operate. The
OVP comparator has 125mV of hysteresis, and the PFC
will not restart until the voltage at V

drops below 2.58V.

The V

should be set at a level where the active and

passive external power components and the ML4824 are
within their safe operating voltages, but not so low as to
interfere with the boost voltage regulation loop.

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V

REF

to produce a soft-start characteristic on

the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.

There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier's

ML4824

FUNCTIONAL DESCRIPTION

(Continued)

open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4824's voltage error amplifier has a
specially shaped nonlinearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbations in
line or load conditions will cause the input to the voltage
error amplifier (V

) to deviate from its 2.5V (nominal)

value. If this happens, the transconductance of the voltage
error amplifier will increase significantly, as shown in the
Typical Performance Characteristics. This raises the gain-
bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristic.

The current amplifier compensation is similar to that of
the voltage error amplifier with the exception of the
choice of crossover frequency. The crossover frequency of
the current amplifier should be at least 10 times that of
the voltage amplifier, to prevent interaction with the
voltage loop. It should also be limited to less than 1/6th
that of the switching frequency, e.g. 16.7kHz for a
100kHz switching frequency.

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.

For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information for
the design of this class of PFC.

Oscillator (RAMP 1)

The oscillator frequency is determined by the values of R

and C

, which determine the ramp and off-time of the

oscillator output clock:

OSC

RAM P

DEADTIM E

(2)

The deadtime of the oscillator is derived from the
following equation:

RAMP

REF

H
G

K
J

125
375

(3)

at V

REF

= 7.5V:

RAMP

´ 0 51

The deadtime of the oscillator may be determined using:

DEADTIME

2 5

490

(4)

The deadtime is so small (t

RAMP

>> t

DEADTIME

) that the

operating frequency can typically be approximated by:

OSC

RAMP

(5)

EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:

kHz

OSC

RAMP

100

RAMP

= ´

0 51 1 10

Solving for R

x C

yields 2 x 10

-4

. Selecting standard

components values, C

= 470pF, and R

= 41.2k

The deadtime of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator deadtime, the Maximum PWM Duty Cycle
is typically 45%. In many applications, care should be
taken that C

not be made so large as to extend the

Maximum Duty Cycle beyond 50%. This can be
accomplished by using a stable 470pF capacitor for C

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4824 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing (at the PFC frequency in the ML4824-1, and at
twice the PFC frequency in the ML4824-2). The PWM is
capable of current-mode or voltage mode operation. In
current-mode applications, the PWM ramp (RAMP 2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage, and
is thereby representative of the current flowing in the
converter's output stage. DC I

LIMIT

, which provides cycle-

by-cycle current limiting, is typically connected to RAMP
2 in such applications. For voltage-mode operation or
certain specialized applications, RAMP 2 can be
connected to a separate RC timing network to generate a
voltage ramp against which V

will be compared. Under

these conditions, the use of voltage feedforward from the
PFC buss can assist in line regulation accuracy and
response. As in current mode operation, the DC I

LIMIT

input is used for output stage overcurrent protection.

ML4824

FUNCTIONAL DESCRIPTION

(Continued)

Figure 3. External Component Connections to V

No voltage error amplifier is included in the PWM stage
of the ML4824, as this function is generally performed on
the output side of the PWM's isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM's RAMP 2 input which
allows V

to command a zero percent duty cycle for

input voltages below 1.25V.

PWM Current Limit

The DC I

LIMIT

pin is a direct input to the cycle-by-cycle

current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.

OK Comparator

The V

OK comparator monitors the DC output of the PFC

and inhibits the PWM if this voltage on V

is less than its

nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to
its rated boost voltage, the soft-start begins.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM's
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (R

RAMP2

, C

RAMP2

), which will have a

minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed
by the following equation:

DELAY

´ 50

125

(6)

where C

is the required soft start capacitance, and

DELAY

is the desired start-up delay.

It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.

Solving for the minimum value of C

50
125

200

Generating V

The ML4824 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power
dissipation while at the same time delivering 10V of gate
drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying it. This can be easily done with a
single resistor in series with the Vcc pin, returned to a bias
supply of typically 18V to 20V. The resistor's value must be
chosen to meet the operating current requirement of the
ML4824 itself (19mA max) plus the current required by the
two gate driver outputs.

EXAMPLE:
With a V

BIAS

of 20V, a V

limit of 14.6V (max) and the

ML4824 driving a total gate charge of 110nC at 100kHz
(e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate
driver current required is:

kHz

GATEDRIVE

100

(7)

BIAS

14 6

180

(8)

To check the maximum dissipation in the ML4824, find
the current at the minimum V

(12.4V):

12 4

180

42 2

(9)

The maximum allowable I

is 55mA, so this is an

acceptable design.

The ML4824 should be locally bypassed with a 10nF and
a 1

F ceramic capacitor. In most applications, an

electrolytic capacitor of between 100

F and 330

F is also

required across the part, both for filtering and as part of
the start-up bootstrap circuitry.

ML4824

VCC

GND

VBIAS

10nF

CERAMIC

1µF

CERAMIC

RBIAS

ML4824

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock. The
error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will
be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.

In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation is
determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.

One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary "no-load" period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the first
stage is reduced. Calculation and evaluation have shown
that the 120Hz component of the PFC's output ripple
voltage can be reduced by as much as 30% using this
method.

TYPICAL APPLICATIONS

Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application
Note 33.

Figure 4. Typical Trailing Edge Control Scheme.

RAMP

VEAO

TIME

VSW1

TIME

REF

OSC

DFF

CLK

RAMP

CLK

SW2

SW1

VIN

ML4824

Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33.

AC INPUT

85 TO 265VAC

470nF

ML4824

3.15A

300m

BR1

4A, 600V

D12

1A, 50V

D13

1A, 50V

R2A

357k

R2B

357k

75k

13k

R1A

499k

R1B

499k

R12

27k

1nF

220pF

R11

750k

C19

1µF

470nF

R27

39k

C18

470pF

41.2k

R10

6.2k

C11

10nF

470nF

C30

330µF

R21

10nF

8A, 600V

100µF

R14

D10

1A, 20V

R7A

178k

R7B

178k

C12

10µF

50V

IRF840

IRF830

C13

100nF

C14

1µF

IEAO

IAC

ISENSE

VRMS

VDC

RAMP 1

RAMP 2

VEAO

VFB

VREF

VCC

PFC OUT

PWM OUT

GND

DC ILIMIT

IRF830

R15

C20

1µF

R28

180

12VDC

3.1mH

33µH

C21

1800µF

C24

1µF

RTN

D11

MBR2545CT

600V

C25

100nF

R17

R30

4.7k

15V

R22

8.66k

R25

2.26k

R20

1.1

C15

10nF

C16

1µF

C31

1nF

2.37k

82nF

8.2nF

C17

220pF

R19

220

R23

1.5k

R24

1.2k

C22

4.7µF

TL431

R26

10k

MOC

8102

C23

100nF

R18

220

L1: Premier Magnetics #TSD-734
L2: 33µH, 10A DC
T1: Premier Magnetics #TSD-736
T2: Premier Magnetics #TSD-735

Premier Magnetics: (714) 362-4211

ML4824

is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.

Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483;
5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959;
5,689,167; 5,714,897; 5,717,798. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any
liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of
others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application
herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.

DS4824-01

2092 Concourse Drive

San Jose, CA 95131

Tel: (408) 433-5200

Fax: (408) 432-0295

www.microlinear.com

PART NUMBER

PWM FREQUENCY

TEMPERATURE RANGE

PACKAGE

ML4824CP-1

1 x PFC

0°C to 70°C

16-Pin PDIP (P16)

ML4824CP-2

2 x PFC

0°C to 70°C

16-Pin PDIP (P16)

ML4824CS-1

1 x PFC

0°C to 70°C

16-Pin Wide SOIC (S16W)

ML4824CS-2

2 x PFC

0°C to 70°C

16-Pin Wide SOIC (S16W)

ML4824IP-1

1 x PFC

40°C to 85°C

16-Pin PDIP (P16)

ML4824IP-2

2 x PFC

40°C to 85°C

16-Pin PDIP (P16)

(Obsolete)

ML4824IS-1

1 x PFC

40°C to 85°C

16-Pin Wide SOIC (S16W)

ML4824IS-2

2 x PFC

40°C to 85°C

16-Pin Wide SOIC (S16W)

(Obsolete)

ORDERING INFORMATION

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML4824CS-1

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML4824CS-1