May 1997
ML4828
*
BiCMOS Phase Modulation/Soft Switching Controller
1
GENERAL DESCRIPTION
The ML4828 is a complete BiCMOS phase modulation
control IC suitable for full bridge soft switching converters.
Unlike conventional PWM circuits, the phase modulation
technique allows for zero voltage switching (ZVS)
transitions and square wave drive across the transformer.
The IC modulates the phases of the two sides of the bridge
to control output power.
The ML4828 can be operated in either voltage or current
mode. Both cycle-by-cycle current limit, integrating fault
detection, and soft start reset are provided. The under-
voltage lockout circuit features a 1.5V hysteresis with a
low starting current to allow off-line start up with a bleed
resistor. A shutdown function powers down the IC, putting
it into a low quiescent state.
The circuit can be operated at frequencies up to 1MHz.
The ML4828 contains four high current CMOS outputs
which feature high slew rate with low cross conduction.
*Some Packages Are End Of Life
BLOCK DIAGRAM
FEATURES
s
5V BiCMOS for low power and high frequency
(1MHz) operation
s
Full bridge phase modulation zero voltage switching
circuit with independent programmable delay times
s
Current or voltage mode operation capability
s
Cycle-by-cycle current limiting with integrating fault
detection and restart delay
s
Can be externally synchronized
s
Four 3
CMOS output drivers
s
Under-voltage lockout circuit with 1.5V hysteresis
8
+
DELAY B
DRIVER
DRIVER
DRIVER
+
2.5V REF
11
16 A2
15 B1
13 B2
+
ISS
IRST
FAULT
LOGIC
Q
Q
S
R
2
17
GND
1
R
A
R
B
5
V
REF
EAO
RAMP
SS
RST
I
LIM
SDN
DRIVER
DELAY A
A1
18
MOD
I
LIM
12
20
S
Q
R
Q
7
1.25V
2.5V
19
UVLO
10
9
EA+
EA
+
SYNC R
T
C
T
OSC
T
Q
Q
6
4
3
14
V
CC
ERROR
AMP
1V
2
ML4828
PIN DESCRIPTION
PIN
NAME
DESCRIPTION
1
R
A
A1
and A2
delay programming
resistor.
2
R
B
B1
and B2
delay programming
resistor
.
3
R
T
Oscillator charge current
programming resistor.
4
C
T
Oscillator timing capacitor.
5
REF
2.5V reference voltage.
6
SYNC
Synchronization input to oscillator.
7
SS
Soft start capacitor connection.
8
EAO
Error amplifier output.
9
EA-
Error amplifier inverting input.
10
EA+
Error amplifier non-inverting input.
PIN CONNECTION
PIN
NAME
DESCRIPTION
11
RAMP
RC network for phase modulator
ramp input.
12
RST
RC network for reset and integrating
fault detect.
13
B2
B2
driver output.
14
V
CC
Power supply
15
B1
B1
driver output.
16
A2
A2 driver output.
17
GND
Ground.
18
A1
A1 driver output.
19
SHDN
Active low device shutdown.
20
I
LIMIT
Current limit control input
ML4828
20-Pin DIP (P20)
20-Pin SOIC (S20)
R
A
R
B
R
T
C
T
REF
SYNC
SS
EA0
EA
EA+
I
LIM
SDN
A1
GND
A2
B1
V
CC
B2
RST
RAMP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
3
ML4828
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, R
A
= R
B
= 33.3k
, R
T
= 16k
, C
T
= 270
P
F, V
CC
= 5V, T
A
= Operation Temperature Range
(Notes 1,2)
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNITS
OSCILLATOR
Initial Accuracy
T
A
= 25
C
340
360
380
kHz
Voltage Stability
4.5V < V
CC
< 5.5V
4
5.3
%/V
Temperature Stability
2
%
Total Variation
Line, temp.
325
400
kHz
C
T
Discharge Current
V
CT
= 2V
1.15
1.5
mA
Ramp Peak
2.6
V
Ramp Valley
1.12
V
REFERENCE
Initial Accuracy
T
A
= 25
C, I
O
= 250
A
2.475
2.5
2.525
V
Line Regulation
4.5V < V
CC
< 6.5V
0.2
1
%/V
Load Regulation
100
A to 1mA
0.5
6
mV
Temperature Stability
0.45
%
Total Variation
Line, Load, & Temp
2.44
2.54
V
Long Term Stability
T
J
= 125
C, 1000 hrs
5
25
mV
Short Circuit Current
V
REF
= 0V
10
23
35
mA
ERROR AMPLIFIER
Input Offset Voltage
20
20
mV
Input Common-Mode Range
0
1.75
V
Open Loop Gain
1V < V
O
< 2.7V
60
80
dB
PSRR
4.5V < V
CC
< 6.5V
60
80
dB
Output Sink Current
V
O
= 0.5V
1.2
1.9
mA
Output Source Current
V
O
= 2.7V
0.35
1.1
mA
Output High Voltage
I
SOURCE
= 500
A
2.6
2.85
V
Output Low Voltage
I
SINK
= 500
A
0.1
0.2
V
Unity Gain Bandwidth
7
10
MHz
Slew Rate
5
10
V/
s
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
V
CC ..................................................................................................
7V
Output Current, Source or Sink (A1, A2, B1, B2)
Pulse (0.5
s) ......................................................... 1.0A
Analog Inputs (EA+, EA, EAO,
RST, RAMP, RST)............................ 0.3V to V
CC
+ 0.3V
R
T
Source Current .................................................... 1mA
Error Amplifier Output Current ................................
2mA
Soft Start Discharge Current ...................................... 5mA
C
T
Charging Current ................................................. 1mA
Junction Temperature .............................................. 150
C
Storage Temperature Range ...................... 65
C to 150
C
Lead Temperature (Soldering 10 sec.) ...................... 260
C
Thermal Resistance (
JA
)
Plastic DIP ........................................................ 67
C/W
Plastic SOIC ..................................................... 95
C/W
OPERATING CONDITIONS
Temperature Range
ML4828CX ................................................. 0
C to 70
C
ML4828IX ............................................... 40
C to 85
C
4
ML4828
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNITS
PHASE MODULATOR
EAO Zero Duty Cycle Threshold
V
RT
= 0V
0
0.5
0.9
V
RAMP Delay to Output
50
80
ns
RAMP Discharge Current
48
95
mA
SOFT-START
Charge Current
V
SS
= 4V
25
50
A
Discharge Current
V
SS
= 1V
6
10
13.2
mA
CURRENT LIMIT/SHUTDOWN
Current Limit Threshold
0.9
1.0
1.1
V
Pin 20 Delay to Output
(Note 1)
50
ns
Pin 12 Shutdown Threshold
1.0
1.1
1.5
V
Pin 12 Restart Threshold
2.2
2.4
2.6
V
Pin 12 Charging Current
350
460
550
A
SDN Shutdown Threshold
1.05
1.6
2.05
V
OUTPUT
Output Low Level
I
OUT
= 20 mA
0.01
0.1
V
I
OUT
= 100 mA
0.1
0.3
V
Output High Level
I
OUT
= 20 mA
4.9
4.95
V
I
OUT
= 100 mA
4.6
4.7
V
Rise/Fall Time
C
L
= 1000pF, (Note 1)
5
7
ns
ZVS Programmable Delay
240
280
315
ns
Delay Mismatch
0
ns
R
A
/R
B
Reference Voltage
2.45
2.5
2.55
V
UNDER VOLTAGE LOCKOUT
Start Threshold
5.1
5.85
6.6
V
Stop Threshold
4.1
4.2
4.3
V
SUPPLY
Start Up Current
V
CC
<
6V
0.6
1
mA
Shutdown Current
100
500
A
I
CC
V
CC
= 5V, C
L
= 1000pF, T
A
= 25
C
5
7
mA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: V
CC
must be brought above the UVLO start voltage (6V) before dropping to V
CC
= 5V to ensure start-up.
5
ML4828
FUNCTIONAL DESCRIPTION
PHASE MODULATOR
The ML4828 controls the power of a full bridge power
section by modulating the phases of the switches of the A
and B sides (Figure 1). The power cycle starts with A2 and
B1 high, as shown in the timing diagram (Figure 2).
1. With A2 and B1 high, Q1 and Q2 are ON. Current
flows through the primary of the transformer, and
power is delivered to the output through the secondary
winding (not shown).
2. After either the
MOD or I
LIM
comparator trips, B1
goes low, turning off Q2. Energy in the primary winding
charges the parasitic capacitances of Q2 and Q3 to
+VIN during t
DB
.
3. B2 goes high after time t
DB
, which is set by the resistor
connected from RB (pin 2) to GND. t
DB
should be set
large enough such that the source of Q3 has been
charged to +VIN. At this time, Q3 turns on at zero
voltage. The transformer is now effectively shorted
through Q1 and Q3, with the primary magnetizing
current circulating in the loop formed by the
transformer primary, Q1, and Q3.
4. CLOCK then goes high and A2 goes low, while A1
remains low for time t
DA
, which is set by the resistor
connected from RA (pin 1) to GND. During this time,
both Q1 and Q4 are OFF. The primary magnetizing
current discharges the parasitic capacitances of Q1 and
Q4 to GND.
5. A1 goes high after time t
DA
. At this point, the drain of
Q4 is discharged to GND, and Q4 turns on at zero
voltage. With both Q3 and Q4 ON, a new power cycle
starts, and power is delivered to the output.
The above sequence is then repeated with the roles of
side A and B interchanged.
The ML4828 can also be used in current mode by sensing
the load current on the RAMP input (pin 11).
Figure 2. Phase Modulation control waveforms (Shaded areas indicate a power cycle).
B2
B1
A2
A1
I
LIM
R
SENSE
T
B
Q3
Q2
Q4
Q1
T
A
TRANSFORMER
L
LEAKAGE
B
A
+VIN
ML4828
T
B
T
A
Figure 1. Simplified diagram of Phase Modulated power Outputs.
t
DA
t
DA
t
DB
t
DA
t
DB
t
PD1
t
PD1
t
DB
t
PD1
C
T
CLOCK
A2
A1
B1
B2
B
A
6
ML4828
SETTING THE OSCILLATOR FREQUENCY
The ML4828 switching frequency is determined by the
charge and discharge times of the network connected to
the R
T
and C
T
pins. Figure 3 shows the relationships
between the internal clock and the charge and discharge
times.
t
DISCHARGE
RAMP PEAK
RAMP VALLEY
t
CHARGE
2.5V
1.25V
INTERNAL
CLOCK
Figure 3. Internal Oscillator Timing.
The frequency of the oscillator is:
f
t
t
OSC
CHARGE
DISCHARGE
=
+
1
(1)
The ramp peak is 2.5V and the ramp valley is 1.25V,
giving a ramp range of 1.25V. The charging current is set
externally through the resistor R
T
:
I
V
R
CHARGE
T
=
2 5
.
(2)
while the discharging current is fixed at 1.4 mA. The
charge and discharge times can be determined by:
t
C
V
I
C
R
CHARGE
T
CHARGE
T
T
=
=
1 25
2
.
(3)
t
C
V
I
C
V
mA
DISCHARGE
T
DISCHARGE
T
=
=
1 25
1 25
1 4
.
.
.
(4)
The oscillator frequency can then be found by substituting
the results of equations 3 and 4 into equation 1. This
frequency activates a T flip-flop which generates the
output pulses. The T flip-flop acts as a frequency divider
(
2), so the output frequency will be:
f
f
OUT
OSC
=
2
(5)
ERROR AMPLIFIER
The ML4828 error amplifier has a 10MHz bandwidth and
a 10V/
s slew rate. Figure 4 gives the Bode plot of the
error amplifier.
100
80
60
40
20
0
20
180
135
90
45
0
100
1K
10K
100K
1M
10M
100M
FREQUENCY
GAIN
PHASE (Degrees)
GAIN
PHASE
Figure 4. Error Amplifier Open-Loop Gain
and Phase vs. Frequency.
OUTPUT DRIVERS
The ML4828 has four high-current CMOS output drivers,
each capable of 1A peak output current. These outputs
have been designed to quickly switch the gates of power
MOSFET transistors via a gate drive transformer. For higher
power applications, the outputs can be connected to
external MOSFET drivers.
The output phase delay times are set by charging an
internal 6.7pF capacitor up to the REF voltage (2.5V) via a
current that is externally programmed through R
A
and R
B
,
for the side A and side B drivers, respectively. The
charging current and delay time for side A are given by:
I
V
R
A
A
=
2 5
.
(6)
t
pF R
DA
A
=
6 7
.
(7)
The same equations can be applied to R
B
. For example,
with R
A
= 33k
:
t
pF
k
ns
DA
=
=
6 7
33
220
.
(8)
7
ML4828
C
RST
+
R
RST
12
+
7
20
INHIBIT
OUTPUT
UNDER-VOLTAGE
LOCKOUT
CLOCK
2.5V
1.25V
RST
R
SENSE
R1
C1
V+
I
RST
S
Q
R
TERMINATE
PWM CYCLE
V+
I
1
I
SWITCH
I
LIM
1V
SS
C
SS
SOFT START TIME CONSTANT
During start up, the output voltage is much lower than the
steady state value. Without soft start circuitry, the error
amplifier output (EAO) would swing all the way to the
upper limit and the phase modulator would issue pulses
with full duty cycle, possibly causing output overshoot. To
ensure smooth start up, EAO (pin 8) is pulled low and
then gradually released through the charging of an
external soft start capacitor connected to SS (pin 7). The
soft start charging current is internally set at 25
A. Hence,
EAO will rise with a time constant of:
dv
dt
A
C
SS
=
25
(9)
For example, with C
SS
= 25
F, the soft start rate of change
will be:
dv
dt
A
F
V
s
=
=
25
25
1
(10)
FAULT TIME CONSTANT AND RESTART DELAY
Figure 5 shows the internal circuitry and external
components involved in fault detection. During normal
operation, RST (pin 12) is discharged to ground through
the external resistor R
RST
. The I
LIM
comparator has a
threshold of 1V. R
SENSE
is selected so that the voltage
across it will be equal to the I
LIM
threshold at the
maximum desired I
SWITCH
current. When the voltage
across R
SENSE
exceeds 1V, the I
LIM
comparator trips,
terminating the present power cycle, and at the same time
activating the fault logic to turn on the 500
A current
source I
RST
. This current charges the reset capacitor C
RST
.
For proper design, R
RST
should be very large (in the order
of 100k
). This will cause nearly all of the I
RST
current
(approximately 500
A) to go into charging C
RST
at a rate of:
dv
dt
A
C
RST
=
500
(11)
in volts per second. I
RST
will be turned off at the beginning
of the next clock cycle. If the current limit condition is
removed, RST will be gradually discharged to ground,
and normal operation resumes as shown in Figure 6.
Figure 5. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.
Figure 6. I
LIM
and Resulting RC
RST
Waveforms During Load Surge.
1V
2.5V
V(PIN 20)
V(PIN 12)
8
ML4828
1V
2.5V
V(PIN 20)
V(PIN 12)
If the current limit condition persists, then I
RST
will be
reactivated, thus charging C
RST
to a higher level as shown
in Figure 7. Eventually, the voltage at RST will exceed
2.5V, and the soft start comparator will trip, shutting down
all power drivers and inhibiting any further delivery of
power. At the same time, the soft start capacitor C
SS
is
discharged to prepare for the next start up cycle.
During the I
LIM
shutdown, I
RST
is turned off, and C
RST
is
discharged through R
RST
with a time constant of:
t
R
C
RST
RST
RST
=
(12)
When the condition causing the current limit is removed,
R
RST
will discharge C
RST
with a time constant of t
RST.
When the voltage at RST (pin 12) drops to 1.25V, the soft
start comparator and the converter will undergo a start up
cycle. The restart delay (t
D(RST)
) is given by:
t
t
D RST
RST
(
)
.
=
1 39
(13)
For example, with C
RST
= 25
F and R
RST
= 240k
:
dv
dt
A
F
V
s
=
=
500
25
20
(14)
and
t
k
F
s
D RST
(
)
(
)
.
.
=
=
240
25
1 39
8 3
(15)
Since the threshold for shutdown is 2.5V, the controller
will shut down after approximately 125ms. After the
converter recovers form the current limit condition, the
controller will reactivate after 8.3s.
UNDERVOLTAGE LOCKOUT
During start-up, the ML4828 draws very little current
(typically 150
A) and V
REF
is disabled. When V
CC
rises
above 6.0V, the internal circuitry and V
REF
are enabled,
and will stay enabled until V
CC
falls below the 4.5V UV
lockout threshold.
SHUTDOWN FUNCTION
The ML4828 can be externally shut down by bringing
SDN (pin 19) low. The shutdown threshold (V
SD
) is given
by
V
V
SD
CC
=
0 33
.
(16)
For example, if V
CC
= 5V, then V
SD
= 1.67V. As long as
2.4V < V
CC
< 6.0V, the SDN pin will be TTL compatible.
Figure 7. I
LIM
and Resulting RC
RST
Waveforms During Short Circuit.
10
ML4828
SEATING PLANE
0.291 - 0.301
(7.39 - 7.65)
PIN 1 ID
0.398 - 0.412
(10.11 - 10.47)
0.498 - 0.512
(12.65 - 13.00)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.022 - 0.042
(0.56 - 1.07)
0.095 - 0.107
(2.41 - 2.72)
0.005 - 0.013
(0.13 - 0.33)
0.090 - 0.094
(2.28 - 2.39)
20
0.007 - 0.015
(0.18 - 0.38)
0 - 8
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
Package: S20
20-Pin SOIC
PHYSICAL DIMENSIONS
inches (millimeters)
11
ML4828
SEATING PLANE
0.240 - 0.260
(6.09 - 6.61)
PIN 1 ID
0.295 - 0.325
(7.49 - 8.26)
1.010 - 1.035
(25.65 - 26.29)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
20
0 - 15
1
0.055 - 0.065
(1.40 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.060 MIN
(1.52 MIN)
(4 PLACES)
Package: P20
20-Pin PDIP
PHYSICAL DIMENSIONS
inches (millimeters) (Continued)
1
1
ML4828
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4828CP
0
C to 70
C
20-Pin DIP (P20)
ML4828CS
0
C to 70
C
20-Pin DIP (S20)
(EOL)
ML4828IP
40
C to 85
C
20- Pin DIP (P20)
(EOL)
ML4828IS
40
C to 85
C
20- Pin SOIC (S20)
(EOL)
ORDERING INFORMATION
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
DS4828-01
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Telex: 275906
Micro Linear 1997
Micro Linear
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
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