July 2000
PRELIMINARY
ML4833
*
Electronic Dimming Ballast Controller
GENERAL DESCRIPTION
The ML4833 is a complete solution for a dimmable or a
non-dimmable, high power factor, high efficiency
electronic ballast. The BiCMOS ML4833 contains
controllers for "boost" type power factor correction as
well as for a dimming ballast. The ML4833 was designed
to minimize the number of external components required
to build an electronic ballast.
The PFC circuit uses a new, simple PFC topology which
requires only one loop for compensation. This system
produces a power factor of better than 0.99 with low
input current THD. An overvoltage protection comparator
inhibits the PFC section in the event of a lamp out or lamp
failure condition.
The ballast controller section provides for programmable
starting sequence with individually adjustable preheat and
lamp out-of-socket interrupt times. The IC controls lamp
output power through feedback. The ML4833 provides a
power down input which reduces power to the lamp, for
GFI, end of life, etc.
FEATURES
s
Complete power factor correction and dimming
ballast control in one IC
s
Low distortion, high efficiency continuous boost,
peak current sensing PFC section
s
Programmable start scenario for rapid or
instant start lamps
s
Lamp current feedback for dimming control
s
Variable frequency dimming and starting
s
Programmable restart for lamp out condition to
reduce ballast heating
s
Internal over-temperature shutdown replaces
external heat sensor
s
PFC overvoltage comparator eliminates output
"runaway" due to load removal
s
Low start-up current <0.5mA
s
Power reduction pin for end of life and GFI detectors
1
BLOCK DIAGRAM
6
R
SET
VARIABLE FREQUENCY
OSCILLATOR
7
R
T
/C
T
9
R
X
/C
X
PRE-HEAT
AND INTERRUPT
TIMERS
CONTROL
&
GATING LOGIC
3
PDWN
10
C
RAMP
POWER
FACTOR
CONTROLLER
UNDER-VOLTAGE
AND THERMAL
SHUTDOWN
OUTPUT
DRIVERS
2
PIFB
1
PEAO
18
PVFB/OVP
V
REF
17
PFC OUT
15
GND
11
VCC
16
PGND
12
OUT B
13
OUT A
14
LFB OUT
5
LAMP FB
4
INTERRUPT
8
(* Indicates part is End Of Life as of July 1, 2000)
ML4833
2
PIN CONFIGURATION
PIN# NAME
FUNCTION
PIN# NAME
FUNCTION
1
PEAO
PFC error amplifier output and
compensation node.
2
PIFB
Sensing of the inductor current and
peak current sense point of the PFC
cycle by cycle current limit
comparator.
3
PDWN
A one volt comparator threshold that
switches the operating frequency to
the preheat frequency when exceeded.
4
LAMP FB
Inverting input of an error amplifier
used to sense (and regulate) lamp arc
current. Also the input node for
dimming control.
5
LFB OUT
Output of the lamp current error
transconductance amplifier used for
lamp current loop compensation.
6
R
SET
External resistor which sets oscillator
F
MAX
, and R(X)/C(X) charging current.
7
R
T
/C
T
Oscillator timing components.
PIN DESCRIPTION
8
INTERRUPT Input used for lamp-out detection and
restart. A voltage less than 1.25 volts
resets the chip and causes a restart
after a programmable interval.
9
R
X
/C
X
Sets the timing for the preheat,
dimming lockout, and interrupt.
10 C
RAMP
Integrated voltage of the error
amp out.
11 GND
Ground.
12 P GND
Power ground for the IC.
13 OUT B
Ballast MOSFET drive output.
14 OUT A
Ballast MOSFET drive output.
15 PFC OUT
Power Factor MOSFET drive output.
16 VCC
Positive supply for the IC.
17 V
REF
Buffered output for the 7.5V voltage
reference.
18 PVFB/OVP
Inverting input to PFC error amplifier
and OVP comparator input.
ML4833
18-Pin DIP (P18)
PEAO
PIFB
PDWN
LAMP FB
LFB OUT
R
SET
R
T
/C
T
INTERRUPT
R
X
/C
X
PVFB/OVP
V
REF
VCC
PFC OUT
OUT A
OUT B
P GND
GND
C
RAMP
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TOP VIEW
ML4833
18-Pin SOIC (S18)
PVFB/OVP
V
REF
VCC
PFC OUT
OUT A
OUT B
P GND
GND
C
RAMP
PEAO
PIFB
PDWN
LAMP FB
LFB OUT
R
SET
R
T
/C
T
INTERRUPT
R
X
/C
X
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
TOP VIEW
ML4833
3
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, R
SET
= 22.1k, R
T
= 15.8k
W, C
T
= 1.5nF, C
VCC
= 1F, V
CC
= 12.5V. (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Lamp Current Amplifier (LAMP FB, LFB OUT)
Input Bias Current
0.3
1.0
A
Small Signal Transconductance
35
65
105
W
Input Voltage Range
0.3
5.0
V
Output Low
Voltage at LAMP FB = 3V, R
L
=
0.2
0.4
V
Output High
Voltage at LAMP FB = 2V, R
L
=
7.1
7.5
7.8
V
Source Current
Voltage at LAMP FB = 0V,
LFB OUT = 7V, T
A
= 25C
0.05
0.15
0.25
mA
Sink Current
Voltage at LAMP FB = 5V,
LFB OUT = 0.3V, T
A
= 25C
0.05
0.12
0.22
mA
PFC Voltage Feedback Amplifier (PEAO, PVFB/OVP)
Input Bias Current
0.3
1.0
A
Small Signal Transconductance
35
65
105
W
Input Voltage Range
0.3
5.0
V
Output Low
Voltage at PVFB = 3V, R
L
=
0.2
0.4
V
Output High
Voltage at PVFB = 2V, R
L
=
6.5
6.8
7.1
V
Source Current
Voltage at PVFB/OVP = 0V,
PEAO = 6V, T
A
= 25C
0.05
0.15
0.25
mA
Sink Current
Voltage at PVFB/OVP = 3V,
PEAO = 0.3V, T
A
= 25C
0.03
0.07
0.16
mA
PFC Current -- Limit Comparator (PIFB)
Current-Limit Threshold
0.90
1.05
1.15
V
Propagation Delay
100mV step and 100mV overdrive
100
ns
Oscillator
Initial Accuracy
T
A
= 25C
72
76
80
kHz
Voltage Stability
V
CCZ
4.5V < V
CC
<V
CCZ
0.5V
1
%
Temperature Stability
2
%
Total Variation
Line, temperature
69
83
kHz
Ramp Valley to Peak
2.5
V
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Supply Current (I
CC
) ............................................... 60mA
Output Current, Source or Sink
(OUT A, OUT B, PFC OUT) DC ......................... 250mA
Output Energy (capacitive load per cycle).............. 1.5 mJ
Analog Inputs
(LAMP FB, INTERRUPT, VCC) ........... 0.3V to V
CC
2V
PIFB input voltage ......................................... 1.5V to 2V
Maximum Forced Voltage
(PEAO, LFB OUT) ................................... 0.3V to 7.7V
Maximum Forced Current (PEAO, LFB OUT) ........ 20mA
Junction Temperature ............................................ 150C
Storage Temperature Range ..................... 65C to 150C
Lead Temperature (Soldering 10 sec.) .................... 260C
Thermal Resistance (
q
JA
)
ML4833CP ...................................................... 70C/W
ML4833CS .................................................... 100C/W
OPERATING CONDITIONS
Temperature Range ........................................ 0C to 85C
W
W
ML4833
4
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator (Continued)
C
T
Charging Current
Voltage at LAMP FB = 3V,
R
T
/C
T
= 2.5V, R
X
/C
X
= 0.9V (Preheat)
90
110
130
A
LAMP FB = 3V, R
T
/C
T
= 2.5V,
R
X
/C
X
= Open
180
220
260
A
C
T
Discharge Current
Voltage at R
T
/C
T
= 2.5V
4.0
5.5
7.0
mA
Output Drive Deadtime
0.65
1
1.35
s
Reference Section
Output Voltage
T
A
= 25C, I
O
= 1mA
7.4
7.5
7.6
V
Line regulation
V
CCZ
4.5V < V
CC
< V
CCZ
0.5V
2
35
mV
Load regulation
1mA < I
O
< 5mA
2
15
mV
Temperature stability
0.4
%
Total Variation
Line, load, temp
7.35
7.65
V
Output Noise Voltage
10Hz to 10kHz
50
V
Long Term Stability
T
J
= 125C, 1000 hrs
5
mV
Preheat and Interrupt Timer (R
X
/C
X
where R
X
= 680k, C
X
= 4.7F)
Initial Preheat Period
0.8
s
Subsequent Preheat Period
0.7
s
Start Period
1.2
s
Interrupt Period
5.7
s
R
X
/C
X
Charging Current
24
28
33
A
R
X
/C
X
Open Circuit Voltage
V
CC
< Start-up threshold
0.4
0.7
1.0
V
R
X
/C
X
Maximum Voltage
7.0
7.3
7.7
V
Input Bias Current
Voltage at C
RAMP
= 1.2V
0.1
A
Preheat Lower Threshold
1.05
1.22
1.36
V
Preheat Upper Threshold
4.2
4.7
5.1
V
Interrupt Recovery Threshold
1.05
1.22
1.36
V
Start Period End Threshold
6.05
6.6
7.35
V
Interrupt Input (INTERRUPT)
Interrupt Threshold
1.1
1.22
1.4
V
Input Bias Current
0.1
A
R
SET
Voltage
2.4
2.5
2.6
V
OVP Comparator (PVFB/OVP)
OVP Threshold
2.63
2.73
2.83
V
Hysteresis
0.18
0.23
0.27
V
Propagation Delay
1.4
s
ML4833
5
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Outputs (OUT A, OUT B, PFC OUT)
Output Voltage Low
I
OUT
= 20mA
0.1
0.2
V
I
OUT
= 200mA
1.0
2.0
V
Output Voltage High
I
OUT
= 20mA
V
CC
0.2
V
CC
0.1
V
I
OUT
= 200mA
V
CC
2.0
V
CC
1.0
V
Output Voltage Low in UVLO
I
OUT
= 10mA, V
CC
< Start-up threshold
0.2
V
Output Rise/Fall Time
C
L
= 1000pF
20
ns
Under-Voltage Lockout and Bias Circuits
IC Shunt Protection Voltage (V
CCZ
)
I
CC
= 15mA
14.2
15.0
15.8
V
Start-up Current
V
CC
- Start-up threshold
0.34
0.48
mA
Operating Current
V
CC
= 12.5V,
5.5
8.0
mA
Voltage at LAMP FB = 0V,
LFB OUT = 2.3, PVFB/OVP = 2.3V
PIFB = Open
Start-up Threshold
V
CC
1.2 V
CCZ
1.0 V
CC
0.8
V
Shutdown Threshold
V
CC
5.3 V
CCZ
4.8 V
CC
4.3
V
Shutdown Temperature (T
DWN
)
(Note 2)
130
C
Hysteresis (T
DWN
)
30
C
PDWN
PDWN Threshold
0.9
1.0
1.1
V
Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
Note 2: Junction temperature.
ML4833
6
FUNCTIONAL DESCRIPTION
OVERVIEW
The ML4833 consists of peak current controlled
continuous boost power factor front end section with a
flexible ballast control section. Start-up and lamp-out
retry timing are controlled by the selection of external
timing components, allowing for control of a wide variety
of different lamp types. The ballast section controls the
lamp power using frequency modulation (FM) with
additional programmability provided to adjust the VCO
frequency range. This allows for the IC to be used with a
variety of different output networks. Figure 1 depicts a
detailed block diagram of ML4833.
POWER FACTOR SECTION
The ML4833 power factor section is a peak current
sensing boost mode PFC control circuit in which only
voltage loop compensation is needed. It is simpler than a
conventional average current control method. It consists
of a voltage error amplifier, a current sense amplifier (no
compensation is needed), an integrator, a comparator, and
a logic control block. In the boost topology, power factor
correction is achieved by sensing the output voltage and
the current flowing through the current sense resistor. Duty
cycle control is achieved by comparing the integrated
voltage signal of the error amplifier and the voltage
across R
SENSE
. The duty cycle control timing is shown in
Figure 2. Setting minimum input voltage for output
regulation can be achieved by selecting C
RAMP
according
to equation 1.
C
PEAO
K
D Ts
s
P
V
V
V
L
D Ts
R
RAMP
MAX
OUT
IN
OUT
IN
SENSE
=
-
-
{
}
-
-
-
22
1
1 1
1
2
2
2
1
8
(
)
.
(
)
(1)
OVERVOLTAGE PROTECTION AND INHIBIT
The OVP pin serves to protect the power circuit from
being subjected to excessive voltages if the load should
change suddenly (lamp removal). A divider from the high
voltage DC bus sets the OVP trip level. When the voltage
on PVFB/OVP exceeds 2.75V, the PFC transistor are
inhibited. The ballast section will continue to operate.
6
R
SET
R
T
/C
T
VCC
V
REF
GND
2.5V
PVFB/OVP
PEAO
C
RAMP
PIFB
7
R
X
/C
X
9
16
17
11
18
1
10
2
OUT B
13
+
+
+
+
+
2.5V
1.0V
+
1.25V
1.0V
2.75V
PREHEAT
TIMER
OSC
CLK
UNDER-VOLTAGE
THERMAL SHUTDOWN
REFOK
+
T Q
PGND
12
OUT A
14
PFC OUT
15
PDWN
3
INTERRUPT
8
LFB OUT
5
LAMP FB
4
OVP
I
SENSE
AMPLIFIER
ILIM
R
S
Q
R
S
Q
V TO I
Figure 1. ML4833 Detailed Block Diagram
ML4833
7
Figure 2. ML4833 PFC Controller Section
+
+
L
A
M
P
L
A
M
P
LAMP
NETWORK
INVERTER
RA
SW2
L
SW1
R
SENSE
SINE
RB
V
OUT
EMI
FILTER
14
2
PIFB
C
RAMP
C1
C2
R1
C
RAMP
OUT A
PVFB/OVP
18
A
S
VREF1
OSC
SINE
RAMP
CLK
PFC OUT
CLK
R
Q
V TO I
PEAO
10
PEAO
1
TRANSCONDUCTANCE AMPLIFIERS
The PFC voltage feedback amplifier is implemented as an
operational transconductance amplifier. It is designed to
have low small signal forward transconductance such that
a large value of load resistor (R1) and a low value
ceramic capacitor (<1F) can be used for AC coupling
(C1) in the frequency compensation network. The
compensation network shown in Figure 3 will introduce a
zero and a pole at:
f
R C
f
R C
Z
P
=
=
1
2
1
2
1 1
1 2
(2)
+
18
2.5V
PVFB/OVP
R1
C1
C2
Figure 3. Compensation Network
ML4833
8
The oscillator frequency is determined by the following
equations:
F
t
t
OSC
CHG
DIS
=
+
1
(3)
and
t
R C In
V
I
R
V
V
I
R
V
CHG
T T
REF
CH
T
TL
REF
CH
T
TH
=
+
-
+
-
(4)
The oscillator's minimum frequency is set when I
CH
= 0
where:
F
R C
OSC
T T
1
0 51
.
(5)
Figure 4 shows the output configuration for the
operational transconductance amplifiers.
CURRENT
MIRROR
IN
OUT
CURRENT
MIRROR
IN
OUT
gmV
IN
io = gmV
IN
IQ +
2
gmV
IN
IQ
2
Figure 4. Output Configuration
A DC path to ground or V
CC
at the output of the
transconductance amplifiers will introduce an offset error.
The magnitude of the offset voltage that will appear at the
input is given by V
OS
= io/gm. For an io of 1A and a gm
of 0.05
W
the input referred offset will be 20mV.
Capacitor C1 as shown in Figure 3 is used to block the
DC current to minimize the adverse effect of offsets.
Slew rate enhancement is incorporated into all of the
operational transconductance amplifiers in the ML4833.
This improves the recovery of the circuit in response to
power up and transient conditions. The response to large
signals will be somewhat non-linear as the transconductance
amplifiers change from their low to high transconductance
mode. This is illustrated in Figure 5.
V
IN
Differential
Linear Slope Region
0
i
O
Figure 5. Transconductance Amplifier Characteristics
BALLAST OUTPUT SECTION
The IC controls output power to the lamps via frequency
modulation with non-overlapping conduction. This means
that both ballast output drivers will be low during the
discharging time t
DIS
of the oscillator capacitor C
T
.
OSCILLATOR
The VCO frequency ranges are controlled by the output
of the LFB amplifier (R
SET
). As lamp current increases,
LFB OUT falls in voltage, causing the C
T
charging current
to increase, thereby causing the oscillator frequency to
increase. Since the ballast output network attenuates high
frequencies, the power to the lamp will be decreased.
17
+
1.25/3.75
7
C
T
V
REF
I
CHG
V
REF
CONTROL
R
T
/C
T
R
T
5.5mA
CLOCK
C
T
V
TH
= 3.75V
V
TL
= 1.25V
t
DIS
t
CHG
Figure 6. Oscillator Block Diagram and Timing
W
ML4833
9
This assumes that t
CHG
>> t
DIS
.
When LFB OUT is high, I
CH
= 0 and the minimum
frequency occurs. The charging current varies according
to two control inputs to the oscillator:
1. The output of the preheat timer
2. The voltage at LFB OUT (lamp feedback amplifier
output)
In preheat condition, charging current is fixed at
I
R
CHG PREHEAT
SET
(
)
.
=
2 5
(6)
In running mode, charging current decreases as the
voltage rises from 0V to V
OH
at the LAMP FB amplifier.
The highest frequency will be attained when I
CHG
is
highest, which is attained when voltage at LFB OUT
is at 0V:
I
R
CHG
SET
( )
0
5
=
(7)
Highest lamp power, and lowest output frequency are
attained when voltage at LFB OUT is at its maximum
output voltage (V
OH
).
In this condition, the minimum operating frequency of the
ballast is set per equation 5 above.
For the IC to be used effectively in dimming ballasts with
higher Q output networks a larger C
T
value and lower R
T
value can be used, to yield a smaller frequency excursion
over the control range (voltage at LFB OUT). The
discharge current is set to 5mA. Assuming that I
DIS
>>
I
RT
:
t
C
DIS VCO
T
(
)
600
(8)
IC BIAS, UNDER-VOLTAGE LOCKOUT AND
THERMAL SHUTDOWN
The IC includes a shunt clamp which will limit the
voltage at V
CC
to 15V (V
CCZ
). The IC should be fed with
a current limited source, typically derived from the
ballast transformer auxiliary winding. When V
CC
is below
V
CCZ
1.1V, the IC draws less than 0.48mA of quiescent
current and the outputs are off. This allows the IC to start
using a "bleed resistor" from the rectified AC line.
To help reduce ballast cost, the ML4833 includes a
temperature sensor which will inhibit ballast operation if
the IC's junction temperature exceeds 120C. In order to
use this sensor in lieu of an external sensor, care should
be taken when placing the IC to ensure that it is sensing
temperature at the physically appropriate point in the
ballast. The ML4833's die temperature can be estimated
with the following equation:
T
T
P
C W
J
A
D
+
+
(
/
)
65
(9)
VCCZ
V(ON)
V(OFF)
5.5mA
0.34mA
V
CC
I
CC
t
t
Figure 7. Typical V
CC
and I
CC
Waveforms when
the ML4833 is Started with a Bleed Resistor from
the Rectified AC Line and Bootstrapped from an
Auxiliary Winding.
STARTING, RE-START, PREHEAT AND INTERRUPT
The lamp starting scenario implemented in the ML4833
is designed to maximize lamp life and minimize ballast
heating during lamp out conditions.
The circuit in Figure 8 controls the lamp starting
scenarios: Filament preheat and lamp out interrupt. C
X
is
charged with a current of I
R(SET)
/4 and discharged through
R
X
. The voltage at C
X
is initialized to 0.7V (V
BE
) at power
up. The time for C
X
to rise to 4.8V is the filament preheat
time. During that time, the oscillator charging current
(I
CHG
) is 2.5/R
SET
. This will produce a high frequency for
filament preheat, but will not produce sufficient voltage
to ignite the lamp or cause significant glow current.
After cathode heating, the inverter frequency drops to F
MIN
causing a high voltage to appear to ignite the lamp. If
lamp current is not detected when the lamp is supposed
to have ignited, the lamp voltage feedback coming into
pin 8 remains below 1.25V, the C
X
charging current is
shut off and the inverter is inhibited until C
X
is discharged
by R
X
to the 1.2V threshold. Shutting off the inverter in
this manner prevents the inverter from generating
excessive heat when the lamp fails to strike or is out of
socket. Typically this time is set to be fairly long by
choosing a large value of R
X
.
ML4833
10
A summary of the operating frequencies in the various
operating modes is shown below.
Operating Mode
Operating Frequency
[F(MAX) to F(MIN)]
Preheat
2
Dimming
Lock-out
F(MIN)
Dimming
Control
F(MIN) to F(MAX)
9
8
R
X
C
X
6.8
+
1.2/4.8
HEAT
INHIBIT
0.625
R
SET
+
1.2/6.8
+
1.25V
DIMMING
LOCKOUT
R
X
/C
X
INTERRUPT
Q
R
S
Figure 8. Lamp Preheat and Interrupt Timers
LFB OUT is ignored by the oscillator until C
X
reaches
6.8V threshold. The lamps are therefore driven to full
power and then dimmed. The C
X
pin is clamped to
about 7.5V.
6.8
4.8
1.2
.65
0
>1.25
R
X
/C
X
HEAT
DIMMING
LOCKOUT
INT
INHIBIT
Figure 9. Lamp Starting and Restart Timing
TYPICAL APPLICATIONS
Figure 10 shows a schematic for a dimming power-factor
corrected 60W ballast, designed to operate two F32T8
fluorescent lamps connected in series.
ML4833
11
Figure 10. 220V Dimming Ballast
R1
R5
C2
R24
R4
R8
R2
C9
C23
C8
VIOLET
REMOTE MANUAL
DIMMER
010VDC
C3
R3
C22
R6
PEAO
PIFB
PDWN
LAMP FB
LFB OUT
R
SET
R
T
C
T
INTERRUPT
R
X
C
X
1
2
3
4
5
6
7
8
9
PVFB
V
REF
V
CC
PFC OUT
OUT A
OUT B
PGND
GND
C
RAMP
18
17
16
15
14
13
12
11
10
U1
ML4833
D3
D1
D4
D5
D6
D10
D2
HOT
NEUTRAL
F1
L1
L2
C2
C1
C3
C25
C20
C26
D9
D12
D13
T1
10
6
98
R20
R17
R18
R14
PDWN
R4
C7
C24
R3
R25
R5
R15
R23
C11
C4
C6
C5
R10
R16
R22
C10
R8
R13
R12
R11
Q1
D7
D11
D8
C13
C14
C16
C21
C12
C15
Q2
Q3
T2
6
72
3
1
56
10
8
1
C17
C19
R19
T4
TP4
6
7
4
3
2
1
9
8
R
R
Y
Y
B
B
R21
R2
R1
U1
C4
C1
220 VAC
TP2
TP3
TP1
TP5
T5
+
+
U2
3
8
7
1
2
5
6
R7
4
GRAY
R6
Q1
D2
D1
R7
T1
4
3
DIMMER CONTROL INTERFACE SUBASSEMBLY
+
ML4833
12
PHYSICAL DIMENSIONS
inches (millimeters)
SEATING PLANE
0.240 - 0.260
(6.09 - 6.61)
PIN 1 ID
0.295 - 0.325
(7.49 - 8.26)
0.890 - 0.910
(22.60 - 23.12)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
18
0 - 15
1
0.050 - 0.065
(1.27 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.045 MIN
(1.14 MIN)
(4 PLACES)
Package: P18
18-Pin PDIP
SEATING PLANE
0.291 - 0.301
(7.39 - 7.65)
PIN 1 ID
0.398 - 0.412
(10.11 - 10.47)
0.449 - 0.463
(11.40 - 11.76)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.022 - 0.042
(0.56 - 1.07)
0.095 - 0.107
(2.41 - 2.72)
0.005 - 0.013
(0.13 - 0.33)
0.090 - 0.094
(2.28 - 2.39)
18
0.009 - 0.013
(0.22 - 0.33)
0 - 8
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
Package: S18
18-Pin SOIC
ML4833
13
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4833CP (End of Life)
0C to 85C
Molded DIP (P18)
ML4833CS (Obsolete)
0C to 85C
SOIC (S18)
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or
design. Micro Linear does not assume any liability arising out of the application or use of any product
described herein, neither does it convey any license under its patent right nor the rights of others. The
circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no
warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of
others, and will accept no responsibility or liability for use of any application herein. The customer is urged
to consult with appropriate legal counsel before deciding on a particular application.
Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017;
5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
DS4833-01
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