2003 Microchip Technology Inc.
DS21711C-page 1
24AA01/24LC01B
Device Selection Table
Features
Single-supply with operation down to 1.8V
Low-power CMOS technology
- 1 mA active current typical
- 1
A standby current typical (I-temp)
Organized as 1 block of 128 bytes (1 x 128 x 8)
2-wire serial interface bus, I
2
CTM compatible
Schmitt Trigger inputs for noise suppression
Output slope control to eliminate ground bounce
100 kHz (24AA01) and 400 kHz (24LC01B)
compatibility
Self-timed write cycle (including auto-erase)
Page write buffer for up to 8 bytes
2 ms typical write cycle time for page write
Hardware write-protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection > 4,000V
1,000,000 erase/write cycles
Data retention > 200 years
8-lead PDIP, SOIC, TSSOP and MSOP packages
5-lead SOT-23 package
Standard and Pb-free finishes
Available for extended temperature ranges:
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
Description
The Microchip Technology Inc. 24AA01/24LC01B
(24XX01*) is a 1 Kbit Electrically Erasable PROM. The
device is organized as one block of 128 x 8-bit memory
with a 2-wire serial interface. Low-voltage design
permits operation down to 1.8V with standby and active
currents of only 1
A and 1 mA, respectively. The
24XX01 also has a page write capability for up to 8
bytes of data. The 24XX01 is available in the standard
8-pin PDIP, surface mount SOIC, TSSOP and MSOP
packages and is also available in the 5-lead SOT-23
package.
Package Types
Block Diagram
Part
Number
V
CC
Range
Max Clock
Frequency
Temp
Ranges
24AA01
1.8-5.5
400 kHz
(1)
I
24LC01B
2.5-5.5
400 kHz
I, E
Note 1:
100 kHz for V
CC
<2.5V
24
XX01
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
PDIP/SOIC/TSSOP/MSOP
SOT-23-5
1
5
4
3
24
XX01
SCL
V
SS
SDA
WP
V
CC
2
Note:
Pins A0, A1 and A2 are not used by the
24XX01 (no internal connections).
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
Memory
Control
Logic
I/O
Control
Logic
I/O
WP
SDA
SCL
V
CC
V
SS
R/W Control
1K I
2
C
TM
Serial EEPROM
24AA01/24LC01B
DS21711C-page 2
2003 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
()
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied ................................................................................................-65C to +125C
ESD protection on all pins
......................................................................................................................................................
4 kV
TABLE 1-1:
DC CHARACTERISTICS
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
V
CC
= +1.8V to +5.5V
Industrial (I):
T
A
= -40C to +85C
Automotive (E): T
A
= -40C to +125C
Param.
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
D1
V
IH
WP, SCL and SDA pins
--
--
--
--
--
D2
--
High-level input voltage
0.7 V
CC
--
--
V
--
D3
V
IL
Low-level input voltage
--
--
0.3 V
CC
V
--
D4
V
HYS
Hysteresis of Schmitt
Trigger inputs
0.05 V
CC
--
--
V
(Note)
D5
V
OL
Low-level output voltage
--
--
0.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
D6
I
LI
Input leakage current
--
--
1
A
V
IN
=.1V to V
CC
D7
I
LO
Output leakage current
--
--
1
A
V
OUT
=.1V to V
CC
D8
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
--
--
10
pF
V
CC
= 5.0V (Note)
T
A
= 25C, F
CLK
= 1 MHz
D9
I
CC
write
Operating current
--
0.1
3
mA
V
CC
= 5.5V, SCL = 400 kHz
D10
I
CC
read
--
0.05
1
mA
--
D11
I
CCS
Standby current
--
--
0.01
--
1
5
Industrial
Automotive
SDA = SCL = V
CC
WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
2003 Microchip Technology Inc.
DS21711C-page 3
24AA01/24LC01B
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
V
CC
= +1.8V to +5.5V
Industrial (I):
T
A
= -40C to +85C
Automotive (E): T
A
= -40C to +125C
Param.
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
1
F
CLK
Clock frequency
--
--
--
--
400
100
kHz
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
2
T
HIGH
Clock high time
600
4000
--
--
--
--
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
3
T
LOW
Clock low time
1300
4700
--
--
--
--
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
4
T
R
SDA and SCL rise time
(Note 1)
--
--
--
--
300
1000
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
5
T
F
SDA and SCL fall time
--
--
--
300
ns
(Note 1)
6
T
HD
:
STA
Start condition hold time
600
4000
--
--
--
--
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
7
T
SU
:
STA
Start condition setup
time
600
4700
--
--
--
--
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
8
T
HD
:
DAT
Data input hold time
0
--
--
--
ns
(Note 2)
9
T
SU
:
DAT
Data input setup time
100
250
--
--
--
--
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
10
T
SU
:
STO
Stop condition setup
time
600
4000
--
--
--
--
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
11
T
AA
Output valid from clock
(Note 2)
--
--
--
--
900
3500
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
12
T
BUF
Bus free-time: Time the
bus must be free before
a new transmission can
start
1300
4700
--
--
--
--
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
13
T
OF
Output fall time from V
IH
minimum to V
IL
maximum
20+0.1C
B
--
--
--
250
250
ns
2.5V
V
CC
5.5V
1.8V
V
CC
<
2.5V (24AA01)
14
T
SP
Input filter spike
suppression
(SDA and SCL pins)
--
--
50
ns
(Notes 1 and 3)
15
T
WC
Write cycle time
(byte or page)
--
--
5
ms
--
16
--
Endurance
1M
--
--
cycles
25C, (Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a
T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total EnduranceTM Model which can be obtained from Microchip's web site:
www.microchip.com.
24AA01/24LC01B
DS21711C-page 4
2003 Microchip Technology Inc.
FIGURE 1-1:
BUS TIMING DATA
FIGURE 1-2:
BUS TIMING START/STOP
7
5
2
4
8
9
10
12
11
14
6
SCL
SDA
IN
SDA
OUT
3
7
6
D4
10
Start
Stop
SCL
SDA
2003 Microchip Technology Inc.
DS21711C-page 5
24AA01/24LC01B
2.0
FUNCTIONAL DESCRIPTION
The 24XX01 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while defining a
device receiving data as a receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX01 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (although only the last sixteen
will be stored when doing a write operation). When an
overwrite does occur, it will replace data in a first-in
first-out (FIFO) fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX01) will leave the data line
high to enable the master to generate the Stop
condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24XX01 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
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