1996 Microchip Technology Inc.
Preliminary
DS21162B-page 1
FEATURES
Single supply with operation down to 1.8V
- Maximum write current 3 mA at 6.0V
- Standby current 1
A max at 1.8V
2-wire serial interface bus, I
2
C
TM
compatible
100 kHz (1.8V) and 400 kHz (5V) compatibility
Self-timed ERASE and WRITE cycles
Power on/off data protection circuitry
Hardware write protect
1,000,000 Erase/Write cycles guaranteed
32 byte page or byte write modes available
Schmitt trigger inputs for noise suppression
Output slope control to eliminate ground bounce
2 ms typical write cycle time, byte or page
Up to eight devices may be connected to the
same bus for up to 256K bits total memory
Electrostatic discharge protection > 4000V
Data retention > 200 years
8-pin PDIP and SOIC packages
Temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24AA32A is a 4K x 8
(32K bit) Serial Electrically Erasable PROM capable of
operation across a broad voltage range (1.8V to 6.0V).
It has been developed for advanced, low power applica-
tions such as personal communications or data acqui-
sition. The 24AA32A also has a page-write capability of
up to 32 bytes of data. The 24AA32A is capable of both
random and sequential reads up to the 32K boundary.
Functional address lines allow up to eight 24AA32A
devices on the same bus, for up to 256K bits address
space. Advanced CMOS technology and broad voltage
range make this device ideal for low-power/low-voltage,
nonvolatile code and data applications. The 24AA32A
is available in the standard 8-pin plastic DIP and both
150 mil and 200 mil SOIC packages.
- Commercial (C):
0
C to +70
C
PACKAGE TYPE
BLOCK DIAGRAM
24AA32A
24AA32A
1
2
3
4
8
7
6
5
A0
A1
A2
Vss
Vcc
WP
SCL
SDA
A0
A1
A2
Vss
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
A0..A2
SDA
SCL
V
CC
V
SS
WP
I/O
24AA32A
32K 1.8V I
2
C
TM
Serial EEPROM
I
2
C is a trademark of Philips Corporation.
This document was created with FrameMaker 4 0 4
24AA32A
DS21162B-page 2
Preliminary
1996 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature ..................................... -65C to +150C
Ambient temp. with power applied ................ -65C to +125C
Soldering temperature of leads (10 seconds) ............. +300C
ESD protection on all pins
..................................................
4 kV
*Notice:
Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
Name
Function
A0..A2
User Configurable Chip Selects
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
WP
Write Protect Input
V
CC
+1.8V to 6.0V Power Supply
TABLE 1-2:
DC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING START/STOP
Vcc = +1.8V to 6.0V
Commercial (C) Tamb = 0
C to +70
C
Parameter
Symbol
Min
Typ
Max
Units
Conditions
A0, A1, A2, SCL , SDA and WP
pins:
High level input voltage
V
IH
.7 V
CC
--
V
Low level input voltage
V
IL
--
.3 Vcc
V
Hysteresis of Schmitt Trigger
inputs
V
HYS
.05
V
CC
--
V
(Note)
Low level output voltage
V
OL
--
.40
V
I
OL
= 3.0 mA
Input leakage current
I
LI
-10
10
A
V
IN
= .1V to V
CC
Output leakage current
I
LO
-10
10
A
V
OUT
= .1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
,C
OUT
--
10
pF
V
CC
= 5.0V (Note)
Tamb = 25C, F
c
= 1 MHz
Operating current
I
CC
Write
--
3
mA
V
CC
= 6.0V
I
CC
Read
--
0.5
mA
V
CC
= 6.0V, SCL = 400kHz
Standby current
I
CCS
--
1
5
A SCL = SDA = V
CC
= 5.5V
I
CCS
1
A
V
CC
= 1.8V (Note)
Note:
This parameter is periodically sampled and not 100% tested.
SCL
SDA
T
SU
:
STA
T
HD
:
STA
T
SU
:
STO
V
HYS
START
STOP
1996 Microchip Technology Inc.
Preliminary
DS21162B-page 3
24AA32A
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
Vcc = 1.8-6.0V
STD. MODE
Vcc = 4.5-6.0V
FAST MODE
Units
Remarks
Min
Max
Min
Max
Clock frequency
F
CLK
--
100
--
400
kHz
Clock high time
T
HIGH
4000
--
600
--
ns
Clock low time
T
LOW
4700
--
1300
--
ns
SDA and SCL rise time
T
R
--
1000
--
300
ns
(Note 1)
SDA and SCL fall time
T
F
--
300
--
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
4000
--
600
--
ns
After this period the first
clock pulse is generated
START condition setup
time
T
SU
:
STA
4700
--
600
--
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
--
0
--
ns
Data input setup time
T
SU
:
DAT
250
--
100
--
ns
STOP condition setup time
T
SU
:
STO
4000
--
600
--
ns
Output valid from clock
T
AA
--
3500
--
900
ns
(Note 2)
Bus free time
T
BUF
4700
--
1300
--
ns
Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
min to V
IL
max
T
OF
--
250
20
+0.1C
B
250
ns
(Note 1), C
B
100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
T
SP
--
50
--
50
ns
(Note 3)
Write cycle time
T
WR
--
5
--
5
ms
Byte or Page Mode
Endurance
--
1M
--
1M
--
cycles
25
C, Vcc = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C
B
= Total capacitance of one bus line in pF.
2: As a trasmitter, the device must provide an internal minimum delay time to bridge the undefined region (mini-
mum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: This application is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
SCL
SDA
IN
SDA
OUT
T
HD
:
STA
T
SU
:
STA
T
F
T
HIGH
T
R
T
SU
:
STO
T
SU
:
DAT
T
HD
:
DAT
T
BUF
T
AA
T
HD
:
STA
T
AA
T
SP
T
LOW
24AA32A
DS21162B-page 4
Preliminary
1996 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24AA32A supports a Bi-directional two-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the Serial Clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24AA32A
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24AA32A) will leave the data line HIGH to
enable the master to generate the STOP condition.
Note:
The 24AA32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(
A
)
(B)
(D)
(D)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
(A)
1996 Microchip Technology Inc.
Preliminary
DS21162B-page 5
24AA32A
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code; for the 24AA32A this is
set as 1010 binary for read and write (R/W) operations.
The next three bits of the control byte are the device
select bits (A2, A1, A0). They are used by the master
device to select which of the eight devices are to be
accessed. These bits are in effect the three most signif-
icant bits of the word address. The last bit of the control
byte defines the operation to be performed. When set
to a one a read operation is selected, and when set to
a zero a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 3-3). Because only A11...A0 are used, the
upper four address bits must be zeros. The most signif-
icant bit of the most significant byte of the address is
transferred first.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
R/W
A
1
0
1
0
A2
A1
A0
READ/WRITE
START
SLAVE ADDRESS
Following the start condition, the 24AA32A monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24AA32A will select a read or
write operation.
Operation
Control
Code
Device Select
R/W
Read
1010
Device Address
1
Write
1010
Device Address
0
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
0
1
0
A
2
A
1
A
0 R/W
0
0
0
0
A
11
A
10
A
9
A
7
A
0
A
8
SLAVE
ADDRESS
DEVICE
SELECT
BUS
CONTROL BYTE
ADDRESS BYTE 1
ADDRESS BYTE 0
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