1996 Microchip Technology Inc.

DS21058G-page 1

FEATURES

· Voltage operating range: 4.5V to 5.5V

- Peak write current 3 mA at 5.5V
- Maximum read current 150

A at 5.5V

- Standby current 1

A typical

· Industry standard two-wire bus protocol, I

compatible

· 8 byte page, or byte modes available
· 2 ms typical write cycle time, byte or page
· 64-byte input cache for fast write loads
· Up to eight devices may be connected to the

same bus for up to 512K bits total memory

· Including 400 KHz compatibility
· Programmable block security options
· Programmable endurance options
· Schmitt trigger, filtered inputs for noise suppres-

sion

· Output slope control to eliminate ground bounce
· Self-timed ERASE and WRITE cycles
· Power on/off data protection circuitry
· Endurance:

- 10,000,000 E/W cycles guaranteed for High

Endurance Block

- 100,000 E/W cycles guaranteed for a Stan-

dard Endurance Block

· Electrostatic discharge protection > 4000V
· Data retention > 200 years
· 8-pin PDIP/SOIC packages
· Temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24C65 is a "smart" 8K x
8 Serial Electrically Erasable PROM (EEPROM). This
device has been developed for advanced, low power
applications such as personal communications, and
provides the systems designer with flexibility through
the use of many new user-programmable features. The
24C65 offers a relocatable 4K bit block of
ultra-high-endurance memory for data that changes
frequently. The remainder of the array, or 60K bits, is
rated at 1,000,000 ERASE/WRITE (E/W) cycles guar-
anteed. The 24C65 features an input cache for fast
write loads with a capacity of eight pages, or 64 bytes.
This device also features programmable security

- Commercial (C):

C to

+70

- Industrial (I)

-40

C to

+85

- Automotive (E):

-40

C to +125

options for E/W protection of critical data and/or code of
up to fifteen 4K blocks. Functional address lines allow
the connection of up to eight 24C65's on the same bus
for up to 512K bits contiguous EEPROM memory.
Advanced CMOS technology makes this device ideal
for low-power nonvolatile code and data applications.
The 24C65 is available in the standard 8-pin plastic DIP
and 8-pin surface mount SOIC package.

24C65

64K 5.0V I

Smart Serial

EEPROM

PACKAGE TYPES

BLOCK DIAGRAM

24C65

SCL

SDA

24C65

SCL

SDA

PDIP

SOIC

HV Generator

EEPROM ARRAY

Page Latches

Cache

YDEC

Vcc

Vss

I/O

Control

Logic

Memory

Control

Logic

SCL

SDA

A0..A2

XDEC

Sense AMP

R/W Control

I/O

C is a trademark of Philips Corporation.

Smart Serial is a trademark of Microchip Technology Inc.

This document was created with FrameMaker 4 0 4

24C65

DS21058G-page 2

1996 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

Storage temperature ..................................... -65°C to +150°C
Ambient temp. with power applied ................ -65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins

..................................................

4 kV

*Notice:

Stresses above those listed under "Maximum Ratings"

may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

A0..A2

User Configurable Chip Selects

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

+4.5V to 5.5V Power Supply

No Internal Connection

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

= +4.5V to +5.5V

Commercial (C): Tamb = 0°C to +70°C
Industrial (I):

Tamb = -40° to +85°C

Automotive (E): Tamb = -40

C to +125

Parameter

Symbol

Min

Max

Units

Conditions

A0, A1, A2, SCL and SDA pins:

High level input voltage
Low level input voltage
Hysteresis of Schmitt Trigger inputs
Low level output voltage

HYS

.7 V

.05 V

.3 Vcc

.40

V
V
V
V

Note 1
I

= 3.0 mA

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

= 5.0V (Note 1)

Tamb = 25°C, F

CLK

= 1 MHz

Operating current

Write

Read

--
--

150

= 5.5V, SCL = 400 kH

= 5.5V, SCL = 400 kHz

Standby current

CCS

= 5.5V, SCL = SDA =V

Note 1

Note 1: This parameter is periodically sampled and not 100% tested.

STA

HYS

STO

START

STOP

SCL

SDA

1996 Microchip Technology Inc.

DS21058G-page 3

24C65

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

STD. MODE

FAST MODE

Units

Remarks

Min

Max

Min

Max

Clock frequency

CLK

100

400

kHz

Clock high time

HIGH

4000

600

Clock low time

LOW

4700

1300

SDA and SCL rise time

1000

300

(Note 1)

SDA and SCL fall time

300

(Note 1)

START condition hold time

STA

4000

600

After this period the first
clock pulse is generated

START condition setup time

STA

4700

600

Only relevant for repeated
START condition

Data input hold time

DAT

Data input setup time

DAT

250

100

STOP condition setup time

STO

4000

600

Output valid from clock

3500

900

(Note 2)

Bus free time

BUF

4700

1300

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to

max

250

20 + 0.1

250

(Note 1), C

100 pF

Input filter spike suppression
(SDA and SCL pins)

(Note 3)

Write cycle time

ms/page (Note 4)

Endurance

High Endurance Block
Rest of Array

10M

--
--

10M

--
--

cycles

C, Vcc = 5.0V, Block

Mode (Note 5)

Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write

cache for total time.

5: This parameter is not tested but guaranteed by characterization. For endurance estimates on a specific

application, please consult the Total Endurance Mode which can be obtained on our BBS or website.

SCL

SDA
IN

SDA
OUT

STA

LOW

HIGH

STA

DAT

STO

BUF

24C65

DS21058G-page 4

1996 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The 24C65 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C65 works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

· Data transfer may be initiated only when the bus is

not busy.

· During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24C65) must leave the data line HIGH to
enable the master to generate the STOP condition.

Note:

The 24C65 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL

SDA

1996 Microchip Technology Inc.

DS21058G-page 5

24C65

3.6

Device Addressing

A control byte is the first byte received following the start
condition from the master device. The control byte con-
sists of a four bit control code, for the 24C65 this is set
as 1010 binary for read and write operations. The next
three bits of the control byte are the device select bits
(A2, A1, A0). They are used by the master device to
select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte (R/W)
defines the operation to be performed. When set to a one
a read operation is selected, when set to a zero a write
operation is selected. The next two bytes received define
the address of the first data byte (Figure 4-1). Because
only A12..A0 are used, the upper three address bits
must be zeros. The most significant bit of the most signif-
icant byte is transferred first. Following the start condi-
tion, the 24C65 monitors the SDA bus checking the
device type identifier being transmitted. Upon receiving a
1010 code and appropriate device select bits, the slave
device (24C65) outputs an acknowledge signal on the
SDA line. Depending upon the state of the R/W bit, the
24C65 will select a read or write operation.

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

Operation

Control

Code

Device Select

R/W

Read

1010

Device Address

Write

1010

Device Address

SLAVE ADDRESS

R/W

START

READ/WRITE

4.0

WRITE OPERATION

4.1

Byte Write

Following the start condition from the master, the control
code (four bits), the device select (three bits), and the
R/W bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed slave
receiver (24C65) that a byte with a word address will fol-
low after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the high-order byte of the word address
and will be written into the address pointer of the 24C65.
The next byte is the least significant address byte. After
receiving another acknowledge signal from the 24C65
the master device will transmit the data word to be writ-
ten into the addressed memory location. The 24C65
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24C65 will not generate acknowledge
signals (Figure 4-1).

4.2

Page Write

The write control byte, word address and the first data
byte are transmitted to the 24C65 in the same way as in
a byte write. But instead of generating a stop condition
the master transmits up to eight pages of eight data
bytes each (64 bytes total) which are temporarily stored
in the on-chip page cache of the 24C65. They will be
written from the cache into the EEPROM array after the
master has transmitted a stop condition. After the receipt
of each word, the six lower order address pointer bits are
internally incremented by one. The higher order seven
bits of the word address remain constant. If the master
should transmit more than eight bytes prior to generating
the stop condition (writing across a page boundary), the
address counter (lower three bits) will roll over and the
pointer will be incremented to point to the next line in the
cache. This can continue to occur up to eight times or
until the cache is full, at which time a stop condition
should be generated by the master. If a stop condition is
not received, the cache pointer will roll over to the first
line (byte 0) of the cache, and any further data received
will overwrite previously captured data. The stop condi-
tion can be sent at any time during the transfer. As with
the byte write operation, once the stop condition is
received an internal write cycle will begin. The 64 byte
cache will continue to capture data until a stop condition
occurs or the operation is aborted (Figure 4-2).

FIGURE 4-1:

BYTE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

This document was created with FrameMaker 4 0 4

1996 Microchip Technology Inc.

DS21058G-page 7

24C65

5.0

READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

5.1

Current Address Read

The 24C65 contains an address counter that maintains
the address of the last word accessed, internally incre-
mented by one. Therefore, if the previous access (either
a read or write operation) was to address n (n is any
legal address), the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24C65
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C65 discon-
tinues transmission (Figure 4-3).

5.2

Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C65 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master issues the con-
trol byte again but with the R/W bit set to a one. The
24C65 will then issue an acknowledge and transmit the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24C65 to discontinue transmission
(Figure 4-4).

5.3

Sequential Read

Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C65 transmits the first
data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24C65 to transmit the
next sequentially addressed 8 bit word (Figure 4-5).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.

To provide sequential reads the 24C65 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.

5.4

Contiguous Addressing Across
Multiple Devices

The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 512K
bits by adding up to eight 24C65's on the same bus. In
this case, software can use A0 of the control byte as
address bit A13, A1 as address bit A14, and A2 as
address bit A15.

5.5

Noise Protection

The SCL and SDA inputs have filter circuits which sup-
press noise spikes to assure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 KHz (Fast Mode) compatibility.

5.6

High Endurance Block

The location of the high-endurance block within the
memory map is programmed by setting the leading bit
7 (S/HE) of the configuration byte to 0. The upper bits
of the address loaded in this command will determine
which 4K block within the memory map will be set to
high endurance (Figure 8-1). This block will be capable
of 10,000,000 erase/write cycles.

5.7

Security Options

The 24C65 has a sophisticated mechanism for
write-protecting portions of the array. This write protect
function is programmable and allows the user to protect
0-15 contiguous 4K blocks. The user sets the security
option by sending to the device the starting block num-
ber for the protected region and the number of blocks to
be protected. If the security option is invoked with 0
blocks protected, then all portions of the array will be
unprotected. All parts will come from the factory in the
default configuration with the starting block number set
to 15 and the number of protected blocks set to zero.
THE SECURITY OPTION CAN BE SET ONLY ONCE.

To invoke the security option, a write command is sent
to the device with the leading bit (bit 7) of the first
address byte set to a 1 (Figure 8-1). Bits 1-4 of the first
address byte define the starting block number for the
protected region. For example, if the starting block
number is to be set to 5, the first address byte would be
1XX0101X. Bits 0, 5 and 6 of the first address byte are
disregarded by the device and can be either high or low.
The device will acknowledge after the first address
byte. A byte of don't care bits is then sent by the master,
with the device acknowledging afterwards. The third
byte sent to the device has bit 7 (S/HE) set high and bit
6 (R) set low. Bits 4 and 5 are don't cares and bits 0-3

Note:

The High Endurance Block cannot be
changed after the security option has been
set. If the H.E. block is not programmed by
the user, the default location is the highest
block of memory.

24C65

DS21058G-page 8

1996 Microchip Technology Inc.

define the number of blocks to be write protected. For
example, if three blocks are to be protected, the third
byte would be 10XX0011. After the third byte is sent to
the device, it will acknowledge and a STOP bit is then
sent by the master to complete the command.

During a normal write sequence, if an attempt is made
to write to a protected address, no data will be written
and the device will not report an error or abort the com-
mand. If a write command is attempted across a
secure boundary, unprotected addresses will be written
and protected addresses will not.

5.8

Security Configuration Read

The status of the secure portion of memory can be read
by using the same technique as programming this
option except the READ bit (bit 6) of the configuration
byte is set to a one. After the configuration byte is sent,
the device will acknowledge and then send two bytes of
data to the master just as in a normal read sequence.
The master must acknowledge the first byte and not
acknowledge the second, and then send a stop bit to
end the sequence. The upper four bits of both of these
bytes will always be read as '1's. The lower four bits of
the first byte contains the starting secure block. The
lower four bits of the second byte contains the number
of secure blocks. The default starting secure block is fif-
teen and the default number of secure blocks is zero
(Figure 8-1).

6.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 6-1 for flow diagram.

FIGURE 6-1:

ACKNOWLEDGE POLLING
FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

1996 Microchip Technology Inc.

DS21058G-page 9

24C65

7.0

PAGE CACHE AND ARRAY
MAPPING

The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer.
The cache allows the loading of up to 64 bytes of data
before the write cycle is actually begun, effectively pro-
viding a 64-byte burst write at the maximum bus rate.
Whenever a write command is initiated, the cache
starts loading and will continue to load until a stop bit is
received to start the internal write cycle. The total length
of the write cycle will depend on how many pages are
loaded into the cache before the stop bit is given. Max-
imum cycle time for each page is 5 ms. Even if a page
is only partially loaded, it will still require the same cycle
time as a full page. If more than 64 bytes of data are
loaded before the stop bit is given, the address pointer
will 'wrap around' to the beginning of cache page 0 and
existing bytes in the cache will be overwritten. The
device will not respond to any commands while the
write cycle is in progress.

7.1

Cache Write Starting at a Page
Boundary

If a write command begins at a page boundary
(address bits A2, A1 and A0 are zero), then all data
loaded into the cache will be written to the array in
sequential addresses. This includes writing across a 4K
block boundary. In the example shown below,
(Figure 8-2) a write command is initiated starting at
byte 0 of page 3 with a fully loaded cache (64 bytes).
The first byte in the cache is written to byte 0 of page 3
(of the array), with the remaining pages in the cache
written to sequential pages in the array. A write cycle is
executed after each page is written. Since the write
begins at page 3 and 8 pages are loaded into the
cache, the last 3 pages of the cache are written to the
next row in the array.

7.2

Cache Write Starting at a Non-Page
Boundary

When a write command is initiated that does not begin
at a page boundary (i.e., address bits A2, A1 and A0
are not all zero), it is important to note how the data is
loaded into the cache, and how the data in the cache is
written to the array. When a write command begins, the
first byte loaded into the cache is always loaded into
page 0. The byte within page 0 of the cache where the
load begins is determined by the three least significant
address bits (A2, A1, A0) that were sent as part of the
write command. If the write command does not start at
byte 0 of a page and the cache is fully loaded, then the
last byte(s) loaded into the cache will roll around to
page 0 of the cache and fill the remaining empty bytes.
If more than 64 bytes of data are loaded into the cache,
data already loaded will be overwritten. In the example
shown in Figure 8-3, a write command has been initi-
ated starting at byte 2 of page 3 in the array with a fully
loaded cache of 64 bytes. Since the cache started load-
ing at byte 2, the last two bytes loaded into the cache

will 'roll over' and be loaded into the first two bytes of
page 0 (of the cache). When the stop bit is sent, page
0 of the cache is written to page 3 of the array. The
remaining pages in the cache are then loaded sequen-
tially to the array. A write cycle is executed after each
page is written. If a partially loaded page in the cache
remains when the STOP bit is sent, only the bytes that
have been loaded will be written to the array.

7.3

Power Management

The design incorporates a power standby mode when
not in use and automatically powers off after the nor-
mal termination of any operation when a stop bit is
received and all internal functions are complete. This
includes any error conditions, i.e. not receiving an
acknowledge or stop condition per the two-wire bus
specification. The device also incorporates V

moni-

tor circuitry to prevent inadvertent writes (data corrup-
tion) during low-voltage conditions. The V

monitor

circuitry is powered off when the device is in standby
mode in order to further reduce power consumption.

8.0

PIN DESCRIPTIONS

8.1

A0, A1, A2 Chip Address Inputs

The A0..A2 inputs are used by the 24C65 for multiple
device operation and conform to the two-wire bus stan-
dard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
(Figure 3-2 and Figure 8-1).

8.2

SDA Serial Address/Data Input/Output

This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

for 100 KHz, 1K

for 400

KHz).

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

8.3

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

24C65

DS21058G-page 10

1996 Microchip Technology Inc.

FIGURE 8-1:

CONTROL SEQUENCE BIT ASSIGNMENTS

Control Byte

Address Byte 1

Address Byte 0

Slave

Address

Device

Select

Bits

Configuration Byte

Block

Count

S/HE

X X

Starting Block

Number

X X

Number of

Blocks to

Protect

ACK

Data from Device

Acknowledge

from

Master

Data from Device

Acknowledges from Device

X X

Acknowledges from Device

X X

High Endurance

Block Number

r
t

X X

o
p

ACK

Data from Device

Acknowledges from Device

X X

0 0

Acknowledges from Device

Starting Block

Number

Number of

Blocks to

Protect

S/HE

Security Read

Security Write

High Endurance Block Read

High Endurance Block Write

High Endurance

Block Number

1996 Microchip Technology Inc.

DS21058G-page 11

24C65

FIGURE 8-2:

CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY

FIGURE 8-3:

CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY

1 Write command initiated at byte 0 of page 3 in the array;

First data byte is loaded into the cache byte 0.

2 64 bytes of data are loaded into cache.

3 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.

4 Remaining pages in cache are written

to sequential pages in array.

cache
byte 0

cache
byte 1

· · ·

cache
byte 7

cache page 1

bytes 8-15

· · ·

page 0

cache page 2

bytes 16-23

cache page 7

bytes 56-63

page 1 page 2

· · ·

byte 7

· · ·

page 4

· · ·

page 7

page 3

cache page 0

Last page in cache written to page 2 in next row.

array row n

array row n + 1

page 0 page 1 page 2

byte 0

byte 1

page 4

page 7

1 Write command initiated; 64 bytes of data

loaded into cache starting at byte 2 of page 0.

2 Last 2 bytes loaded 'roll over'

to beginning.

Last 2 bytes
loaded into
page 0 of cache.

4 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.

cache
byte 1

cache
byte 2

· · ·

cache
byte 7

cache page 1

bytes 8-15

· · ·

page 0

cache page 2

bytes 16-23

cache page 7

bytes 56-63

page 1 page 2

· · ·

page 4

· · ·

page 7

page 3

Remaining bytes in cache are
written sequentially to array.

array

row n

array

row

n + 1

cache
byte 0

Last 3 pages in cache written to next row in array.

page 1 page 2

byte 0

byte 2

byte 1

page 4

page 7

byte 7

byte 3

byte 4

page 0

DS21058G-page 16

1996 Microchip Technology Inc.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

ORLDWIDE

ALES

& S

ERVICE

ASIA/PACIFIC

China

Microchip Technology
Unit 406 of Shanghai Golden Bridge Bldg.
2077 Yan'an Road West, Hongiao District
Shanghai, Peoples Republic of China
Tel: 86 21 6275 5700
Fax: 011 86 21 6275 5060

Hong Kong

Microchip Technology
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431

India

Microchip Technology
No. 6, Legacy, Convent Road
Bangalore 560 025 India
Tel: 91 80 526 3148 Fax: 91 80 559 9840

Korea

Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934

Singapore

Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850

Taiwan, R.O.C

Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 1628 850303 Fax: 44 1628 850178

France

Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: 39 39 6899939 Fax: 39 39 689 9883

JAPAN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: 81 45 471 6166 Fax: 81 45 471 6122

9/3/96

AMERICAS

Corporate Office

Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com

Atlanta

Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307

Boston

Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508 480-9990 Fax: 508 480-8575

Chicago

Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075

Dallas

Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972 991-7177 Fax: 972 991-8588

Dayton

Microchip Technology Inc.
Suite 150
Two Prestige Place
Miamisburg, OH 45342
Tel: 513 291-1654 Fax: 513 291-9175

Los Angeles

Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 714 263-1888 Fax: 714 263-1338

New York

Microchip Technmgy Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335

San Jose

Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955

Toronto

Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279

Fax: 905 405-6253

1996, Microchip Technology Incorporated, USA. 9/96

Printed on recycled paper.

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