1996 Microchip Technology Inc.
DS21073E-page 1
FEATURES
Voltage operating range: 2.5V to 6.0V
- Peak write current 3 mA at 6.0V
- Maximum read current 150
A at 6.0V
- Standby current 1
A typical
Industry standard two wire bus protocol I
2
C
TM
compatible
8 byte page, or byte modes available
2 ms typical write cycle time, byte or page
64-byte input cache for fast write loads
Up to 8 devices may be connected to the same
bus for up to 512K bits total memory
Including 100 kHz (2.5V) and 400 kHz (5.0V)
compatibility
Programmable block security options
Programmable endurance options
Schmitt trigger, filtered inputs for noise suppres-
sion
Output slope control to eliminate ground bounce
Self-timed ERASE and WRITE cycles
Power on/off data protection circuitry
Endurance:
- 10,000,000 E/W cycles guaranteed for a High
Endurance Block
- 1,000,000 E/W cycles guaranteed for a Stan-
dard Endurance Block
Electrostatic discharge protection > 4000V
Data retention > 200 years
8-pin PDIP/SOIC packages
Temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24LC65 is a "smart" 8K
x 8 Serial Electrically Erasable PROM. This device
has been developed for advanced, low power applica-
tions such as personal communications, and provides
the systems designer with flexibility through the use of
many new user-programmable features. The 24LC65
offers a relocatable 4K bit block of ultra-high-endurance
memory for data that changes frequently. The remain-
der of the array, or 60K bits, is rated at 1,000,000
ERASE/WRITE (E/W) cycles guaranteed. The 24LC65
features an input cache for fast write loads with a
capacity of eight pages, or 64 bytes. This device also
features programmable security options for E/W protec-
tion of critical data and/or code of up to fifteen 4K
- Commercial (C):
0
C to +70
C
- Industrial (I)
-40
C to +85
C
blocks. Functional address lines allow the connection of
up to eight 24LC65's on the same bus for up to 512K
bits contiguous EEPROM memory. Advanced CMOS
technology makes this device ideal for low-power non-
volatile code and data applications. The 24LC65 is
available in the standard 8-pin plastic DIP and 8-pin
surface mount SOIC package.
24LC65
64K 2.5V I
2
C
TM
Smart Serial
TM
EEPROM
PACKAGE TYPES
BLOCK DIAGRAM
24LC65
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
NC
SCL
SDA
24LC65
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
NC
SCL
SDA
PDIP
SOIC
HV Generator
EEPROM ARRAY
Page Latches
Cache
YDEC
Vcc
Vss
I/O
Control
Logic
Memory
Control
Logic
SCL
SDA
A0..A2
XDEC
Sense AMP
R/W Control
I/O
I
2
C is a trademark of Philips Corporation.
Smart Serial is a trademark of Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
24LC65
DS21073E-page 2
1996 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature ...................................... -65C to+150C
Ambient temp. with power applied ................ -65C to +125C
Soldering temperature of leads (10 seconds) ............. +300C
ESD protection on all pins
..................................................
4 kV
*Notice:
Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
Name
Function
A0..A2
User Configurable Chip Selects
Vss
Ground
SDA
Serial Address/Data/I/O
SCL
Serial Clock
V
CC
+2.5V to 6.0V Power Supply
NC
No Internal Connection
TABLE 1-2:
DC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING START/STOP
V
CC
= +2.5V to +6.0V
Commercial (C):
Tamb
= 0
C to +70
C
Industrial
(I):
Tamb = -40
C to +85
C
Parameter
Sym
Min
Max
Units
Conditions
A0, A1, A2, SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of Schmitt Trigger inputs
Low level output voltage
V
IH
V
IL
V
HYS
V
OL
.7 Vcc
--
.05 V
CC
--
--
.3 V
CC
--
.40
V
V
V
V
(Note 1)
I
OL
= 3.0 mA
Input leakage current
I
LI
-10
10
A
V
IN
= .1V to V
CC
Output leakage current
I
LO
-10
10
A
V
OUT
= .1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
--
10
pF
V
CC
= 5.0V (Note 1)
Tamb = 25C, Fclk = 1 MHz
Operating current
I
CC
W
RITE
I
CC
Read
--
--
3
150
mA
A
V
CC
= 6.0V, SCL = 400 kHz
V
CC
= 6.0V, SCL = 400 kHz
Standby current
I
CCS
--
5
A
V
CC
= 5.0V, SCL = SDA = V
CC
(Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
1996 Microchip Technology Inc.
DS21073E-page 3
24LC65
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
Vcc = 2.5V-6.0V
STD. MODE
V
CC
= 4.5-6.0V
FAST MODE
Units
Remarks
Min
Max
Min
Max
Clock frequency
F
CLK
--
100
--
400
kHz
Clock high time
T
HIGH
4000
--
600
--
ns
Clock low time
T
LOW
4700
--
1300
--
ns
SDA and SCL rise time
T
R
--
1000
--
300
ns
(Note 1)
SDA and SCL fall time
T
F
--
300
--
300
ns
(Note 1)
START condition setup time
T
HD
:
STA
4000
--
600
--
ns
After this period the first
clock pulse is generated
START condition setup time
T
SU
:
STA
4700
--
600
--
ns
Only relevant for
repeated START condi-
tion
Data input hold time
T
HD
:
DAT
0
--
0
--
ns
Data input setup time
T
SU
:
DAT
250
--
100
--
ns
STOP condition setup time
T
SU
:
STO
4000
--
600
--
ns
Output valid from clock
T
AA
--
3500
--
900
ns
(Note 2)
Bus free time
T
BUF
4700
--
1300
--
ns
Time the bus must be
free before a new trans-
mission can start
Output fall time from V
IH
min to
V
IL
max
T
OF
--
250
20 + 0.1
C
B
250
ns
(Note 1), C
B
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
--
50
--
50
ns
Note 3
Write cycle time
T
WR
--
5
--
5
ms/page (Note 4)
Endurance
High Endurance Block
Rest of Array
10M
1M
--
--
10M
1M
--
--
cycles
25
C, Vcc = 5.0V, Block
Mode (Note 5)
Note 1: Not 100 percent tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
24LC65
DS21073E-page 4
1996 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24LC65 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LC65 works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24LC65) must leave the data line HIGH to
enable the master to generate the STOP condition.
Note:
The 24LC65 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
SDA
1996 Microchip Technology Inc.
DS21073E-page 5
24LC65
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code, for the 24LC65 this is
set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte defines
the operation to be performed. When set to a one a
read operation is selected, when set to a zero a write
operation is selected. The next two bytes received
define the address of the first data byte (Figure 4-1).
Because only A12..A0 are used, the upper three
address bits must be zeros. The most significant bit of
the most significant byte is transferred first. Following
the start condition, the 24LC65 monitors the SDA bus
checking the device type identifier being transmitted.
Upon receiving a 1010 code and appropriate device
select bits, the slave device (24LC65) outputs an
acknowledge signal on the SDA line. Depending upon
the state of the R/W bit, the 24LC65 will select a read
or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
Operation Control Code
Device Select
R/W
Read
1010
Device Address
1
Write
1010
Device Address
0
SLAVE ADDRESS
1
0
1
0
A2
A1
A0
R/W
A
START
READ/WRITE
4.0
WRITE OPERATION
4.1
Byte Write
Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low is placed onto the bus
by the master transmitter. This indicates to the
addressed slave receiver (24LC65) that a byte with a
word address will follow after it has generated an
acknowledge bit during the ninth clock cycle. Therefore
the next byte transmitted by the master is the high-order
byte of the word address and will be written into the
address pointer of the 24LC65. The next byte is the
least significant address byte. After receiving another
acknowledge signal from the 24LC65 the master device
will transmit the data word to be written into the
addressed memory location. The 24LC65 acknowl-
edges again and the master generates a stop condi-
tion. This initiates the internal write cycle, and during
this time the 24LC65 will not generate acknowledge
signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC65 in the same way as
in a byte write. But instead of generating a stop condi-
tion the master transmits up to eight pages of eight data
bytes each (64 bytes total) which are temporarily stored
in the on-chip page cache of the 24LC65. They will be
written from the cache into the EEPROM array after the
master has transmitted a stop condition. After the
receipt of each word, the six lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remain con-
stant. If the master should transmit more than eight
bytes prior to generating the stop condition (writing
across a page boundary), the address counter (lower
three bits) will roll over and the pointer will be incre-
mented to point to the next line in the cache. This can
continue to occur up to eight times or until the cache is
full, at which time a stop condition should be generated
by the master. If a stop condition is not received, the
cache pointer will roll over to the first line (byte 0) of the
cache, and any further data received will overwrite pre-
viously captured data. The stop condition can be sent
at any time during the transfer. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin. The 64 byte cache will con-
tinue to capture data until a stop condition occurs or the
operation is aborted (Figure 4-2).
FIGURE 4-1:
BYTE WRITE
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
0 0 0
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