1996 Microchip Technology Inc.
DS11125G-page 1
FEATURES
Fast Read Access Time--150 ns
CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100
A Standby
Fast Byte Write Time--200
s or 1 ms
Data Retention >200 years
High Endurance - Minimum 10
4
Erase/Write Cycles
Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
Data polling
Chip Clear Operation
Enhanced Data Protection
- V
CC
Detector
- Pulse Filter
- Write Inhibit
Electronic Signature for Device Identification
5-Volt-Only Operation
Organized 2Kx8 JEDEC Standard Pinout
24-pin Dual-In-Line Package
32-pin PLCC Package
28-pin Thin Small Outline Package (TSOP)
8x20mm
28-pin Very Small Outline Package (VSOP)
8x13.4mm
Available for Extended Temperature Ranges:
- Commercial: 0C to +70C
- Industrial: -40C to +85C
DESCRIPTION
The Microchip Technology Inc. 28C16A is a CMOS 16K
non-volatile electrically Erasable PROM. The 28C16A
is accessed like a static RAM for the read or write
cycles without the need of external components. Dur-
ing a "byte write", the address and data are latched
internally, freeing the microprocessor address and data
bus for other operations. Following the initiation of
write cycle, the device will go to a busy state and auto-
matically clear and write the latched data using an
internal control timer. To determine when a write cycle
is complete, the 28C16A uses Data polling. Data poll-
ing allows the user to read the location last written to
when the write operation is complete. CMOS design
and processing enables this part to be used in systems
where reduced power consumption and reliability are
required. A complete family of packages is offered to
provide the utmost flexibility in applications.
PACKAGE TYPES
BLOCK DIAGRAM
A10
CE
21
20
19
V
SS
I/O2
14
13
12
OE
NC
A9
A8
22
23
24
NC
NC
A7
1
2
3
4
5
25
26
27
28
6
7
NC
WE
V
CC
A6
A5
A4
A3
I/O7
I/O6
I/O5
I/O4
I/O3
I/O1
I/O0
A0
A1
A2
18
17
16
15
11
10
9
8
OE
NC
A9
A8
NC
WE
Vcc
NC
NC
A7
A6
A5
A4
A3
A10
CE
I/07
I/06
I/05
I/04
I/03
Vss
I/02
I/01
I/00
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Pin 1 indicator on PLCC on top of package
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
NC
NC
OE
A10
CE
I/O7
I/O6
A7
NC
NC
NU
Vcc
WE
NC
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
14
15
16
17
18
19
20
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
Vcc
A8
A9
WE
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
SS
DIP
PLCC
TSOP
VSOP
I/O0
I/O7
Input/Output
Buffers
Chip Enable/
Output Enable
Control Logic
CE
OE
Data Protection
Circuitry
A10
Y Gating
16K bit
Cell Matrix
X
Decoder
Y
Decoder
A0
Data
Poll
Auto Erase/Write
Timing
V
CC
V
SS
WE
L
a
t
c
h
e
s
Program Voltage
Generation
28C16A
16K (2K x 8) CMOS EEPROM
This document was created with FrameMaker 4 0 4
28C16A
DS11125G-page 2
1996 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
1.1
MAXIMUM RATINGS*
V
CC
and input voltages w.r.t. V
SS
....... -0.6V to + 6.25V
Voltage on OE w.r.t. V
SS
..................... -0.6V to +13.5V
Voltage on A9 w.r.t. V
SS
...................... -0.6V to +13.5V
Output Voltage w.r.t. V
SS
................ -0.6V to V
CC
+0.6V
Storage temperature .......................... -65C to +125C
Ambient temp. with power applied ....... -50C to +95C
*Notice:
Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
Name
Function
A0 - A10
Address Inputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
V
CC
+5V Power Supply
V
SS
Ground
NC
No Connect; No Internal Connection
NU
Not Used; No External Connection is
Allowed
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTICS
V
CC
= +5V
10%
Commercial (C): Tamb = 0C
to +70C
Industrial (I): Tamb = -40C
to +85C
Parameter
Status
Symbol
Min
Max
Units
Conditions
Input Voltages
Logic `1'
Logic `0;
V
IH
V
IL
2.0
-0.1
V
CC
+1
0.8
V
V
Input Leakage
--
I
LI
-10
10
A
V
IN
= -0.1V to V
CC
+1
Input Capacitance
--
C
IN
--
10
pF
V
IN
= 0V; Tamb = 25C;
f = 1 MHz
Output Voltages
Logic `1'
Logic `0'
V
OH
V
OL
2.4
0.45
V
V
I
OH
= -400
A
I
OL
= 2.1 mA
Output Leakage
--
I
LO
-10
10
A
V
OUT
= -0.1V to V
CC
+0.1V
Output Capacitance
--
C
OUT
--
12
pF
V
IN
= 0V; Tamb = 25C;
f = 1 MHz
Power Supply Current,
Active
TTL input
I
CC
--
30
mA
f = 5 MHz (Note 1)
V
CC
= 5.5V;
Power Supply Current,
Standby
TTL input
TTL input
CMOS input
I
CC
(
S
)
TTL
I
CC
(
S
)
TTL
I
CC
(
S
)
CMOS
--
2
3
100
mA
mA
A
CE = V
IH
(0C to +70C)
CE = V
IH
(-40C to +85C)
CE = V
CC
-0.3 to V
CC
+1
Note 1: AC power supply current above 5 MHz; 1 mA/MHz.
1996 Microchip Technology Inc.
DS11125G-page 3
28C16A
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
FIGURE 1-1:
READ WAVEFORMS
AC Testing Waveform:
V
IH
= 2.4V; V
IL
= 0.45V; V
OH
= 2.0V; Vol = 0.8V
Output Load:
1 TTL Load + 100pF
Input Rise and Fall Times: 20 ns
Ambient Temperature:
Commercial (C): Tamb =
0C to +700C
Industrial (I):
Tamb =
-40C to +85C
Parameter
Sym
28C16A-15
28C16A-20
28C16A-25
Units
Conditions
Min
Max
Min
Max
Min
Max
Address to Output Delay
t
ACC
--
150
--
200
--
250
ns
OE = CE = V
IL
CE to Output Delay
t
CE
--
150
--
200
--
250
ns
OE = V
IL
OE to Output Delay
t
OE
--
70
--
80
--
100
ns
CE = V
IL
CE or OE High to Output Float
t
OFF
0
50
0
55
0
70
ns
Output Hold from CE or OE,
whichever occurs first
t
OH
0
--
0
--
0
--
ns
Endurance
--
1M
--
1M
--
1M
--
cycles 25
C, Vcc =
5.0V, Block
Mode (Note)
Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
Address
CE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
OE
Data
WE
V
OH
V
OL
V
IH
V
IL
Address Valid
High Z
Valid Output
t
ACC
(1) t
OFF
is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
(3) This parameter is sampled and is not 100% tested
High Z
t
OH
t
OFF(1,3)
Notes:
t
OE(2)
t
CE(2)
28C16A
DS11125G-page 4
1996 Microchip Technology Inc.
TABLE 1-4:
BYTE WRITE AC CHARACTERISTICS
FIGURE 1-2:
PROGRAMMING WAVEFORMS
AC Testing Waveform:
V
IH
= 2.4V and V
IL
= 0.45V; V
OH
= 2.0V; V
OL
= 0.8V
Output Load:
1 TTL Load + 100 pF
Input Rise/Fall Times:
20 ns
Ambient Temperature:
Commercial (C):
Tamb
=
0C to +70C
Industrial (I):
Tamb
=
-40C to +85C
Parameter
Symbol
Min
Max
Units
Remarks
Address Set-Up Time
t
AS
10
--
ns
Address Hold Time
t
AH
50
--
ns
Data Set-Up Time
t
DS
50
--
ns
Data Hold Time
t
DH
10
--
ns
Write Pulse Width
t
WPL
100
--
ns
Note 1
Write Pulse High Time
t
WPH
50
--
ns
OE Hold Time
t
OEH
10
--
ns
OE Set-Up Time
t
OES
10
--
ns
Data Valid Time
t
DV
--
1000
ns
Note 2
Write Cycle Time (28C16A)
t
WC
--
1
ms
0.5 ms typical
Write Cycle Time (28C16AF)
t
WC
--
200
s
100
s typical
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the pos-
itive edge of CE or WE, whichever occurs first.
2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until t
DH
after the positive edge of WE or CE, whichever occurs first.
t
AS
t
AH
t
WPL
t
DS
t
DH
t
OES
t
OEH
t
DV
Address
CE, WE
Data In
OE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
1996 Microchip Technology Inc.
DS11125G-page 5
28C16A
FIGURE 1-3:
DATA POLLING WAVEFORMS
FIGURE 1-4:
CHIP CLEAR WAVEFORMS
TABLE 1-5:
SUPPLEMENTARY CONTROL
Mode
CE
OE
WE
A9
V
CC
I/O
I
Chip Clear
V
IL
V
H
V
IL
X
V
CC
Extra Row Read
V
IL
V
IL
V
IH
A9 = V
H
V
CC
Data Out
Extra Row Write
*
V
IH
*
A9 = V
H
V
CC
Data In
Note 1: V
H
= 12.0V
0.5V * Pulsed per programming waveforms.
Address Valid
Last Written
Address Valid
t
ACC
t
CE
t
WPL
t
WPH
t
DV
t
WC
t
OE
True Data Out
Data In
Valid
V
IH
V
IL
Data
OE
WE
CE
Address
I/O7 Out
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
H
V
IH
CE
OE
WE
t
S
t
H
t
W
t
S
= = 1
s
t
H
= 10ms
t
W
V
IH
V
IL
V
IH
V
IL
= 12.0V
0.5V
V
H
28C16A
DS11125G-page 6
1996 Microchip Technology Inc.
2.0
DEVICE OPERATION
The Microchip Technology Inc. 28C16A has four basic
modes of operation--read, standby, write inhibit, and
byte write--as outlined in the following table.
2.1
Read Mode
The 28C16A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to
the output pins independent of device selection.
Assuming that addresses are stable, address access
time (t
ACC)
is equal to the delay from CE to output (t
CE
).
Data is available at the output t
OE
after the falling edge
of OE, assuming that CE has been low and addresses
have been stable for at least t
ACC
-t
OE
.
2.2
Standby Mode
The 28C16A is placed in the standby mode by applying
a high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state, inde-
pendent of the OE input.
2.3
Data Protection
In order to ensure data integrity, especially during criti-
cal power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal V
CC
detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation
when V
CC
is less than the V
CC
detect circuit trip.
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10 ns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (V
CC
).
Operation
Mode
CE
OE
WE
I/O
Read
L
L
H
D
OUT
Standby
H
X
X
High Z
Write Inhibit
H
X
X
High Z
Write Inhibit
X
L
X
High Z
Write Inhibit
X
X
H
High Z
Byte Write
L
H
L
D
IN
Byte Clear
Automatic Before Each "Write"
X = Any TTL level.
2.4
Write Mode
The 28C16A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and ini-
tiated by a low going pulse on the WE pin. On the fall-
ing edge of WE, the address information is latched. On
rising edge, the data and the control pins (CE and OE)
are latched.
2.5
Data Polling
The 28C16A features Data polling to signal the com-
pletion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the
data complement of I/O7 (I/O0 to I/O6 are indetermin-
able). After completion of the write cycle, true data is
available. Data polling allows a simple read/compare
operation to determine the status of the chip eliminat-
ing the need for external hardware.
2.6
Electronic Signature for Device
Identification
An extra row of 32 bytes of EEPROM memory is avail-
able to the user for device identification. By raising A9
to 12V
0.5V and using address locations 7EO to 7FF,
the additional bytes can be written to or read from in the
same manner as the regular memory array.
2.7
Chip Clear
All data may be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE
low. This procedure clears all data, except for the extra
row.
28C16A
1996 Microchip Technology Inc.
DS11125G-page 7
28C16A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Package:
L = Plastic Leaded Chip Carrier (PLCC)
P = Plastic DIP (600 mil)
TS = Thin Small Outline Package (TSOP) 8x20mm
VS = Very Small Outline Package (VSOP) 8x13.4mm
Temperature
Blank = 0
C to +70
C
Range:
I
= -40
C to +85
C
Access Time:
15
150 ns
20
200 ns
25
250 ns
Shipping:
Blank
Tube
T
Tape and Reel "L" only
Option:
Blank = twc = 1ms
F = twc = 200
s
Device:
28C16A
2K x 8 CMOS EEPROM
28C16A
F
T
15
I
/P
DS11125G-page 8
1996 Microchip Technology Inc.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
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