1996 Microchip Technology Inc.
DS11020F-page 1
27LV256
FEATURES
Wide voltage range 3.0V to 5.5V
High speed performance
- 200 ns access time available at 3.0V
CMOS Technology for low power consumption
- 8 mA Active current at 3.0V
- 20 mA Active current at 5.5V
- 100
A Standby current
Factory programming available
Auto-insertion-compatible plastic packages
Auto ID aids automated programming
Separate chip enable and output enable controls
High speed "Express" programming algorithm
Organized 32K x 8: JEDEC standard pinouts
- 28-pin Dual-in-line package
- 32-pin PLCC package
- 28-pin SOIC package
- 28-pin VSOP package
- Tape and reel
Data Retention > 200 years
Available for the following temperature ranges:
- Commercial:
0C to +70C
- Industrial:
-40C to +85C
DESCRIPTION
The Microchip Technology Inc. 27LV256 is a low volt-
age (3.0 volt) CMOS EPROM designed for battery
powered applications. The device is organized as a
32K x 8 (32K-Byte) non-volatile memory product. The
27LV256 consumes only 8 mA maximum of active cur-
rent during a 3.0 volt read operation therefore improv-
ing battery performance. This device is designed for
very low voltage applications where conventional 5.0
volt only EPROMS can not be used. Accessing individ-
ual bytes from an address transition or from power-up
(chip enable pin going low) is accomplished in less than
200 ns at 3.0V. This device allows systems designers
the ability to use low voltage non-volatile memory with
today's' low voltage microprocessors and peripherals
in battery powered applications.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount appli-
cations, PLCC, VSOP or SOIC packaging is available.
Tape and reel packaging is also available for PLCC or
SOIC packages.
PACKAGE TYPES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
V
V
A14
A13
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
PP
SS
CC
A6
A5
A4
A3
A2
A1
A0
NC
O0
A8
A9
A11
NC
OE
A10
CE
O7
O6
A7
A12
V
NU
Vcc
A14
A13
O1
O2
V
NU
O3
O4
O5
PP
SS
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
4
3
2
1
32
31
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
PP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
V
SS
V
CC
A14
A13
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
A10
CE
21
20
19
V
SS
O2
14
13
12
OE
A11
A9
A8
22
23
24
V
PP
A12
A7
1
2
3
4
5
25
26
27
28
6
7
A13
A14
V
CC
A6
A5
A4
A3
O7
O6
O5
O4
O3
O1
O0
A0
A1
A2
18
17
16
15
11
10
9
8
PDIP
PLCC
SOIC
VSOP
27L
V256
27L
V256
27L
V256
27L
V256
256K (32K x 8) Low-Voltage CMOS EPROM
This document was created with FrameMaker 4 0 4
27LV256
DS11020F-page 2
1996 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
and input voltages w.r.t. V
SS
........ -0.6V to +7.25V
V
PP
voltage w.r.t. V
SS
during
programming ......................................... -0.6V to +14V
Voltage on A9 w.r.t. V
SS
...................... -0.6V to +13.5V
Output voltage w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature .......................... -65C to +150C
Ambient temp. with power applied ..... -65C to +125C
*Notice: Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
Name
Function
A0-A14
Address Inputs
CE
Chip Enable
OE
Output Enable
V
PP
Programming Voltage
O0 - O7
Data Output
V
CC
+5V or +3V Power Supply
V
SS
Ground
NC
No Connection; No Internal
Connection
NU
Not Used; No External Connection Is
Allowed
TABLE 1-2:
READ OPERATION DC CHARACTERISTICS
V
CC
= +5V
10% or 3.0V where indicated
Commercial:
Tamb = 0C to +70C
Industrial:
Tamb = -40C to +85C
Parameter
Part*
Status
Symbol
Min.
Max.
Units
Conditions
Input Voltages
all
Logic "1"
Logic "0"
V
IH
V
IL
2.0
-0.5
V
CC
+1
0.8
V
V
Input Leakage
all
I
LI
-10
10
A
V
IN
= 0 to V
CC
Output Voltages
all
Logic "1"
Logic "0"
V
OH
V
OL
2.4
0.45
V
V
I
OH
= -400
A
I
OL
= 2.1 mA
Output Leakage
all
--
I
LO
-10
10
A
V
OUT
= 0V to V
CC
Input Capacitance
all
--
C
IN
--
6
pF
V
IN
= 0V; Tamb = 25
C;
f = 1 MHz
Output Capacitance
all
--
C
OUT
--
12
pF
V
OUT
= 0V; Tamb = 25
C;
f = 1 MHz
Power Supply Current,
Active
C
I
TTL input
TTL input
I
CC1
I
CC2
--
--
20 @ 5.0V
8 @ 3.0V
25 @ 5.0V
10 @ 3.0V
mA
mA
mA
mA
V
CC
= 5.5V; V
PP
= V
CC
f = 1 MHz;
OE = CE = V
IL
;
I
OUT
= 0 mA;
V
IL
= -0.1 to 0.8V;
V
IH
= 2.0 to V
CC
;
Note 1
Power Supply Current,
Standby
C
I
all
TTL input
TTL input
CMOS input
I
CC
(
S
)
--
1 @ 3.0V
2 @ 3.0V
100 @ 3.0V
mA
mA
A
CE=V
CC
0.2V
* Parts: C=Commercial Temperature Range
I =Industrial Temperature Ranges
Note 1: Typical active current increases .75 mA per MHz up to operating frequency for all temperature ranges.
1996 Microchip Technology Inc.
DS11020F-page 3
27LV256
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
FIGURE 1-1:
READ WAVEFORMS
AC Testing Waveform:
V
IH
= 2.4V and V
IL
= 0.45V; V
OH
= 2.0V V
OL
= 0.8V
Output Load:
1 TTL Load + 100 pF
Input Rise and Fall Times: 10 ns
Ambient Temperature:
Commercial:
Tamb = 0C to +70C
Industrial:
Tamb = -40C to +85C
Parameter
Sym
27HC256-20
27HC256-25
27HC256-30
Units
Conditions
Min
Max
Min
Max
Min
Max
Address to Output Delay
t
ACC
--
200
--
250
--
300
ns
CE = OE = V
IL
CE to Output Delay
t
CE
--
200
--
250
--
300
ns
OE = V
IL
OE to Output Delay
t
OE
--
100
--
125
--
125
ns
CE = V
IL
CE or OE to O/P High
Impedance
t
OFF
0
50
0
50
0
50
ns
Output Hold from
Address CE or OE,
whichever goes first
t
OH
0
--
0
--
0
--
ns
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Outputs
O0 - O7
V
OH
V
OL
Address valid
t
CE(2)
t
OE(2)
High Z
Valid Output
t
ACC
(1) t
OFF
is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
(3) This parameter is sampled and is not 100% tested.
High Z
t
OH
t
OFF(1,3)
CE
OE
Notes:
27LV256
DS11020F-page 4
1996 Microchip Technology Inc.
TABLE 1-4:
PROGRAMMING DC CHARACTERISTICS
TABLE 1-5:
PROGRAMMING AC CHARACTERISTICS
Ambient Temperature: Tamb = 25
C
5
C
V
CC
= 6.5V
0.25V, V
PP
= 13.0V
0.25V
Parameter
Status
Symbol
Min
Max.
Units
Conditions
Input Voltages
Logic"1"
Logic"0"
V
IH
V
IL
2.0
-0.1
V
CC
+1
0.8
V
V
Input Leakage
--
I
LI
-10
10
A
V
IN
= 0V to V
CC
Output Voltages
Logic"1"
Logic"0"
V
OH
V
OL
2.4
0.45
V
V
I
OH
= -400
A
I
OL
= 2.1 mA
V
CC
Current, program & verify
--
I
CC2
--
20
mA
Note 1
V
PP
Current, program
--
I
PP2
--
25
mA
Note 1
A9 Product Identification
--
V
H
11.5
12.5
V
Note 1: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
for Program, Program Verify
AC Testing Waveform:
V
IH
=2.4V and V
IL
=0.45V; V
OH
=2.0V; V
OL
=0.8V
and Program Inhibit Modes
Output Load:
1 TLL Load + 100pF
Ambient Temperature:
Tamb=25
C
5
C
V
CC
= 6.5V
0.25V, V
PP
=13.0V
0.25V
Parameter
Symbol
Min.
Max.
Units
Remarks
Address Set-Up Time
t
AS
2
--
s
Data Set-Up Time
t
DS
2
--
s
Data Hold Time
t
DH
2
--
s
Address Hold Time
t
AH
0
--
s
Float Delay (2)
t
DF
0
130
ns
V
CC
Set-Up Time
t
VCS
2
--
s
Program Pulse Width (1)
t
PW
95
105
s
100
s typical
CE Set-Up Time
t
CES
2
--
s
OE Set-Up Time
t
OES
2
--
s
V
PP
Set-Up Time
t
VPS
2
--
s
Data Valid from OE
t
OE
--
100
ns
Note 1: For express algorithm, initial programming width tolerance is 100
s
5%.
2: This parameter is only sampled and not 100% tested. Output float is defined as the point where data is no
longer driven (see timing diagram).
1996 Microchip Technology Inc.
DS11020F-page 5
27LV256
FIGURE 1-2:
PROGRAMMING WAVEFORMS
TABLE 1-6:
MODES
Operation Mode
CE
OE
V
PP
A9
O0 - O7
Read
V
IL
V
IL
V
CC
X
D
OUT
Program
V
IL
V
IH
V
H
X
D
IN
Program Verify
V
IH
V
IL
V
H
X
D
OUT
Program Inhibit
V
IH
V
IH
V
H
X
High Z
Standby
V
IH
X
V
CC
X
High Z
Output Disable
V
IL
V
IH
V
CC
X
High Z
Identity
V
IL
V
IL
V
CC
V
H
Identity Code
X = Don't Care
V
IH
V
IL
V
IH
V
IL
13.0V(2)
5.0V
6.5V(2)
5.0V
V
IH
V
IL
V
IH
V
IL
Address
Data
V
PP
V
CC
CE
OE
t
DF
and t
OE
are characteristics of the device but must be accommodated by the programmer
V
CC
= 6.5V
0.25V, V
PP
= V
H
= 13.0V
0.25V for express algorithm
t
PW
t
OPW
t
OES
Address Stable
t
AH
t
DS
t
VPS
t
DF
(1)
t
DH
t
OE
(1)
t
AS
Program
Data Stable
Data Out Valid
Verify
t
VCS
Notes:
(1)
(2)
High Z
1.2
Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when:
a)
the CE pin is low to power up (enable) the chip
b)
the OE pin is low to gate the data to the output
pins
For Read operations, if the addresses are stable, the
address access time (t
ACC
) is equal to the delay from
CE to output (t
CE
). Data is transferred to the output
after a delay from the falling edge of OE (t
OE
).
27LV256
DS11020F-page 6
1996 Microchip Technology Inc.
1.3
Standby Mode
The standby mode is defined when the CE pin is high
(V
IH
) and a program mode is not defined. Output Dis-
able
1.4
Output Enable
This feature eliminates bus contention in multiple bus
microprocessor systems and the outputs go to a high
impedance when the following condition is true:
The OE pin is high and program mode is not
defined.
1.5
Programming Mode
The Express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 100-microsecond pulses are
applied until the byte is verified. No over-programming
is required. A flowchart of the express algorithm is
shown in Figure 1.
Programming takes place when:
a)
V
CC
is brought to the proper voltage
b)
V
PP
is brought to the proper V
H
level
c)
the OE pin is high
d)
the CE pin is low
Since the erased state is "1" in the array, programming
of "0" is required. The address to be programmed is set
via pins A0-A14 and the data to be programmed is pre-
sented to pins O0-O7. When data and address are sta-
ble, a low-going pulse on the CE line programs that
location.
1.6
Verify
After the array has been programmed it must be veri-
fied to ensure that all the bits have been correctly pro-
grammed. This mode is entered when all of the
following conditions are met:
a)
V
CC
is at the proper level
b)
V
PP
is at the proper V
H
level
c)
the CE pin is high
d)
the OE line is low
1.7
Inhibit
When Programming multiple devices in parallel with
different data, only CE needs to be under separate con-
trol to each device. By pulsing the CE line low on a par-
ticular device, that device will be programmed, and all
other devices with CE held high will not be pro-
grammed with the data although address and data are
available on their input pins.
1.8
Identity Mode
In this mode specific data is outputted which identifies
the manufacturer as Microchip Technology Inc. and
device type. This mode is entered when Pin A9 is
taken to V
H
(11.5V to 12.5V). The CE and OE lines
must be at V
IL
. A0 is used to access any of the two
non-erasable bytes whose data appears on O0 through
O7.
Pin
Input
Output
Identity
A0
0
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
H
e
x
Manufacturer
Device Type*
V
IL
V
IH
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
0
29
8C
* Code subject to change.
1996 Microchip Technology Inc.
DS11020F-page 7
27LV256
FIGURE 1-3:
PROGRAMMING EXPRESS ALGORITHM
Start
ADDR = First Location
V
CC
= 6.5V
V
PP
= 13.0V
X = 0
Program one 100
s pulse
Increment X
Verify
Byte
Pass
Fail
X = 10?
No
Yes
Device
Failed
Last
Address?
No
Increment Address
Conditions:
T
amb
= 25+/-5C
V
CC
= 6.5+/-0.25V
V
PP
= 13.0+/-0.25V
Yes
V
CC
= V
PP
= 4.5V, 5.5V
Device
Passed
All
bytes
= original
data?
Device
Failed
No
Yes
27LV256
DS11020F-page 8
1996 Microchip Technology Inc.
NOTES:
1996 Microchip Technology Inc.
DS11020F-page 9
27LV256
NOTES:
27LV256
DS11020F-page 10
1996 Microchip Technology Inc.
NOTES:
27LV256
1996 Microchip Technology Inc.
DS11020F-page 11
27LV256 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Package:
L = Plastic Leaded Chip Carrier
P = Plastic DIP (600 Mil)
SO = Plastic SOIC (300 Mil)
VS = Very Small Outline Package (VSOP) 8X13.4mm
Temperature
Blank = 0C to +70C
Range:
I
= -40C to +85C
Access
20 = 200 ns
Time:
25 = 250 ns
30 = 300 ns (SOIC only)
Device:
27LV256
256K (32K x 8) Low-Voltage CMOS EPROM
27LV256
25
I
/P
DS11020F-page 12
1996 Microchip Technology Inc.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
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1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
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