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Section 4. Architecture

HIGHLIGHTS

This section of the manual contains the following major topics:

4.1

Introduction .................................................................................................................... 4-2

4.2

Clocking Scheme/Instruction Cycle ............................................................................... 4-5

4.3

Instruction Flow/Pipelining ............................................................................................. 4-6

4.4

I/O Descriptions ............................................................................................................. 4-7

4.5

Design Tips .................................................................................................................. 4-14

4.6

Related Application Notes............................................................................................ 4-15

4.7

Revision History ........................................................................................................... 4-16

PIC18C Reference Manual

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4.1

Introduction

The high performance of the PIC18CXXX devices can be attributed to a number of architectural
features commonly found in RISC microprocessors. These include:

· Harvard architecture
· Long Word Instructions
· Single Word Instructions
· Single Cycle Instructions
· Instruction Pipelining
· Reduced Instruction Set
· Register File Architecture
· Orthogonal (Symmetric) Instructions

Figure 4-2

shows a general block diagram for PIC18CXXX devices.

Harvard Architecture:

Harvard architecture has the program memory and data memory as separate memories which
are accessed from separate buses. This improves bandwidth over traditional von Neumann
architecture in which program and data are fetched from the same memory using the same bus.
To execute an instruction, a von Neumann machine must make one or more (generally more)
accesses across the 8-bit bus to fetch the instruction. Then data may need to be fetched, oper-
ated on and possibly written. As can be seen from this description, the bus can become
extremely congested. With a Harvard architecture, the instruction is fetched in a single instruction
cycle (all 16 bits). While the program memory is being accessed, the data memory is on an inde-
pendent bus and can be read and written. These separated busses allow one instruction to exe-
cute, while the next instruction is fetched. A comparison of Harvard and von Neumann
architectures is shown in

Figure 4-1

Figure 4-1: Harvard vs. von Neumann Block Architectures

Long Word Instructions:

Long word instructions have a wider (more bits) instruction bus than the 8-bit data memory bus.
This is possible because the two buses are separate. This allows instructions to be sized differ-
ently than the 8-bit wide data word and allows a more efficient use of the program memory, since
the program memory width is optimized to the architectural requirements.

Single Word Instructions:

Single word instruction opcodes are 16-bits wide making it possible to have all but a few instruc-
tions be single word instructions. A 16-bit wide program memory access bus fetches a 16-bit
instruction in a single cycle. With single word instructions, the number of words of program mem-
ory locations equals the number of instructions for the device. This means that all locations are
valid instructions.

Typically in the von Neumann architecture, most instructions are multi-byte. In general, a device
with 4 Kbytes of program memory would allow approximately 2K of instructions. This 2:1 ratio is
generalized and dependent on the application code. Since each instruction may take multiple
bytes, there is no assurance that each location is a valid instruction.

Program

Memory

Data

Memory

Program

Memory

and

Data

CPU

Harvard

von Neumann

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Double Word Instructions:

Some operations require more information then can be stored in the 16 bits of a program memory
location. These operations require a double word instruction, and are therefore 32-bits wide.
Instructions that require this second instruction word are:

· Memory to memory move instruction (12 bits for each RAM address)

- MOVFF

SourceReg, DestReg

· Literal value to FSR move instruction (12 bits for data and 2 bits for FSR to load)

- LFSR

FSR#, Address

· Call and goto operations (20 bits for address)

- CALL

Address

- GOTO

Address

The first word indicates to the CPU that the next program memory location is the additional infor-
mation for this instruction and not an instruction. If the CPU tries to execute the second word of
an instruction (due to a software modified PC pointing to that location as an instruction), the
fetched data is executed as a NOP.

Double word instruction execution is not split between the two T

cycles by an interrupt request.

That is, when an interrupt request occurs during the execution of a double word instruction, the
execution of the instruction is completed before the processor vectors to the interrupt address.
The interrupt latency is preserved.

Instruction Pipeline:

The instruction pipeline is a two-stage pipeline that overlaps the fetch and execution of instruc-
tions. The fetch of the instruction takes one T

, while the execution takes another T

. However,

due to the overlap of the fetch of current instruction and execution of previous instruction, an
instruction is fetched and another instruction is executed every T

Single Cycle Instructions:

With the program memory bus being 16-bits wide, the entire instruction is fetched in a single
machine cycle (T

), except for double word instructions. The instruction contains all the infor-

mation required and is executed in a single cycle. There may be a one cycle delay in execution
if the result of the instruction modified the contents of the program counter. This requires the pipe-
line to be flushed and a new instruction to be fetched.

Two Cycle Instructions:

Double word instructions require two cycles to execute, since all the required information is in the
32 bits.

Reduced Instruction Set:

When an instruction set is well designed and highly orthogonal (symmetric), fewer instructions
are required to perform all needed tasks. With fewer instructions, the whole set can be more rap-
idly learned.

Register File Architecture:

The register files/data memory can be directly or indirectly addressed. All special function regis-
ters, including the program counter, are mapped in the data memory.

Orthogonal (Symmetric) Instructions:

Orthogonal instructions make it possible to carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of "special instructions" make programming
simple yet efficient. In addition, the learning curve is reduced significantly. The Enhanced MCU
instruction set uses only three non-register oriented instructions, which are used for two of the
cores features. One is the SLEEP instruction, which places the device into the lowest power use
mode. The second is the CLRWDT instruction, which verifies the chip is operating properly by pre-
venting the on-chip Watchdog Timer (WDT) from overflowing and resetting the device. The third
is the RESET instruction, which resets the device.

PIC18C Reference Manual

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Figure 4-2:

General Enhanced MCU Block Diagram

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKIN

OSC2/CLKOUT

MCLR

, V

PORTA

PORTB

PORTC

RA4
RA5

RB0/INT0

RB<7:4>

RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7

Brown-out

Reset

Note 1: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are

device dependent.

RA3

RA2

RA1

RA0

Timing

Generation

4X PLL

RB1/INT1

Data Latch

Data RAM

(up to 4K

address reach)

Address Latch

Address<12>

Bank0, F

BSR

FSR0

FSR1

FSR2

inc / dec

logic

Decode

PCH

PCL

PCLATH

31 Level Stack

Program Counter

PRODL

PRODH

8 x 8 Multiply

BITOP

ALU<8>

Address Latch

Program Memory

(up to 2M Bytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

TABLELATCH

Instruction

ROMLATCH

PORTD

RB2/INT2
RB3

T1OSI
T1OSO

PCLATU

PCU

RA6

Precision

Reference

Bandgap

Addressable

CCP's

Synchronous

Timer0

Timer1

Timer2

Serial Port

A/D Converter

Timer3

Enhanced

USART

Master

Other

Peripherals

RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7

PORTE

RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7

Peripheral Modules (Note 1)

CAN

USB

PORTx

Rx0
Rx1
Rx2
Rx3
Rx4
Rx5
Rx6
Rx7

CCP's

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4.2

Clocking Scheme/Instruction Cycle

The clock input is internally divided by four to generate four non-overlapping quadrature clocks,
namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the
instruction is fetched from the program memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the following Q1 through Q4. The clocks and
instruction execution flow are illustrated in

Figure 4-3

and

Example 4-1

Figure 4-3: Clock/Instruction Cycle

4.2.1

Phase Lock Loop (PLL)

The clock input is multiplied by four by the PLL. Therefore, when it is internally divided by four, it
provides an instruction cycle that is the same frequency as the external clock frequency. Four
non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4 are still generated internally.

Internally, the program counter (PC) is incremented every Q1, and the instruction is fetched from
the program memory and latched into the instruction register in Q4. The instruction is decoded
and executed during the following Q1 through Q4. The clocks and instruction execution flow are
illustrated in

Figure 4-4

and

Example 4-1

Figure 4-4: Clock/Instruction Cycle with PLL

Device Clock

CLKOUT

(RC mode)

PC+2

PC+4

Fetch INST (PC)

Execute INST (PC-2)

Fetch INST (PC+2)

Execute INST (PC)

Fetch INST (PC+4)

Execute INST (PC+2)

Internal

phase

clock

(OSC1 or T1OSCI)

PLL Output

OSC2/CLKOUT

(RC mode)

PC+2

PC+4

Fetch INST (PC)

Execute INST (PC-2)

Fetch INST (PC+2)

Execute INST (PC)

Fetch INST (PC+4)

Execute INST (PC+2)

Internal

phase

clock

PIC18C Reference Manual

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4.3

Instruction Flow/Pipelining

An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). Fetch takes one instruction
cycle, while decode and execute takes another instruction cycle. However, due to pipelining, each
instruction effectively executes in one cycle. If an instruction causes the program counter to
change (e.g. GOTO instruction), then an extra cycle is required to complete the instruction (See

Example 4-1

The instruction fetch begins with the program counter incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the "Instruction Register (IR)" in
cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data
memory is read during Q2 (operand read) and written during Q4 (destination write).

Example 4-1

shows the operation of the two stage pipeline for the instruction sequence shown.

At time T

0, the first instruction is fetched from program memory. During T

1, the first instruc-

tion executes, while the second instruction is fetched. During T

2, the second instruction exe-

cutes, while the third instruction is fetched. During T

3, the fourth instruction is fetched, while

the third instruction (CALL SUB_1) is executed. When the third instruction completes execution,
the CPU forces the address of instruction four onto the Stack and then changes the Program
Counter (PC) to the address of SUB_1. This means that the instruction that was fetched during
T

3 needs to be "flushed" from the pipeline. During T

4, instruction four is flushed (executed

as a NOP) and the instruction at address SUB_1 is fetched. Finally during T

5, instruction five is

executed and the instruction at address SUB_1 + 2 is fetched.

Example 4-1: Instruction Pipeline Flow

Most instructions are single cycle. Program branches take two cycles, since the fetch instruction is "flushed" from
the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. CALL SUB_1

Fetch 3

Execute 3

4. BSF

PORTA, BIT3 (Forced NOP)

Fetch 4

Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

Fetch SUB_1 + 2

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4.4

I/O Descriptions

Table 4-1

gives a brief description of device pins and the functions that may be multiplexed to a

port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral
module's functional requirements may force an override of the data direction (TRIS bit) of the port
pin (such as in the A/D and Comparator modules).

Table 4-1:

I/O Descriptions

Pin Name

Pin

Type

Buffer

Type

Description

A19

System bus address line 19

A18

System bus address line 18

A17

System bus address line 17

A16

System bus address line 16

AD15

I/O

TTL

System bus address/data line 15

AD14

I/O

TTL

System bus address/data line 14

AD13

I/O

TTL

System bus address/data line 13

AD12

I/O

TTL

System bus address/data line 12

AD11

I/O

TTL

System bus address/data line 11

AD10

I/O

TTL

System bus address/data line 10

AD9

I/O

TTL

System bus address/data line 9

AD8

I/O

TTL

System bus address/data line 8

AD7

I/O

TTL

System bus address/data line 7

AD6

I/O

TTL

System bus address/data line 6

AD5

I/O

TTL

System bus address/data line 5

AD4

I/O

TTL

System bus address/data line 4

AD3

I/O

TTL

System bus address/data line 3

AD2

I/O

TTL

System bus address/data line 2

AD1

I/O

TTL

System bus address/data line 1

AD0

I/O

TTL

System bus address/data line 0

ALE

System bus address latch enable strobe

Analog Input Channels

AN0

Analog

AN1

Analog

AN2

Analog

AN3

Analog

AN4

Analog

AN5

Analog

AN6

Analog

AN7

Analog

AN8

Analog

AN9

Analog

AN10

Analog

AN11

Analog

AN12

Analog

AN13

Analog

AN14

Analog

AN15

Analog

VDD

Analog Power

Legend: TTL = TTL-compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = output

PU = Weak internal pull-up

I = input

Analog = Analog input or output

P = Power

PIC18C Reference Manual

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VSS

Analog Ground

BA0

System bus byte address 0

CANRX

CAN bus receive pin

CANTX0

CAN bus transmit

CANTX1

CAN bus complimentary transmit or CAN bus bit time clock

CCP1

I/O

Capture1 input/Compare1 output/PWM1 output

CCP2

I/O

Capture2 input/Compare2 output/PWM2 output.

I/O

USART Synchronous Clock, always associated with TX pin function
(See related TX, RX, DT)

CLKI

ST/CMOS

External clock source input. Always associated with pin function
OSC1. (See related OSC1/CLKIN, OSC2/CLKOUT pins)

CLKO

Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
Always associated with OSC2 pin function. (See related OSC2,
OSC1)

CMPA

Comparator A output

CMPB

Comparator B output

TTL

Chip select control for parallel slave port (See related RD and WR)

REF

Analog

Comparator voltage reference output

I/O

USART Synchronous Data. Always associated RX pin function. (See
related RX, TX, CK)

Table 4-1:

I/O Descriptions (Continued)

Pin Name

Pin

Type

Buffer

Type

Description

Legend: TTL = TTL-compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = output

PU = Weak internal pull-up

I = input

Analog = Analog input or output

P = Power

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INT0

External Interrupt0

INT1

External Interrupt1

INT2

External Interrupt2

System bus low byte strobe

LVDIN

Analog

Low voltage detect input

MCLR

I/P

Master clear (reset) input or programming voltage input. This pin is
an active low reset to the device.

These pins should be left unconnected.

System bus output enable strobe

OSC1

ST/CMOS

Oscillator crystal input or external clock source input. ST buffer when
configured in RC mode. CMOS otherwise.

OSC2

Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.

PSP0

I/O

TTL

Parallel Slave Port for interfacing to a microprocessor port. These
pins have TTL input buffers when PSP module is enabled.

PSP1

I/O

TTL

PSP2

I/O

TTL

PSP3

I/O

TTL

PSP4

I/O

TTL

PSP5

I/O

TTL

PSP6

I/O

TTL

PSP7

I/O

TTL

PORTA is a bi-directional I/O port.

RA0

I/O

TTL

RA1

I/O

TTL

RA2

I/O

TTL

RA3

I/O

TTL

RA4

I/O

RA4 is an open drain when configured as output.

RA5

I/O

TTL

RA6

I/O

TTL

PORTB is a bi-directional I/O port. PORTB can be software pro-
grammed for internal weak pull-ups on all inputs.

RB0

I/O

TTL

RB1

I/O

TTL

RB2

I/O

TTL

RB3

I/O

TTL

RB4

I/O

TTL

Interrupt on change pin.

RB5

I/O

TTL

Interrupt on change pin.

RB6

I/O

TTL/ST

Interrupt on change pin. Serial programming clock. TTL input
buffer as general purpose I/O, Schmitt Trigger input buffer when
used as the serial programming clock.

RB7

I/O

TTL/ST

Interrupt on change pin. Serial programming data. TTL input
buffer as general purpose I/O, Schmitt Trigger input buffer when
used as the serial programming data.

Table 4-1:

I/O Descriptions (Continued)

Pin Name

Pin

Type

Buffer

Type

Description

Legend: TTL = TTL-compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = output

PU = Weak internal pull-up

I = input

Analog = Analog input or output

P = Power

PIC18C Reference Manual

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PORTC is a bi-directional I/O port.

RC0

I/O

RC1

I/O

RC2

I/O

RC3

I/O

RC4

I/O

RC5

I/O

RC6

I/O

RC7

I/O

TTL

Read control for parallel slave port. (See also WR and CS pins.)

PORTD is a bi-directional I/O port.

RD0

I/O

RD1

I/O

RD2

I/O

RD3

I/O

RD4

I/O

RD5

I/O

RD6

I/O

RD7

I/O

PORTE is a bi-directional I/O port.

RE0

I/O

RE1

I/O

RE2

I/O

RE3

I/O

RE4

I/O

RE5

I/O

RE6

I/O

RE7

I/O

PORTF is a digital input

RF0

I/O

RF1

I/O

RF2

I/O

RF3

I/O

RF4

I/O

RF5

I/O

RF6

I/O

RF7

I/O

Table 4-1:

I/O Descriptions (Continued)

Pin Name

Pin

Type

Buffer

Type

Description

Legend: TTL = TTL-compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = output

PU = Weak internal pull-up

I = input

Analog = Analog input or output

P = Power

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PORTG is a digital input

RG0

I/O

RG1

I/O

RG2

I/O

RG3

I/O

RG4

I/O

RG5

I/O

RG6

I/O

RG7

I/O

PORTH is a digital input

RH0

I/O

RH1

I/O

RH2

I/O

RH3

I/O

RH4

I/O

RH5

I/O

RH6

I/O

RH7

I/O

PORTJ is a digital input

RJ0

I/O

RJ1

I/O

RJ2

I/O

RJ3

I/O

RJ4

I/O

RJ5

I/O

RJ6

I/O

RJ7

I/O

PORTK is a digital input

RK0

I/O

RK1

I/O

RK2

I/O

RK3

I/O

RK4

I/O

RK5

I/O

RK6

I/O

RK7

I/O

Table 4-1:

I/O Descriptions (Continued)

Pin Name

Pin

Type

Buffer

Type

Description

Legend: TTL = TTL-compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = output

PU = Weak internal pull-up

I = input

Analog = Analog input or output

P = Power

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PORTL is a digital input

RL0

I/O

RL1

I/O

RL2

I/O

RL3

I/O

RL4

I/O

RL5

I/O

RL6

I/O

RL7

I/O

USART Asynchronous Receive

SCL

I/O

Synchronous serial clock input/output for I

C mode.

SCLA

I/O

Synchronous serial clock for I

C interface.

SCLB

I/O

Synchronous serial clock for I

C interface.

SDA

I/O

Data I/O

SDAA

I/O

Synchronous serial data I/O for I

C interface

SDAB

I/O

Synchronous serial data I/O for I

C interface

SCK

I/O

Synchronous serial clock input/output for SPI mode.

SDI

SPI Data In

SDO

SPI Data Out (SPI mode)

SPI Slave Select input

T0CKI

Timer0 external clock input

T1CKI

Timer1 external clock input

T1OSO

CMOS

Timer1 oscillator output

T1OSI

CMOS

Timer1 oscillator input

USART Asynchronous Transmit (See related RX)

System bus upper byte strobe

Table 4-1:

I/O Descriptions (Continued)

Pin Name

Pin

Type

Buffer

Type

Description

Legend: TTL = TTL-compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = output

PU = Weak internal pull-up

I = input

Analog = Analog input or output

P = Power

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REF

Analog

Analog High Voltage Reference input.
DR reference voltage output on devices with comparators.

REF

Analog

Analog High Voltage Reference input.
Usually multiplexed onto an analog pin.

REF

Analog

Analog Low Voltage Reference input.
Usually multiplexed onto an analog pin.

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

Programming voltage input

TTL

Write control for parallel slave port (See CS and RD pins also).

WRL

System bus write low byte strobe

WRH

System bus write high byte strobe

Table 4-1:

I/O Descriptions (Continued)

Pin Name

Pin

Type

Buffer

Type

Description

Legend: TTL = TTL-compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = output

PU = Weak internal pull-up

I = input

Analog = Analog input or output

P = Power

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4.6

Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-
tion notes may not be written specifically for the Enhanced family (that is, they may be written for
the Base-Line, the Mid-Range, or High-End families), but the concepts are pertinent and could
be used (with modification and possible limitations). The current application notes related to
Architecture are:

Title

Application Note #

No related application notes at this time.

Note:

Please visit the Microchip Web site for additional software code examples. These

code examples are stand alone examples to assist in the understanding of the
PIC18CXXX. The web address for these examples is:

http://www.microchip.com/10/faqs/codeex/

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