32,64 Meg x 64 SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
1
2002, Micron Technology Inc.
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
SYNCHRONOUS
DRAM MODULE
MT8LSDT3264A(I) - 256MB
MT16LSDT6464A(I) - 512MB
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/moduleds
Features
PC100- and PC133-compliant
JEDEC-standard 168-pin, dual in-line memory
module (DIMM)
Unbuffered
256MB (32 Meg x 64), 512MB (64 Meg x 64)
Single +3.3V 0.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal SDRAM banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, including Concurrent Auto
Precharge, and Auto Refresh Modes
64ms, 8,192 cycle Auto Refresh cycle
Self Refresh Mode
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
Figure 1: 168-Pin DIMM (MO161)
OPTIONS
MARKING
Package
Unbuffered
A
168-pin DIMM (gold)
G
Operating Temperature Range
Commercial (0C to +70C)
None
Industrial (-40C to +85C)
1
NOTE:
1. Consult Micron for availability; Industrial Tempera-
ture Option available in -133 speed only.
I
Memory Clock/CAS Latency
(133 MHz)/CL = 2
-13E
(133 MHz)/CL = 3
-133
(100 MHz)/CL = 2
-10E
Table 1:
Address Table
256MB
MODULE
512MB
MODULE
Refresh Count
8K
8K
Device Banks
4 (BA0, BA1)
4 (BA0, BA1)
Device Configuration
32 Meg x 8
32 Meg x 8
Row Addressing
8K (A0A12)
8K (A0A12)
Column Addressing
1K (A0A9)
1K (A0A9)
Module Banks
1 (S0,S2)
2 (S0,S2; S1,S3)
Table 2:
Timing parameters
MODULE
MARKINGS
PC100
CL -
t
RCD -
t
RP
PC133
CL -
t
RCD -
t
RP
-13E
2 - 2 - 2
2 - 2 - 2
-133
2 - 2 - 2
3 - 3 - 3
-10E
2 - 2 - 2
NA
Table 3:
Part Numbers
PARTNUMBER
1
NOTE:
1. The designators for component and PCB revision
are the last two characters of each part number.
Consult factory for current revision codes. Example:
MT8LSDT3264AG-133B1.
CONFIGURATION
SYSTEM
BUS SPEED
MT8LSDT3264AG-13E_
32 Meg x 64
133 MHz
MT8LSDT3264AG(I)-133_
32 Meg x 64
133 MHz
MT8LSDT3264AG-10E_
32 Meg x 64
100 MHz
MT16LSDT6464AG-13E_
64 Meg x 64
133 MHz
MT16LSDT6464AG(I)-133_
64 Meg x 64
133 MHz
MT16LSDT6464AG-10E_
64 Meg x 64
100 MHz
Standard
Low Profile
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
32,64 Meg x 64 SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
2
2002, Micron Technology Inc.
Figure 2: PIN Locations (168-PIN DIMM)
Table 4:
Pin Assignment, Standard
PCB (168-Pin DIMM Front)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
V
SS
22
NC
43
V
SS
64
V
SS
2
DQ0
23
V
SS
44
NC
65
DQ21
3
DQ1
24
NC
45
S2#
66
DQ22
4
DQ2
25
NC
46
DQMB2
67
DQ23
5
DQ3
26
V
DD
47
DQMB3
68
V
SS
6
V
DD
27
WE#
48
NC
69
DQ24
7
DQ4
28 DQMB0
49
V
DD
70
DQ25
8
DQ5
29 DQMB1
50
NC
71
DQ26
9
DQ6
30
S0#
51
NC
72
DQ27
10
DQ7
31
NC
52
NC
73
V
DD
11
DQ8
32
V
SS
53
NC
74
DQ28
12
V
SS
33
A0
54
V
SS
75
DQ29
13
DQ9
34
A2
55
DQ16
76
DQ30
14
DQ10
35
A4
56
DQ17
77
DQ31
15
DQ11
36
A6
57
DQ18
78
V
SS
16
DQ12
37
A8
58
DQ19
79
CK2
17
DQ13
38
A10
59
V
DD
80
NC
18
V
DD
39
BA1
60
DQ20
81
NC
19
DQ14
40
V
DD
61
NC
82
SDA
20
DQ15
41
V
DD
62
NC
83
SCL
21
NC
42
CK0
63
CKE1
84
V
DD
Table 5:
Pin Assignment, Standard
PCB (168-Pin DIMM Back)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
85
V
SS
106
NC
127
V
SS
148
V
SS
86
DQ32
107
V
SS
128
CKE0
149
DQ53
87
DQ33
108
NC
129
S3#
150
DQ54
88
DQ34
109
NC
130 DQMB6
151
DQ55
89
DQ35
110
V
DD
131 DQMB7 152
V
SS
90
V
DD
111
CAS#
132
NC
153
DQ56
91
DQ36
112 DQMB4 133
V
DD
154
DQ57
92
DQ37
113 DQMB5 134
NC
155
DQ58
93
DQ38
114
S1#
135
NC
156
DQ59
94
DQ39
115
RAS#
136
NC
157
V
DD
95
DQ40
116
V
SS
137
NC
158
DQ60
96
V
SS
117
A1
138
V
SS
159
DQ61
97
DQ41
118
A3
139
DQ48
160
DQ62
98
DQ42
119
A5
140
DQ49
161
DQ63
99
DQ43
120
A7
141
DQ50
162
V
SS
100
DQ44
121
A9
142
DQ51
163
CK3
101
DQ45
122
BA0
143
V
DD
164
NC
102
V
DD
123
A11
144
DQ52
165
SA0
103
DQ46
124
V
DD
145
NC
166
SA1
104
DQ47
125
CK1
146
NC
167
SA2
105
NC
126
A12
147
NC
168
V
DD
Front View
Back View (Populated only for 512MB module)
Indicates a V
DD
pin
Indicates a V
SS
pin
PIN 1
PIN 41
PIN 84
PIN 85
PIN125
PIN 168
U1
U2
U3
U4
U6
U7
U8
U9
U10
U11
U12
U13
U14
U16
U17
U18
U19
See Figure 10, 256MB Module Dimensions, on page 23 and Figure 11, 512MB Module Dimensions, on
page 24 for module dimensions.
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
32,64 Meg x 64 SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
3
2002, Micron Technology Inc.
Table 6:
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information.
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
27, 111, 115
RAS#, CAS#,
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
42, 79, 125, 163
CK0-CK3
Input
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
63, 128
CKE0, CKE1
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in
progress). CKE is synchronous except after the device enters
power- down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input
buffers, including CK, are disabled during power-down and
self refresh modes, providing low standby power.
30, 45,114, 129
S0# -S3#
Input
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
28, 29, 46, 47, 112, 113, 130,
131
DQMB0-DQMB7
Input
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
39, 122
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
33 - 38, 117 - 121, 123, 126
A0-A12
Input
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto prcharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory arrary in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
83
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
165-167
SA0-SA2
Input
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
2-5, 7-11, 13-17, 19-20, 55-58,
60, 65-67, 69-72, 74-77, 86-89,
91-95, 97-101, 103-104,
139-142, 144, 149-151,
153-156,158-161
DQ0-DQ63
Input/
Output
Data I/O: Data bus.
82
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
32,64 Meg x 64 SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
4
2002, Micron Technology Inc.
6, 18, 26, 40, 41, 49, 59, 73,
84, 90, 102, 110, 124, 133,
143, 157, 168
V
DD
Supply
Power Supply: +3.3V 0.3V.
1, 12, 23, 32, 43, 54, 64, 68,
78, 85, 96, 107, 116, 127, 138,
148, 152, 162
V
SS
Supply
Ground.
21-22, 24-25, 31, 44, 48,
50-53, 61-62, 80, 81, 105-106,
108-109, 132, 134-137,
145-147, 164
NC
Not Connected: These pins are not connected on these
modules.
Table 6:
Pin Descriptions (Continued)
Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information.
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
32,64 Meg x 64 SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
5
2002, Micron Technology Inc.
Figure 3: Functional Block Diagram
Single Bank Modules
DQM CS#
U8
A0
SA0
SPD
SDA
A1
SA1
A2
SA2
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQMB7
DQM CS#
U6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB6
DQM CS#
U4
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB5
DQM CS#
U2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB4
DQM CS#
U9
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQMB3
DQM CS#
U7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB2
DQM CS#
U3
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB1
DQM CS#
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB0
S2#
S0#
RAS#
CAS#
CKE0
WE#
RAS#: SDRAMs
CAS#: SDRAMs
CKE0: SDRAMs
WE#: SDRAMs
A0-A11: SDRAMs
BA0: SDRAMs
BA1: SDRAMs
A0-A11
BA0
BA1
V
DD
V
SS
SDRAMs
SDRAMs
10pF
CK1, CK3
U1
U2
U3
U4
U5
CK0
U6
U7
U8
U9
CK2
3.3pF
SCL
WP
U10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Notes:
All resistor values are 10
W unless otherwise specified.
Per industry standard, Micron modules use various component speed grades as
referenced in the module part numbering guide at:
www.micron.com/numberguide
.
SDRAMs = MT48LC32M8A2TG, Commercial Temperature
SDRAMs = MT48LC32M8A2TG-75 IT, Industrial Temperature
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