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Электронный компонент: MT18LSDT3272D

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1
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
PART NUMBERS
PART NUMBER
CONFIGURATION SYSTEM BUS SPEED
MT18LSDT3272DG-13E__
32 Meg x 72
133 MHz
MT18LSDT3272DG-133__
32 Meg x 72
133 MHz
MT18LSDT3272DG-10E__
32 Meg x 72
100 MHz
MT18LSDT6472DG-13E__
64 Meg x 72
133 MHz
MT18LSDT6472DG-133__
64 Meg x 72
133 MHz
MT18LSDT6472DG-10E__
64 Meg x 72
100 MHz
NOTE: The designators for component and PCB revision are
the last two characters of each part number. Consult
factory for current revision codes. Example:
MT18LSDT3272DG-133B1
TIMING PARAMETERS
Module
PC100
PC133
Markings
CL -
t
RCD -
t
RP
CL -
t
RCD -
t
RP
-13E
2 - 2 - 2
2 - 2 - 2
-133
2 - 2 - 2
3 - 3 - 3
-10E
2 - 2 - 2
NA
SYNCHRONOUS
DRAM MODULE
MT18LSDT3272D - 256MB
MT18LSDT6472D - 512MB
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/moduleds
FEATURES
JEDEC-standard 168-pin, dual in-line memory
module (DIMM)
PC133- and PC100-compliant
Registered inputs with one-clock delay
Utilizes 100 MHz and 133 MHz SDRAM components
Phase-lock loop (PLL) clock driver to minimize
loading
ECC, 1-bit error detection and correction
256MB (32 Meg x 72), 512MB (64 Meg x 72)
Single +3.3V 0.3V power supply
Fully synchronous; all signals registered on positive
edge of PLL clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal SDRAM banks for hiding row access/
precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, Auto Refresh, and Self Refresh
Modes
64ms refresh (256MB - 4,096 cycles; 512MB - 8,192
cycles)
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
OPTIONS
MARKING
Package
168-pin DIMM (gold)
G
Frequency/CAS Latency*
133 MHz/CL = 2
-13E
133 MHz/CL = 3
-133
100 MHz/CL = 2
-10E
*
An extra clock cycle will be incurred when the module is in registered
mode.
ADDRESS TABLE
256MB MODULE
512MB MODULE
Refresh Count
4K
8K
Device Banks
4 (BA0, BA1)
4 (BA0, BA1)
Device Configuration
16 Meg x 8
32 Meg x 8
Row Addressing
4K (A0A11)
8K (A0A12)
Column Addressing
1K (A0A9)
1K (A0A9)
Module Banks
2 (S0,S2; S1,S3)
2(S0,S2; S1,S3)
168-PIN DIMM
MO 168
Low Profile
Standard
2
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
PIN SYMBOL PIN SYMBOL PIN
SYMBOL
PIN
SYMBOL
1
V
SS
22
CB1
43
V
SS
64
V
SS
2
DQ0
23
V
SS
44
NC
65
DQ21
3
DQ1
24
NC
45
S2#
66
DQ22
4
DQ2
25
NC
46
DQMB2
67
DQ23
5
DQ3
26
V
DD
47
DQMB3
68
V
SS
6
V
DD
27
WE#
48
NC
69
DQ24
7
DQ4
28
DQMB0
49
V
DD
70
DQ25
8
DQ5
29
DQMB1
50
NC
71
DQ26
9
DQ6
30
S0#
51
NC
72
DQ27
10
DQ7
31
NC
52
CB2
73
V
DD
11
DQ8
32
V
SS
53
CB3
74
DQ28
12
V
SS
33
A0
54
V
SS
75
DQ29
13
DQ9
34
A2
55
DQ16
76
DQ30
14
DQ10
35
A4
56
DQ17
77
DQ31
15
DQ11
36
A6
57
DQ18
78
V
SS
16
DQ12
37
A8
58
DQ19
79
DNU
17
DQ13
38
A10
59
V
DD
80
NC
18
V
DD
39
BA1
60
DQ20
81
NC
19
DQ14
40
V
DD
61
NC
82
SDA
20
DQ15
41
V
DD
62
NC
83
SCL
21
CB0
42
CKO
63
CKE1
84
V
DD
PIN ASSIGNMENT (168-Pin DIMM FRONT)
PIN SYMBOL PIN SYMBOL
PIN
SYMBOL
PIN
SYMBOL
85
V
SS
106
CB5
127
V
SS
148
V
SS
86
DQ32
107
V
SS
128
CKE0
149
DQ53
87
DQ33
108
NC
129
S3#
150
DQ54
88
DQ34
109
NC
130
DQMB6
151
DQ55
89
DQ35
110
V
DD
131
DQMB7
152
V
SS
90
V
DD
111
CAS#
132
NC
153
DQ56
91
DQ36
112 DQMB4
133
V
DD
154
DQ57
92
DQ37
113 DQMB5
134
NC
155
DQ58
93
DQ38
114
S1#
135
NC
156
DQ59
94
DQ39
115
RAS#
136
CB6
157
V
DD
95
DQ40
116
V
SS
137
CB7
158
DQ60
96
V
SS
117
A1
138
V
SS
159
DQ61
97
DQ41
118
A3
139
DQ48
160
DQ62
98
DQ42
119
A5
140
DQ49
161
DQ63
99
DQ43
120
A7
141
DQ50
162
V
SS
100
DQ44
121
A9
142
DQ51
163
DNU
101
DQ45
122
BA0
143
V
DD
164
NC
102
V
DD
123
A11
144
DQ52
165
SA0
103
DQ46
124
V
DD
145
NC
166
SA1
104
DQ47
125
DNU
146
NC
167
SA2
105
CB4
126
NC/
A12
147
REGE
168
V
DD
PIN ASSIGNMENT (168-Pin DIMM BACK)
NOTE:
Pin 126 is not connected (NC) for the 256MB module. For the 512MB module, pin 126 is address input A12.
PIN 1
PIN 84
Back View
PIN 40
PIN 41
PIN 168
PIN 85
PIN 125
PIN 124
Front View
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
PIN 84
PIN 168
PIN 85
U1
U2
U3
U5
U4
U6
U7
U9
U10
U11
U12
U13
U14
PIN 1
Back View
Front View
168-PIN DIMM PIN LOCATIONS
3
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
27, 111, 115
WE#, RAS#,
Input
Command Inputs: WE#, RAS# and CAS# (along with S#)
CAS#
define the command being entered.
42
CK0
Input
Clock: System clock inputs. All SDRAM inputs are sampled
on the rising edge of CK, which is distributed through an
on-board PLL to all devices.
63, 128
CKE0, CKE1
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW)
the CK signal. Deactivating the clock provides POWER-
DOWN and SELF REFRESH operation (all device banks idle)
or CLOCK SUSPEND operation (burst access in progress). CKE
is synchronous except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers,
including CK, are disabled during power-down and self
refresh modes, providing low standby power.
30, 45, 114, 129
S0#-S3#
Input
Chip Select: S# enables (registered LOW) and disable
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
28, 29, 46, 47, 112,
DQMB0-
Input
Input/Output Mask: DQMB is an input mask signal for write
113, 130, 131
DQMB7
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
39, 122
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE or PRECHARGE command is being
applied.
33, 34, 35, 36, 37, 38,
A0-A11
Input
Address Inputs: Provide the row address for ACTIVE
117, 118, 119, 120, 121,
(256MB)
commands, and the column addres and auto precharge bit
123, 126
(512MB)
A0-A12
(A10) for READ/WRITE commands, to select one location out
(512MB)
of the memory array in the espective device bank. A10
sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address input also provide the op-code
during a MODE REGISTER SET command.
147
REGE
Input
Register Enable.
2-5, 7-11, 13-17, 19, 20,
DQ0-DQ63
Input/
Data I/Os: Data bus.
55-58, 60, 65-67, 69-72,
Output
74-77, 86-89, 91-95,
97-101, 103, 104,
139-142, 144, 149-151,
153-156, 158-161
21, 22, 52, 53, 105, 106,
CB0-CB7
Input/
Check Bits. ECC 1-bit error dectection and correction
136-137
Output
NOTE: Pin numbers may not correlate with symbols. Refer to Pin Assignment tables for pin number and symbol information.
4
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
NOTE: Pin numbers may not correlate with symbols. Refer to Pin Assignment tables for pin number and symbol information.
PIN DESCRIPTIONS (continued)
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
82
SDA
Input/
Serial Presence-Detect Data: SDA is a bidirectional pin
Output
used to transfer addresses and data into and data out of the
presence-detect portion of the module.
83
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
165-167
SA0-SA2
Input
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
6, 18, 26, 40, 41, 49, 59,
V
DD
Supply
Power Supply: +3.3V 0.3V.
73, 84, 90, 102, 110, 124,
133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
V
SS
Supply
Ground.
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
24, 25, 31, 44, 48, 50, 51,
NC
Not Connected: These pins are not connected on these
61, 62, 63, 80, 81, 108,
modules.
109, 126
(256MB)
, 132,
134, 135, 145, 146, 164
79, 125, 163
DNU
Do Not Use: These pins are not connected on these modules
but are assigned pins on the compatible DRAM version.
5
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
FUNCTIONAL BLOCK DIAGRAM (STANDARD PCB)
A0
SA0
SPD
SDA
A1
SA1
A2
SA2
RAS#
CAS#
CKE0
CKE1
WE#
A0-A11 (256MB)
A0-A12 (512MB)
BA0
BA1
S0# - S3#
DQMB0-DQMB7
PLL CLK
RRAS#: SDRAMs U1-U9, U15-U23
RCAS#: SDRAMs U1-U9, U15-U23
RCKE0: SDRAMs U1-U9
RCKE1: SDRAMs U15-U23
RWE#: SDRAMs U1-U9, U15-U23
RA0-RA11 (256MB): SDRAMs U1-U9, U15-U23
RA0-RA12 (512MB): SDRAMs U1-U9, U15-U23
RBA0: SDRAMs U1-U9, U15-U23
RBA1: SDRAMs U1-U9, U15-U23
RS0# - RS3#
RDQMB0-RDQMB7
V
DD
V
SS
SDRAMs U1-U9, U15-U23
SDRAMs U1-U9, U15-U23
REGE
V
DD
10K
R
E
G
I
S
T
E
R
S
WP
PLL
SDRAM x 3
SDRAM x 3
SDRAM x 3
SDRAM x 3
SDRAM x 3
SDRAM x 3
REGISTER x 3
CK0
12pF
12pF
CK1-CK3
SCL
U1-U9, U15-U23 = MT48LC16M8A2TG SDRAMs for 256MB
U1-U9, U15-U23 = MT48LC32M8A2TG SDRAMs for 512MB
NOTE:
All resistor values are 10 ohms unless otherwise specified.
DQM CS#
U8
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RDQMB7
DQM CS#
U6
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
RDQMB6
DQM CS#
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
RDQMB5
DQM CS#
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
RDQMB4
DQM CS#
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
RDQMB3
DQM CS#
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
RDQMB2
DQM CS#
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
RDQMB1
DQM CS#
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RDQMB0
RS2#
RS0#
DQM CS#
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM CS#
U16
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQM CS#
U18
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQM CS#
U20
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQM CS#
U22
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RS1#
DQM CS#
U15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQM CS#
U17
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQM CS#
U21
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQM CS#
U23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQM CS#
U19
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RS3#
U13
U14
U10, U11, U24
U12
Per industry standard, Micron modules utilize various
component speed grades, as referenced in the Module
Part Numbering Guide at
www.micron.com/numberguide
.
6
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
A0
SA0
SPD
SDA
A1
SA1
A2
SA2
RAS#
CAS#
CKE0
WE#
A0-A11 (256MB)
A0-A12 (512MB)
RRAS#: SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
RCAS#: SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
RCKE0: SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
RWE#: SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
RA0-RA11 (256MB): SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
RA0-RA12 (512MB): SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
RBA0: SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
RBA1: SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
RS0# - RS3#
RDQMB0-RDQMB7
BA0
BA1
S0# - S3#
DQMB0-DQMB7
PLL CLK
V
DD
V
SS
SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
SDRAMs U1-U3, U5, 6, 9, 10, 13, 14
REGE
V
DD
10K
R
E
G
I
S
T
E
R
S
WP
PLL
SDRAM x 1
SDRAM x 2
SDRAM x 2
SDRAM x 2
SDRAM x 2
REGISTER x 2
CK0
12pF
12pF
CK1-CK3
SCL
47K
U1-U3, U5, 6, 9, 10, 13, 14 = MT48LC16M8A2TG SDRAMs for 256MB
U1-U3, U5, 6, 9, 10, 13, 14 = MT48LC32M8A2TG SDRAMs for 512MB
NOTE:
1. All resistor values are 10 ohms unless otherwise specified.
2. 'b' = bottom portion of stacked SDRAM, 't' = top portion of
stacked SDRAM.
DQM CS0
U9b
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RDQMB7
DQM CS0
U10b
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
RDQMB6
DQM CS0
U13b
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
RDQMB5
DQM CS0
U14b
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
RDQMB4
DQM CS0
U6b
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
RDQMB3
DQM CS0
U5b
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
RDQMB2
DQM CS0
U2b
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
RDQMB1
DQM CS0
U1b
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RDQMB0
RS2#
RS0#
DQM
U3b
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM CS1
U9t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS1
U10t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS1
U13t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS1
U14t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RS1#
DQM CS1
U6t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS1
U5t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS1
U2t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS1
U1t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
U3t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RS3#
U8
U7
U11, U12
U4
CS0
CS1
FUNCTIONAL BLOCK DIAGRAM (LOW PROFILE PCB)
7
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
GENERAL DESCRIPTION
The MT18LSDT3272D and MT18LSDT6472D are
high-speed CMOS, dynamic random-access, 256MB and
512MB memory modules organized in x72 (ECC) con-
figurations.
The SDRAM memory devices used for these mod-
ules are quad-bank DRAMs, that operate at 3.3V and
include a synchronous interface (all signals are regis-
tered on the positive edge of the clock signal, CK). The
four banks of a x8, 128Mb device (for the 256MB mod-
ules) are each configured as 4,096 bit-rows, by 1,024
bit-columns, by 8 input/output bits. The four banks of
a x8, 256Mb device (for the 512MB modules) are config-
ured as 8,192 bit-rows by 1,024 bit columns, by 8 input/
output bits.
Module read and write accesses are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ
or WRITE command. The address bits registered coin-
cident with the ACTIVE command are used to select
the device bank and row to be accessed. BA0 and BA1
select the device bank, A0-A11 (for 256MB module), or
A0-A12 (for 512MB module), select the device row. The
address bits A0-A9, registered coincident with the READ
or WRITE command are used to select the starting de-
vice column location for the burst access.
Prior to normal operation, the SDRAM must be ini-
tialized. The following sections provide detailed infor-
mation covering device initialization, register defini-
tion, command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V
DD
and V
DD
Q (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100s delay
prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this
100s period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
Once the 100s delay has been satisfied with at
least one COMMAND INHIBIT or NOP command hav-
ing been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
These modules use an internal pipelined architec-
ture to achieve high-speed operation. This architecture
is compatible with the 2n rule of prefetch architectures,
but it also allows the device column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one device bank while
accessing one of the other three device banks will hide
the PRECHARGE cycles and provide seamless, high-
speed, random-access operation.
These modules are designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM
operating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave be-
tween device banks in order to hide precharge time, and
the capability to randomly change device column ad-
dresses on each clock cycle during a burst access. For
more information regarding SDRAM operation, refer to
the 128Mb and 256Mb SDRAM data sheets.
PLL AND REGISTER OPERATION
These modules can be operated in either registered
mode (REGE pin HIGH), where the control/address input
signals are latched in the register on one rising clock edge
and sent to the SDRAM devices on the following rising
clock edge (data access is delayed by one clock), or in
buffered mode (REGE pin LOW) where the input signals
pass through the register/buffer to the SDRAM devices on
the same clock. A phase-lock loop (PLL) on the modules is
used to redrive the clock signals to the SDRAM devices to
minimize system clock loading (CK0 is connected to the
PLL).
8
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
SERIAL PRESENCE-DETECT OPERATION
These modules incorporate serial presence-detect
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the cus-
tomer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM's
SCL (clock) and SDA (data) signals, together with SA(2:0),
which provide eight unique DIMM/EEPROM addresses.
Mode Register Definition
Mode Register
The mode register is used to define the specific mode
of operation of the DRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
the Mode Register Definition Diagram. The mode reg-
ister is programmed via the LOAD MODE REGISTER
command and will retain the stored information until it
is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10 and M11 are reserved for future use.
For the 512MB module, A12 (M12) is undefined, but
should be driven LOW during loading of mode register
The mode register must be loaded when all device
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable,
as shown in the Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given READ
or WRITE command. Burst lengths of 1, 2, 4, or 8 loca-
tions are available for both the sequential and the in-
terleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached, as shown in the Burst Defini-
tion Table. The block is uniquely selected by A1-A9
when the burst length is set to two; A2-A9 when the
burst length is set to four; and by A3-A9 when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. Full-page bursts wrap within the
page if the boundary is reached, as shown in the Burst
Definition Table.
9
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
NOTE: 1. For full-page accesses: y = 1,024.
2. For a burst length of two, A1-A9 select the block-
of-two burst; A0 selects the starting column
within the block.
3. For a burst length of four,A2-A9 select the block-
of-four burst; A0-A1 select the starting column
within the block.
4. For a burst length of eight, A3-A9 select the
block-of-eight burst; A0-A2 select the starting
column within the block.
5. For a full-page burst, the full row is selected and
A0-A9 select the starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A9 select the unique
column to be accessed, and mode register bit M3
is ignored.
Burst Definition
Table
Burst
Starting Column
Order of Accesses Within a Burst
Length
Address
Type = Sequential Type = Interleaved
A0
2
0
0-1
0-1
1
1-0
1-0
A1 A0
0
0
0-1-2-3
0-1-2-3
4
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2 A1 A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
n = A0-A9
Cn, Cn + 1, Cn + 2
Page
Cn + 3, Cn + 4...
Not Supported
(y)
(location 0-y)
...Cn - 1,
Cn...
Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting col-
umn address, as shown in the Burst Definition Table.
Mode Register Definition
Diagram
Reserved*
Reserved*
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M6
0
0
0
1
1
1
1
M4
0
0
1
0
1
0
1
M5
0
1
1
0
0
1
1
Burst Length
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M3
M6-M0
M8
M7
Op Mode
A10
A11
10
11
12
WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M12, M11, M10 = "0, 0, 0"
to ensure compatibility
with future devices.
A12
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
Op Mode
A10
A11
10
11
Reserved* WB
*Should program
M11, M10 = "0, 0"
to ensure compatibility
with future devices.
256MB Module
512MB Module
10
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
Operating Mode
The normal operating mode is selected by setting M7
and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes.
The programmed burst length applies to both READ and
WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with fu-
ture versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to
READ bursts, but write accesses are single-location
(nonburst) accesses.
CAS Latency
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first piece of output data. The latency can be set to
two or three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency is
programmed to two clocks, the DQs will start driving
after T1 and the data will be valid by T2, as shown in the
CAS Latency Diagram. The CAS Latency Table indicate
the operating frequencies at which each CAS latency
setting can be used.
Reserved states should not be used as unknown op-
eration or incompatibility with future versions
may result.
CAS Latency Diagram
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON'T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
CAS Latency Table
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHz)
CAS
CAS
SPEED
LATENCY = 2*
LATENCY = 3*
-13E
133
143
-133
100
133
-10E
100
NA
*Input register will add one extra clock in registered mode.
11
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the Mode Register, and in the case of the 512MB module, A12 should be driven
low.
3. A0-A11 provide device row address for the 256MB module; A0-A12 for the 512MB module. BA0, BA1 determine which
device bank is made active.
4. A0-A9 provide device column address for 256MB and 512MB modules; A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being
read from or written to.
5. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both device banks are precharged
and BA0, BA1 are "Don't Care."
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
TRUTH TABLE SDRAM COMMANDS AND DQMB OPERATION
(Note: 1, notes appear below table)
NAME (FUNCTION)
CS# RAS# CAS# W E # D Q M B
ADDR
D Q
NOTES
COMMAND INHIBIT (NOP)
H
X
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
3
READ (Select bank and column, and start READ
L
H
L
H
L/H
8
Bank/Col
X
4
burst)
WRITE (Select bank and column, and start WRITE
L
H
L
L
L/H
8
Bank/Col
Valid
4
burst)
BURST TERMINATE
L
H
H
L
X
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
X
5
AUTO REFRESH or
L
L
L
H
X
X
X
6, 7
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
L
L
L
L
X
Op-Code
X
2
Write Enable/Output Enable
L
Active
8
Write Inhibit/Output High-Z
H
High-Z
8
Commands
The Truth Table provides a quick reference of avail-
able commands. This is followed by a written description
of each command. For a more detailed description of
commands and operations refer to 128Mb or 256Mb
SDRAM data sheets.
12
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply Relative to V
SS
.... -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to V
SS
.......................................... -1V to +4.6V
Operating Temperature, T
A
(ambient) .... 0C to +70C
Storage Temperature (plastic) ............. -55C to +150C
Power Dissipation ..................................................... 1 8 W
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6; notes appear following parameter tables); (V
DD
, V
DD
Q = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
M I N
M A X
UNITS NOTES
SUPPLY VOLTAGE
V
DD
, V
DD
Q
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
2
V
DD
+ 0.3
V
22
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-0.3
0.8
V
22
INPUT LEAKAGE CURRENT: Any input
Command and
0V
V
IN
V
DD
Address
I
I
-5
5
A
33
(All other pins not under test = 0V)
DQMB, S#, CKE
-2.5
2.5
CK
-5
-5
DQ
-10
10
OUTPUT LEAKAGE CURRENT: DQ pins are disabled;
I
OZ
-10
10
A
33
0V
V
OUT
V
DD
Q
OUTPUT LEVELS:
V
OH
2.4
V
Output High Voltage (I
OUT
= -4mA)
Output Low Voltage (I
OUT
= 4mA)
V
OL
0.4
V
13
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
I
DD
SPECIFICATIONS AND CONDITIONS* 256MB Module
(Notes: 1, 6, 11, 13; notes appear following parameter tables)
(V
DD
, V
DD
Q = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL -13E -133
-10E
UNITS NOTES
OPERATING CURRENT: Active Mode;
I
DD
1
a
1,458 1,368 1,278
mA
3, 18,
Burst = 2; READ or WRITE;
t
RC =
t
RC (MIN)
19, 30
STANDBY CURRENT: Power-Down Mode;
I
DD
2
b
36
36
36
mA
30
All device banks idle; CKE = LOW
STANDBY CURRENT: Active Mode;
I
DD
3
a
468
468
378
mA
3, 12,
CKE = HIGH; CS# = HIGH; All device banks active after
t
RCD met;
19, 30
No accesses in progress
OPERATING CURRENT: Burst Mode; Continuous burst;
I
DD
4
a
1,503 1,368 1,278
mA
3, 18,
READ or WRITE; All device banks active
19, 30
AUTO REFRESH CURRENT
t
RFC =
t
RFC (MIN)
I
DD
5
b
5,940 5,580 4,860
mA
3, 12,
CS# = HIGH; CKE = HIGH
t
RFC = 15.6s
I
DD
6
b
54
54
54
mA
18, 19,
30, 31
SELF REFRESH CURRENT: CKE
0.2V
I
DD
7
b
36
36
36
mA
4
MAX
I
DD
SPECIFICATIONS AND CONDITIONS* 512MB Module
(Notes: 1, 6, 11, 13; notes appear following parameter tables)
(V
DD
, V
DD
Q = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL -13E -133 -10E
UNITS NOTES
OPERATING CURRENT: Active Mode;
I
DD
1
a
1,233 1,143 1,143
mA
3, 18,
Burst = 2; READ or WRITE;
t
RC =
t
RC (MIN)
19, 30
STANDBY CURRENT: Power-Down Mode;
I
DD
2
b
36
36
36
mA
30
All device banks idle; CKE = LOW
STANDBY CURRENT: Active Mode;
I
DD
3
a
378
378
378
mA
3, 12,
CKE = HIGH; CS# = HIGH; All device banks active after
t
RCD met;
19, 30
No accesses in progress
OPERATING CURRENT: Burst Mode; Continuous burst;
I
DD
4
a
1,233 1,233 1,233
mA
3, 18,
READ or WRITE; All device banks active
19, 30
AUTO REFRESH CURRENT
t
RFC =
t
RFC (MIN)
I
DD
5
b
5,130 4,860 4,860
mA
3, 12,
CS# = HIGH; CKE = HIGH
t
RFC = 7.81 s
I
DD
6
b
63
63
63
mA
18, 19,
30, 31
SELF REFRESH CURRENT: CKE
0.2V
I
DD
7
b
45
45
45
mA
4
MAX
*DRAM components only.
a - Value calculated as one module bank in this operating condition, and all other banks in Power-Down Mode.
b - Value calculated reflects all module banks in this operating condition.
14
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
CAPACITANCE
(Note: 2; notes appear following parameter tables)
PARAMETER
SYMBOL
MIN
TYP
MAX UNITS
Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#,WE#
C
I
1
-
8
-
pF
Input Capacitance: S0#-S3#, CKE0, DQMB0#-DQMB7#
C
I
2
-
4
-
p F
Input Capacitance: CK0
C
I
3
-
16
-
p F
Input/Output Capacitance: SCL, SA0-SA2, WP, SDA
C
I
4
-
-
10
p F
Input/Output Capacitance: DQ0-DQ63, CB0-CB7
C
I
O
8
-
12
p F
*Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS*
(Notes: 5, 6, 8, 9, 11; notes appear following parameter tables)
AC CHARACTERISTICS
-13E
-133
-10E
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from
CL = 3
t
AC(3)
5.4
5.4
6
ns
27
CLK (pos. edge)
CL = 2
t
AC(2)
5.4
6
6
ns
Address hold time
t
AH
0.8
0.8
1
ns
Address setup time
t
AS
1.5
1.5
2
ns
CLK high-level width
t
CH
2.5
2.5
3
ns
CLK low-level width
t
CL
2.5
2.5
3
ns
Clock cycle time
CL = 3
t
CK(3)
7
7.5
8
ns
23
CL = 2
t
CK(2)
7.5
10
10
ns
23
CKE hold time
t
CKH
0.8
0.8
1
ns
CKE setup time
t
CKS
1.5
1.5
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
t
CMH
0.8
0.8
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
t
CMS
1.5
1.5
2
ns
Data-in hold time
t
DH
0.8
0.8
1
ns
Data-in setup time
t
DS
1.5
1.5
2
ns
Data-out high-impedance
CL = 3
t
HZ(3)
5.4
5.4
6
ns
10
time
CL = 2
t
HZ(2)
5.4
6
6
ns
10
Data-out low-impedance time
t
LZ
1
1
1
ns
Data-out hold time (load)
t
OH
3
3
3
ns
Data-out hold time (no load)
t
OH
N
1.8
1.8
1.8
ns
28
ACTIVE to PRECHARGE command
t
RAS
37
120,000
44
120,000
50
120,000
ns
29
ACTIVE to ACTIVE command period
t
RC
60
66
70
ns
ACTIVE to READ or WRITE delay
t
RCD
15
20
20
ns
Refresh period
t
REF
64
64
64
ms
AUTO REFRESH period
t
RFC
66
66
70
ns
PRECHARGE command period
t
RP
15
20
20
ns
ACTIVE bank a to ACTIVE bank b command
t
RRD
14
15
20
ns
Transition time
t
T
0.3
1.2
0.3
1.2
0.3
1.2
ns
7
WRITE recovery time
t
WR
1 CLK +
1 CLK +
1 CLK +
ns
24
7ns
7.5ns
7ns
14
15
15
ns
25
Exit SELF REFRESH to ACTIVE command
t
XSR
67
75
80
ns
20
15
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear following parameter tables)
PARAMETER
SYMBOL -13E
-133
-10E UNITS NOTES
READ/WRITE command to READ/WRITE command
t
CCD
1
1
1
t
CK
17
CKE to clock disable or power-down entry mode
t
CKED
1
1
1
t
CK
14, 32
CKE to clock enable or power-down exit setup mode
t
PED
1
1
1
t
CK
14, 32
DQM to input data delay
t
DQD
0
0
0
t
CK
17,
32
DQM to data mask during WRITEs
t
DQM
0
0
0
t
CK
17, 32
DQM to data high-impedance during READs
t
DQZ
2
2
2
t
CK
17, 32
WRITE command to input data delay
t
DWD
0
0
0
t
CK
17, 32
Data-in to ACTIVE command
t
DAL
4
5
4
t
CK
15, 21,
32
Data-in to PRECHARGE command
t
DPL
2
2
2
t
CK
16, 21,
32
Last data-in to burst STOP command
t
BDL
1
1
1
t
CK
17, 32
Last data-in to new READ/WRITE command
t
CDL
1
1
1
t
CK
17, 32
Last data-in to PRECHARGE command
t
RDL
2
2
2
t
CK
16, 21,
32
LOAD MODE REGISTER command to ACTIVE or REFRESH command
t
MRD
2
2
2
t
CK
26
Data-out to high-impedance from PRECHARGE command
CL = 3
t
ROH(3)
3
3
3
t
CK
17, 32
CL = 2
t
ROH(2)
2
2
2
t
CK
17, 32
16
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
DD
, V
DD
Q = +3.3V;
f = 1 MHz, T
A
= 25C; pin under test biased at 1.4V.
3.
I
DD
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured; (0C
T
A
+70C).
6.
An initial pause of 100s is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (V
DD
and V
DD
Q
must be powered up simultaneously. V
SS
and V
SS
Q
must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time
the
t
REF refresh requirement is exceeded.
7.
AC characteristics assume
t
T = 1ns.
8.
In addition to meeting the transition rate specifica-
tion, the clock and CKE must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
9.
Outputs measured at 1.5V with equivalent load:
10.
t
HZ defines the time at which the output achieves the
open circuit condition; it is not a reference to V
OH
or
V
OL
. The last valid data element will meet
t
OH before
going High-Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V,
with timing referenced to 1.5V crossover point. If the
input transition time is longer than 1 ns, then the
timing is referenced at V
IL
(MAX) and V
IH
(MIN) and
no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no more
than once every two clocks and are otherwise at valid
V
IH
or V
IL
levels.
13. I
DD
specifications are tested after the device is prop-
erly initialized.
14. Timing actually specified by
t
CKS; clock(s) specified
as a reference only at minimum cycle rate.
15. Timing actually specified by
t
WR plus
t
RP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by
t
WR.
17. Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The I
DD
current will increase or decrease propor-
tionally according to the amount of frequency alter-
ation for the test condition.
19. Address transitions average one transition every two
clocks.
20. CLK must be toggled a minimum of two times during
this period.
21. Based on
t
CK = 10ns for -10E, and
t
CK = 7.5ns for -133
and -13E.
22. V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 2V for a pulse
width
3ns, and the pulse width cannot be greater
than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access
or precharge states (READ, WRITE, including
t
WR,
and PRECHARGE commands). CKE may be used to
reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (
t
RP) begins 7ns for -13E; 7.5ns for -133 and
7ns for -10E after the first clock delay, after the last
WRITE is executed. May not exceed limit set for
precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
t
AC for -133/-13E at CL = 3 with no load is 4.6ns and
is guaranteed by design.
28. Parameter guaranteed by design.
29. The value of
t
RAS. use in -13E speed grade module
SPDs is calculated from
t
RC -
t
RP = 45ns.
30. For -10E, CL= 2 and
t
CK = 10ns; for -133, CL = 3 and
t
CK = 7.5ns; for -13E, CL = 2 and
t
CK = 7.5ns.
31. CKE is HIGH during refresh command period
t
RFC (MIN) else CKE is LOW. The I
DD
6 limit is actu-
ally a nominal value and does not result in a fail
value.
32. This AC timing function will show an extra clock
cycle when input register is in registered mode.
33. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
Q
50pF
17
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions
(Figures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL is
HIGH. The SPD device continuously monitors the SDA
and SCL lines for the start condition and will
not respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place the
SPD device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after transmit-
ting eight bits. During the ninth clock cycle, the receiver
will pull the SDA line LOW to acknowledge that it re-
ceived the eight bits of data (Figure 3).
The SPD device will always respond with an acknowl-
edge after recognition of a start condition and its slave
address. If both the device and a WRITE operation have
been selected, the SPD device will respond with an ac-
knowledge after the receipt of each subsequent eight-bit
word. In the read mode the SPD device will transmit eight
bits of data, release the SDA line and monitor the line for
an acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the slave will
continue to transmit data. If an acknowledge is not de-
tected, the slave will terminate further data transmis-
sions and await the stop condition to return to standby
power mode.
SCL
SDA
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 1
Data Validity
SCL
SDA
START
BIT
STOP
BIT
Figure 2
Definition of Start and Stop
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
9
8
Acknowledge
Figure 3
Acknowledge Response From Receiver
18
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
SCL
SDA IN
SDA OUT
tLOW
tSU:STA
tHD:STA
tF
tHIGH
tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
SPD EEPROM TIMING DIAGRAM
SYMBOL
MIN
MAX
UNITS
t
AA
0.3
3.5
s
t
BUF
4.7
s
t
DH
300
ns
t
F
300
ns
t
HD:DAT
0
s
t
HD:STA
4
s
SYMBOL
MIN
MAX
UNITS
t
HIGH
4
s
t
LOW
4.7
s
t
R
1
s
t
SU:DAT
250
ns
t
SU:STA
4.7
s
t
SU:STO
4.7
s
SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS
EEPROM DEVICE SELECT CODE
Note: The most significant bit (b7) is sent first.
DEVICE TYPE IDENTIFIER
CHIP ENABLE
RW
b7
b6
b5
b4
b3
b2
b1
b0
Memory Area Select Code (two arrays)
1
0
1
0
E2
E1
E0
RW
Protection Register Select Code
0
1
1
0
E2
E1
E0
RW
EEPROM OPERATING MODES
MODE
RW BIT
WC
1
BYTES
INITIAL SEQUENCE
Current Address Read
1
X
1
START, Device Select, RW = `1'
Random Address Read
0
X
1
START, Device Select, RW = `0', Address
1
X
1
reSTART, Device Select, RW = `1'
Sequential Read
1
X




1
Similar to Current or Random Address Read
Byte Write
0
V
IL
1
START, Device Select, RW = `0'
Page Write
0
V
IL
16
START, Device Select, RW = `0'
NOTE: 1. X = V
IH
or V
IL
.
19
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS
(Note: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
SUPPLY VOLTAGE
V
DD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
V
DD
x 0.7 V
DD
+ 0.5
V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-1
V
DD
x 0.3
V
OUTPUT LOW VOLTAGE: I
OUT
= 3mA
V
OL
0.4
V
INPUT LEAKAGE CURRENT: V
IN
= GND to V
DD
I
LI
10
A
OUTPUT LEAKAGE CURRENT: V
OUT
= GND to V
DD
I
LO
10
A
STANDBY CURRENT:
I
SB
30
A
SCL = SDA = V
DD
- 0.3V; All other inputs = GND or 3.3V +10%
POWER SUPPLY CURRENT:
I
DD
2
mA
SCL clock frequency = 100 KHz
SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS
(Note: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SCL LOW to SDA data-out valid
t
AA
0.3
3.5
s
Time the bus must be free before a new transition can start
t
BUF
4.7
s
Data-out hold time
t
DH
300
ns
SDA and SCL fall time
t
F
300
ns
Data-in hold time
t
HD:DAT
0
s
Start condition hold time
t
HD:STA
4
s
Clock HIGH period
t
HIGH
4
s
Noise suppression time constant at SCL, SDA inputs
t
I
100
ns
Clock LOW period
t
LOW
4.7
s
SDA and SCL rise time
t
R
1
s
SCL clock frequency
t
SCL
100
KHz
Data-in setup time
t
SU:DAT
250
ns
Start condition setup time
t
SU:STA
4.7
s
Stop condition setup time
t
SU:STO
4.7
s
WRITE cycle time
t
WRC
10
ms
2
NOTE: 1. All voltages referenced to V
SS
.
2. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
20
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
2. The value of
t
RAS used for the -13E module is calculated from
t
RC -
t
RP. Actual device spec. vaule is 37ns.
SERIAL PRESENCE-DETECT MATRIX
(Note: 1)
BYTE
DESCRIPTION
ENTRY (VERSION)
MT18LSDT3272D
MT18LSDT6472D
0
NUMBER OF BYTES USED BY MICRON
128
80
80
1
TOTAL NUMBER OF SPD MEMORY BYTES
256
08
08
2
MEMORY TYPE
SDRAM
04
04
3
NUMBER OF ROW ADDRESSES
12 or 13
0C
0D
4
NUMBER OF COLUMN ADDRESSES
10
0A
0A
5
NUMBER OF BANKS
2
02
02
6
MODULE DATA WIDTH
72
48
48
7
MODULE DATA WIDTH (continued)
0
00
00
8
MODULE VOLTAGE INTERFACE LEVELS
LVTTL
01
01
9
SDRAM CYCLE TIME,
t
CK
7 (-13E)
70
70
(CAS LATENCY = 3)7.5 (-133)
75
75
8 (-10E)
80
80
10
SDRAM ACCESS FROM CLOCK,
t
AC
5.4 (-13E/-133)
54
54
(CAS LATENCY = 3)6 (-10E)
60
60
11
MODULE CONFIGURATION TYPE
ECC
02
02
12
REFRESH RATE/TYPE
15.6s or 7.81s/SELF
80
82
13
SDRAM WIDTH (PRIMARY SDRAM)
8
08
08
14
ERROR-CHECKING SDRAM DATA WIDTH
8
08
08
15
MIN. CLOCK DELAY FROM BACK-TO-BACK
1
01
01
RANDOM COLUMN ADDRESSES,
t
CCD
16
BURST LENGTHS SUPPORTED
1, 2, 4, 8, PAGE
8F
8F
17
NUMBER OF BANKS ON SDRAM DEVICE
4
04
04
18
CAS LATENCIES SUPPORTED
2, 3
06
06
19
CS LATENCY
0
01
01
20
WE LATENCY
0
01
01
21
SDRAM MODULE ATTRIBUTES
1F
1F
22
SDRAM DEVICE ATTRIBUTES: GENERAL
0E
0E
0E
23
SDRAM CYCLE TIME,
t
CK
7.5 (-13E)
75
75
(CAS LATENCY = 2)
10 (-133/-10E)
A0
A0
24
SDRAM ACCESS FROM CLK,
t
AC
5.4 (-13E)
54
54
(CAS LATENCY = 2)
6 (-133/-10E)
60
60
25
SDRAM CYCLE TIME,
t
CK
00
00
(CAS LATENCY = 1)
26
SDRAM ACCESS FROM CLK,
t
AC
00
00
(CAS LATENCY = 1)
27
MINIMUM ROW PRECHARGE TIME,
t
RP
15 (-13E)
0F
0F
20 (-133/-10E)
14
14
28
MINIMUM ROW ACTIVE TO ROW ACTIVE,
14 (-13E)
0E
0E
t
RRD
15 (-133)
0F
0F
20 (-10E)
14
14
29
MINIMUM RAS# TO CAS# DELAY,
t
RCD
15 (-13E)
0F
0F
20 (-133/-13E)
14
14
30
MINIMUM RAS# PULSE WIDTH,
t
RAS
45 (-13E)
2D
2D
(Note: 2)
44 (-133)
2C
2C
50 (-10E)
32
32
31
MODULE BANK DENSITY
128MB or 256MB
20
40
21
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
SERIAL PRESENCE-DETECT MATRIX (continued)
(Notes: 1, 2)
BYTE
DESCRIPTION
ENTRY (VERSION)
MT18LSDT3272D
MT18LSDT6472D
32
COMMAND AND ADDRESS SETUP TIME,
1.5 (-13E/-133)
15
15
t
AS,
t
CMS
2 (-10E)
20
20
33
COMMAND AND ADDRESS HOLD TIME,
0.8 (-13E/-133)
08
08
t
AH,
t
CMH
1 (-10E)
10
10
34
DATA SIGNAL INPUT SETUP TIME,
t
DS
1.5 (-13E/-133)
15
15
2 (-10E)
20
20
35
DATA SIGNAL INPUT HOLD TIME,
t
DH
0.8 (-13E/-133)
08
08
1 (-10E)
10
10
36-61
RESERVED
00
00
62
SPD REVISION
REV. 1.2
12
12
63
CHECKSUM FOR BYTES 0-62
-13E
9A
BD
-133
E0
03
-10E
28
4B
64
MANUFACTURER'S JEDEC ID CODE
MICRON
2C
2C
65-71
MANUFACTURER'S JEDEC ID (CONT.)
FF
FF
72
MANUFACTURING LOCATION
1 - 11
01
0B
73-90
MODULE PART NUMBER (ASCII)
xx
xx
91
PCB IDENTIFICATION CODE
1 - 9
01
09
92
IDENTIFICATION CODE (CONT.)
0
00
00
93
YEAR OF MANUFACTURE IN BCD
xx
xx
94
WEEK OF MANUFACTURE IN BCD
xx
xx
95-98
MODULE SERIAL NUMBER
xx
xx
99-125
MANUFACTURER-SPECIFIC DATA (RSVD)
126
SYSTEM FREQUENCY
100 MHz/133 MHz
64
64
127
SDRAM COMPONENT AND CLOCK DETAIL
8F
8F
NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
2. x = Variable Data.
22
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
168-PIN DIMM DIMENSIONS (STANDARD PCB)
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
1.705 (43.31)
1.695 (43.05)
.128 (3.25)
.118 (3.00)
(2X)
PIN 1
.700 (17.78)
TYP.
.118 (3.00)
(2X)
.118 (3.00) TYP.
.250 (6.35) TYP.
4.550 (115.57)
.050 (1.27)
TYP.
.118 (3.00)
TYP.
.040 (1.02)
TYP.
.079 (2.00) R
(2X)
.039 (1.00) R(2X)
PIN 84
FRONT VIEW
BACK VIEW
PIN 168
PIN 85
2.625 (66.68)
1.661 (42.18)
.054 (1.37)
.046 (1.17)
5.256 (133.50)
5.244 (133.20)
.157 (4.00)
MAX
23
32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD18C32_64x72DG_C.p65Rev. C; Pub. 1/03
2002, Micron Technology, Inc.
256MB / 512MB (x72, ECC)
168-PIN REGISTERED SDRAM DIMM
168-PIN DIMM DIMENSIONS (LOW-PROFILE PCB, STACKED)
FRONT VIEW
BACK VIEW
5.256 (133.50)
5.244 (133.20)
.320 (8.13)
MAX
.700 (17.78)
1.131 (28.73)
1.119(28.42)
PIN 1
.250 (6.35)
4.550 (115.57)
.050 (1.27)
.040 (1.02)
.039 (1.00) R(2X)
PIN 84
.118 (3.00)
.118 (3.00)
.079 (2.00) R
(2X)
.118 (3.00)
(2X)
PIN 168
PIN 85
2.625 (66.68)
1.661 (42.18)
.128 (3.25)
.118 (3.00)
(2X)
.054 (1.37)
.046 (1.17)
U1
U2
U3
U5
U4
U6
U7
U9
U10
U11
U12
U13
U14
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