PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
32, 64 Meg x 72 DDR SDRAM DIMMs
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
1
2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
REGISTEREDDDR
SDRAM DIMM
MT18VDDF3272 256MB
MT18VDDF6472 512MB
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/moduleds
Features
184-pin, dual in-line memory module (DIMM)
Fast data transfer rates PC1600, PC2100, or PC2700
Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR
SDRAM components
Registered Inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
ECC, 1-bit error detection and correction
256MB (32 Meg x 72) and 512MB (64 Meg x 72)
V
DD
= V
DD
Q = +2.5V
V
DDSPD
= +2.3V to +3.6V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/received
with data--i.e., source-synchronous data capture
Differential clock inputs CK and CK#
Four internal device banks for concurrent operation
Programmable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
15.625s (256MB), 7.8125s (512MB) maximum
average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Programmable READ CAS latency
Figure 1: 184-Pin DIMM MO-206
NOTE:
1. Registered Mode will add one clock cycle to CL.
OPTIONS
MARKING
Package
184-pin DIMM (gold)
G
Frequency/CAS Latency
1
6ns/166MHz,(333MT/s)
CL = 2.5
-335
7.5ns/133 MHz (266 MT/s) CL = 2
-262
7.5ns/133 MHz (266 MT/s) CL = 2
-26A
7.5ns/133 MHz (266 MT/s) CL = 2.5
-265
10ns/100 MHz (200 MT/s) CL = 2
-202
Table 1:
Address Table
256MB
512MB
Refresh Count
4K
8K
Row Addressing
4K (A0A11)
8K (A0A12)
Device Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
Device Configuration
32 Meg x 4
64 Meg x 4
Column Addressing
2K (A0A9, A11) 2K (A0A9, A11)
Module Rank Addressing
1 (S0#)
1 (S0#)
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
2
2003 Micron Technology, Inc. All rights reserved.
Table 2:
Part Numbers and Timing Parameters
PART NUMBER
MODULE
DENSITY
CONFIGURATION
MODULE
BANDWIDTH
MEMORY CLOCK/
DATA BIT RATE
LATENCY
(CL -
t
RCD -
t
RP)
MT18VDDF3272G-335__
256MB
32 Meg x 72
2.7 GB/s
6ns/333 MT/s
2.5-3-3
MT18VDDF3272Y-335__
256MB
32 Meg x 72
2.7 GB/s
6ns/333 MT/s
2.5-3-3
MT18VDDF3272G-26A__
256MB
32 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2-2-2
MT18VDDF3272Y-26A__
256MB
32 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2-2-2
MT18VDDF3272G-26A__
256MB
32 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2-3-3
MT18VDDF3272Y-26A__
256MB
32 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2-3-3
MT18VDDF3272G-265__
256MB
32 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2.5-3-3
MT18VDDF3272Y-265__
256MB
32 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2.5-3-3
MT18VDDF3272G-202__
256MB
32 Meg x 72
1.6 GB/s
10ns/200 MT/s
2-2-2
MT18VDDF3272Y-202__
256MB
32 Meg x 72
1.6 GB/s
10ns/200 MT/s
2-2-2
MT18VDDF6472G-335__
512MB
64 Meg x 72
2.7 GB/s
6ns/333 MT/s
2.5-3-3
MT18VDDF6472Y-335__
512MB
64 Meg x 72
2.7 GB/s
6ns/333 MT/s
2.5-3-3
MT18VDDF6472G-262__
512MB
64 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2-2-2
MT18VDDF6472Y-262__
512MB
64 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2-2-2
MT18VDDF6472G-26A__
512MB
64 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2-3-3
MT18VDDF6472Y-26A__
512MB
64 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2-3-3
MT18VDDF6472G-265__
512MB
64 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2.5-3-3
MT18VDDF6472Y-265__
512MB
64 Meg x 72
2.1 GB/s
7.5ns/266 MT/s
2.5-3-3
MT18VDDF6472G-202__
512MB
64 Meg x 72
1.6 GB/s
10ns/200 MT/s
2-2-2
MT18VDDF6472Y-202__
512MB
64 Meg x 72
1.6 GB/s
10ns/200 MT/s
2-2-2
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT18VDDF3272G-265B1.
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
3
2003 Micron Technology, Inc. All rights reserved.
NOTE:
Pin 115 is a No Connect for 256MB modules, or A12 for 512MB modules.
Figure 2: Pin Locations
Table 3:
Pin Assignment
(184-Pin DIMM Front)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
V
REF
24
DQ17
47
DQS8
70
V
DD
2
DQ0
25
DQS2
48
A0
71
NC
3
V
SS
26
V
SS
49
CB2
72
DQ48
4
DQ1
27
A9
50
V
SS
73
DQ49
5
DQS0
28
DQ18
51
CB3
74
V
SS
6
DQ2
29
A7
52
BA1
75
NC
7
V
DD
30
V
DD
Q
53
DQ32
76
NC
8
DQ3
31
DQ19
54
V
DD
Q
77
V
DD
Q
9
NC
32
A5
55
DQ33
78
DQS6
10
RESET#
33
DQ24
56
DQS4
79
DQ50
11
V
SS
34
V
SS
57
DQ34
80
DQ51
12
DQ8
35
DQ25
58
V
SS
81
V
SS
13
DQ9
36
DQS3
59
BA0
82
NC
14
DQS1
37
A4
60
DQ35
83
DQ56
15
V
DD
Q
38
V
DD
61
DQ40
84
DQ57
16
NC
39
DQ26
62
V
DD
Q
85
V
DD
17
NC
40
DQ27
63
WE#
86
DQS7
18
V
SS
41
A2
64
DQ41
87
DQ58
19
DQ10
42
V
SS
65
CAS#
88
DQ59
20
DQ11
43
A1
66
V
SS
89
V
SS
21
CKE0
44
CB0
67
DQS5
90
NC
22
V
DD
Q
45
CB1
68
DQ42
91
SDA
23
DQ16
46
V
DD
69
DQ43
92
SCL
Table 4:
Pin Assignment
(184-Pin DIMM Back)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
93
V
SS
116
V
SS
139
V
SS
162
DQ47
94
DQ4
117
DQ21
140
DQS17
163
NC
95
DQ5
118
A11
141
A10
164
V
DD
Q
96
V
DD
Q
119
DQS11
142
CB6
165
DQ52
97
DQS9
120
V
DD
143
V
DD
Q
166
DQ53
98
DQ6
121
DQ22
144
CB7
167
NC
99
DQ7
122
A8
145
V
SS
168
V
DD
100
V
SS
123
DQ23
146
DQ36
169
DQS15
101
NC
124
V
SS
147
DQ37
170
DQ54
102
NC
125
A6
148
V
DD
171
DQ55
103
NC
126
DQ28
149
DQS13
172
V
DD
Q
104
V
DD
Q
127
DQ29
150
DQ38
173
NC
105
DQ12
128
V
DD
Q
151
DQ39
174
DQ60
106
DQ13
129
DQS12
152
V
SS
175
DQ61
107
DQS10
130
A3
153
DQ44
176
V
SS
108
V
DD
131
DQ30
154
RAS#
177
DQS16
109
DQ14
132
V
SS
155
DQ45
178
DQ62
110
DQ15
133
DQ31
156
V
DD
Q
179
DQ63
111
NC
134
CB4
157
S0#
180
V
DD
Q
112
V
DD
Q
135
CB5
158
NC
181
SA0
113
NC
136
V
DD
Q
159
DQS14
182
SA1
114
DQ20
137
CK0
160
V
SS
183
SA2
115 NC/
A12
138
CK0#
161
DQ46
184
V
DDSPD
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
PIN 93
PIN 144
PIN 145
PIN 184
PIN 1
PIN 52
PIN 53
PIN 92
Indicates a V
DD
pin
Indicates a V
SS
pin
Front View
Back View
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
4
2003 Micron Technology, Inc. All rights reserved.
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information.
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
1
V
REF
Input
SSTL_2 reference voltage.
63, 65, 154
WE#, CAS#, RAS#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S0#) define
the command being entered.
137, 138
CK0, CK0#
Input
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQ and
DQS) is referenced to the crossings of CK and CK#.
21
CKE0
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank).CKE is synchronous for POWER-
DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
DD
is applied.
157
S0#
Input
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.
52, 59
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
27, 29, 32, 37, 41, 43, 48,
115
(
512MB
),
118, 122,
125, 130, 141
A0-A11
(256MB)
A0-A12
(512MB)
Input
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode
register or extended mode register) is loaded during the LOAD
MODE REGISTER command.
5, 14, 25, 36, 47, 56, 67,
78, 86, 97, 107, 119, 129,
140, 149, 159, 169, 177
DQS0-DQS17
Input/
Output
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
44, 45, 49, 51, 134, 135,
142, 144
CB0-CB7
Input/
Output
Check Bits: ECC, 1-bit error detection and correction.
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
5
2003 Micron Technology, Inc. All rights reserved.
2, 4, 6, 8, 12,13, 19, 20,
23, 24, 28, 31, 33, 35, 39,
40, 53, 55, 57, 60, 61, 64,
68, 69, 72, 73, 79, 80, 83,
84, 87, 88, 94, 95, 98, 99,
105, 106, 109, 110, 114,
117, 121, 123, 126, 127,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
DQ0-DQ63
Input/
Output
Data I/Os: Data bus.
92
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
181, 182, 183
SA0-SA2
Input
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
91
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
15, 22, 30, 54, 62, 77, 96,
104, 112, 128, 136, 143,
156, 164, 172, 180
V
DD
Q
Supply
DQ Power Supply: +2.5V 0.2V.
7, 38, 46, 70, 85, 108,
120, 148, 168
V
DD
Supply
Power Supply: +2.5V 0.2V.
3, 11, 18, 26, 34, 42, 50,
58, 66, 74, 81, 89, 93, 100,
116, 124, 132, 139, 145,
152, 160, 176
V
SS
Supply
Ground.
184
V
DDSPD
Supply
Serial EEPROM positive power supply: +2.3V to +3.6V.
9, 16, 17, 71, 75, 76, 82,
90, 101, 102, 103, 111,
113, 115 (
256MB
),158,
163, 167, 173
NC
--
No Connect: These pins should be left unconnected.
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information.
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
6
2003 Micron Technology, Inc. All rights reserved.
Figure 3: Functional Block Diagram
U1
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQS CS# DM
U22
DQ
DQ
DQ
DQ
DQ60
DQ61
DQ62
DQ63
DQS CS# DM
U2
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQS CS# DM
U21
DQ
DQ
DQ
DQ
DQ52
DQ53
DQ54
DQ55
DQS CS# DM
U3
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQS CS# DM
U20
DQ
DQ
DQ
DQ
DQ44
DQ45
DQ46
DQ47
DQS CS# DM
U4
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQS CS# DM
U19
DQ
DQ
DQ
DQ
DQ36
DQ37
DQ38
DQ39
DQS CS# DM
U5
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
DQS CS# DM
U18
DQ
DQ
DQ
DQ
CB4
CB5
CB6
CB7
DQS CS# DM
U8
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQS CS# DM
U15
DQ
DQ
DQ
DQ
DQ28
DQ29
DQ30
DQ31
DQS CS# DM
U9
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQS CS# DM
U14
DQ
DQ
DQ
DQ
DQ20
DQ21
DQ22
DQ23
DQS CS# DM
U10
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQS CS# DM
U13
DQ
DQ
DQ
DQ
DQ12
DQ13
DQ14
DQ15
DQS CS# DM
U11
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQS CS# DM
U12
DQ
DQ
DQ
DQ
DQ4
DQ5
DQ6
DQ7
PLL
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
REGISTER X 2
CK0
CK0#
DQS CS# DM
DQS0
A0
SA0
SERIAL PD
SDA
A1
SA1
A2
SA2
S0 #
BA0, BA1
A0-A11 (256MB Modules)
A0-A12 (512MB Modules)
RAS#
CAS#
CKE0
WE#
RS0#: DDR SDRAMs
RBA0, RBA1: DDR SDRAMs
RA0-RA11: DDR SDRAMs
RA0-RA12: DDR SDRAMs
RRAS#: DDR SDRAMs
RCAS#: DDR SDRAMs
RCKE0: DDR SDRAMs
RWE#: DDR SDRAMs
R
E
G
I
S
T
E
R
S
WP
SCL
MT46V32M4FJ = DDR SDRAMs for 256MB modules
MT46V64M4FJ = DDR SDRAMs for 512MB modules
DQS1
DQS2
DQS3
DQS8
DQS4
DQS6
DQS7
DQS5
DQS9
DQS10
DQS11
DQS12
DQS17
DQS13
DQS14
DQS15
DQS16
CK
CK#
RESET#
RS0#
V
SS
U17
U6
U7, U16
120
120
V
REF
V
SS
DDR SDRAMs
DDR SDRAMs
V
DDQ
V
DD
DDR SDRAMs
DDR SDRAMs
V
DDSPD
SPD
NOTE:
1. All resistor values are 22
W unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part
Numbering Guide at
www.micron.com/numberguide
.
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
7
2003 Micron Technology, Inc. All rights reserved.
General Description
The MT18VDDF3272 and MT18VDDF6472 are high-
speed CMOS, dynamic random-access, 256MB and
512MB memory modules organized in x72 (ECC) con-
figuration. These modules use internally configured
quad-bank DDR SDRAMs.
These DDR SDRAM modules use a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the DDR SDRAM mod-
ule effectively consists of a single 2n-bit wide, one-
clock-cycle data transfer at the internal DRAM core
and two corresponding n-bit wide, one-half-clock-
cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
These DDR SDRAM modules operate from differen-
tial clock inputs (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as
the positive edge of CK. Commands (address and con-
trol signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.
Read and write accesses to the DDR SDRAM mod-
ules are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is
then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE
command are used to select the device bank and row
to be accessed (BA0, BA1 select device bank; A0A11
select device row for 256MB modules , A0A12 select
device row for 512MB modules). The address bits reg-
istered coincident with the READ or WRITE command
are used to select the device bank and starting device
column location for the burst access (BA0, BA1; A0A9,
A11).
These DDR SDRAM modules provide for program-
mable READ or WRITE burst lengths of 2, 4, or 8 loca-
tions. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at
the end of the burst access.
The pipelined, multibank architecture of DDR
SDRAM modules allows for concurrent operation,
thereby providing effective high bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb and 256Mb DDR SDRAM component data
sheets.
PLL and Register Operation
These DDR SDRAM modules operate in registered
mode, where the command/address input signals are
latched in the registers on the rising clock edge and
sent to the DDR SDRAM devices on the following ris-
ing clock edge (data access is delayed by one clock
cycle). A phase-lock loop (PLL), on the module,
receives and redrives the differential clock signals (CK,
CK#) to the DDR SDRAM devices. The registers and
PLL minimize system and clock loading.
Serial Presence-Detect Operation
These DDR SDRAM modules incorporate serial
presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile
storage device contains 256 bytes. The first 128 bytes
can be programmed by Micron to identify the module
type and various SDRAM organizations and timing
parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/
WRITE operations between the master (system logic)
and the slave EEPROM device (DIMM) occur via a
standard I
2
C bus using the DIMM's SCL (clock) and
SDA (data) signals, together with SA (2:0), which pro-
vide eight unique DIMM/EEPROM addresses.
Mode Register Definition
The mode register is used to define the specific
mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in the
Mode Register Diagram. The mode register is pro-
grammed via the MODE REGISTER SET command
(with BA0 = 0 and BA1 = 0) and will retain the stored
information until it is programmed again or the device
loses power (except for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
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DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
8
2003 Micron Technology, Inc. All rights reserved.
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
Mode register bits A0A2 specify the burst length,
A3 specifies the type of burst (sequential or inter-
leaved), A4A6 specify the CAS latency, and A7A11
(for 256MB modules ) or A7A12 (for 512MB modules)
specify the operating mode.
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, because un-
known operation or incompatibility with future ver-
sions may result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A11 (excluding A10, which is assigned
the auto precharge command) when the burst length
is set to two, by A2-A11 when the burst length is set to
four and by A3-A11 when the burst length is set to
eight. The remaining (least significant) address bit(s)
is (are) used to select the starting location within the
block. The programmed burst length applies to both
READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 9.
Figure 4: Mode Register Definition
Diagram
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
1
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
Valid
Valid
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency BT
0*
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8 M7
Operating Mode
A10
A12 A11
BA0
BA1
10
11
12
13
0*
14
* M14 and M13 (BA1 and BA0)
must be "0, 0" to select the
base mode register (vs. the
extended mode register).
M9
M10
M12 M11
Burst Length
CAS Latency BT
0*
0*
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
Operating Mode
A10
A11
BA0
BA1
10
11
12
13
* M13 and M12 (BA1 and BA0)
must be "0, 0" to select the
base mode register (vs. the
extended mode register).
256MB Module
512MB Module
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
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DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
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2003 Micron Technology, Inc. All rights reserved.
NOTE:
1. For a burst length of two, A1-A9, A11 select the two-
data-element block; A0 selects the first access within
the block.
2. For a burst length of four, A2-A9, A11 select the four-
data-element block; A0-A1 select the first access within
the block.
3. For a burst length of eight, A3-A9, A11 select the eight-
data-element block; A0-A2 select the first access within
the block.
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS
Latency Diagram.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used, because un-
known operation or incompatibility with future ver-
sions may result.
Figure 5: CAS Latency Diagram
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7A11 (for
256MB modules), or A7A12 (for 512MB modules)
each set to zero, and bits A0A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9A11 (256MB
modules), or A7 and A9A12 (for 512MB modules)
each set to zero, bit A8 set to one, and bits A0A6 set to
the desired values. Although not required by the
Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
Table 6:
Burst Definition Table
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES
WITHIN A BURST
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVE
D
2
A0
0
0-1
0-1
1
1-0
1-0
4
A1 A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
A2 A1 A0
0
0
0
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Table 7:
CAS Latency (CL) Table
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHz)
SPEED
CL = 2
CL = 2.5
-335
N/A
75
f 166
-262
75
f 133
75
f 133
-26A
75
f 133
75
f 133
-265
75
f 100
75 f
133
-202
75
f 100
75
f 125
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T2n
T3
T3n
DON'T CARE
TRANSITIONING DATA
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
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DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
10
2003 Micron Technology, Inc. All rights reserved.
reset the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
All other combinations of values for A7A11, or A7
A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Extended Mode Register
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable, output
drive strength, and QFC#. These functions are con-
trolled via the bits shown in the Extended Mode Regis-
ter Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
Output Drive Strength
The normal full drive strength for all outputs is
specified to be SSTL2, Class II. For detailed informa-
tion on output drive strength, refer to 128Mb and
256Mb DDR SDRAM component data sheets.
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
Figure 6: Extended Mode Register
Definition Diagram
Operating Mode
Reserved
Reserved
0
0
Valid
0
1
DLL
Enable
Disable
DLL
11
01
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
E0
0
Drive Strength
Normal
E1
0
QFC# Function
Disabled
Reserved
E22
E0
E1,
Operating Mode
A10
A11
A12
BA1 BA0
10
11
12
13
14
NOTE: 1. E13 and E12 (256MB module), or E14 and E13 (512MB Module)
(BA1 and BA0) must be "0, 1" to select the Extended
Mode Register (vs. the base Mode Register).
2. The QFC# option is not supported.
E2,
E3
E4
0
0
0
0
0
E6 E5
E7
E8
E9
0
0
E10
E11
0
E12
DS
QFC#
DLL
11
01
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
Operating Mode
A10
A11
BA1 BA0
10
11
12
13
DS
QFC
256MB Module
512MB Module
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
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11
2003 Micron Technology, Inc. All rights reserved.
Commands
The Truth Tables below provide a general reference
of available commands. For a more detailed descrip-
tion of commands and operations, refer to the 128Mb
or 256Mb DDR SDRAM component data sheet.
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0
BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0
A11 (256MB) or
A0
A12 (512MB) provide the op-code to be written to the selected mode register.
3. BA0
BA1 provide device bank address and A0
A11 (256MB) or A0
A12 (512MB) provide row address.
4. BA0
BA1 provide device bank address; A0
A9, A11 provide column address; A10 HIGH enables the auto precharge
feature (nonpersistent), and A10 LOW disables the auto precharge feature.
5. A10 LOW: BA0
BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0
BA1 are "Don't Care."
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
Table 8:
Truth Table Commands
Note: 1
NAME (FUNCTION)
CS#
RAS#
CAS#
WE#
ADDR
NOTES
DESELECT (NOP)
H
X
X
X
X
9
NO OPERATION (NOP)
L
H
H
H
X
9
ACTIVE (Select bank and activate row)
L
L
H
H
Bank/
Row
3
READ (Select bank and column, and start READ burst)
L
H
L
H
Bank/Col
4
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L
Bank/Col
4
BURST TERMINATE
L
H
H
L
X
8
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
Code
5
AUTO REFRESH or SELF REFRESH
L
L
L
H
X
6, 7
(Enter self refresh mode)
LOAD MODE REGISTER
L
L
L
L
Op-Code
2
Table 9:
Truth Table DM Operation
Note: 10
NAME (FUNCTION)
DM
DQS
WRITE Enable
L
Valid
WRITE Inhibit
H
X
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
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2003 Micron Technology, Inc. All rights reserved.
Absolute Maximum Ratings*
Voltage on V
DD
Supply
Relative to V
SS
. . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on V
DD
Q Supply
Relative to V
SS
. . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on V
REF
and Inputs
Relative to V
SS
. . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on I/O Pins
Relative to V
SS
. . . . . . . . . . . . . -0.5V to V
DD
Q +0.5V
Operating Temperature
T
A
(ambient) . . . . . . . . . . . . . . . . . . . . .. 0C to +70C
Storage Temperature (plastic) . . . . . .-55C to +150C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . 18W
Short Circuit Output Current . . . . . . . . . . . . . . . 50mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.
DC Electrical Characteristics and Operating Conditions
Notes: 15, 14; notes appear following parameter tables; 0C
T
A
+70C; V
DD
= +2.5V 0.2V, V
DD
Q = +2.5V 0.2V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
Supply Voltage
V
DD
2.3
2.7
V
32, 36
I/O Supply Voltage
V
DDQ
2.3
2.7
V
32, 36, 39
I/O Reference Voltage
V
REF
0.49
X
V
DD
Q 0.51
X
V
DD
Q
V
6, 39
I/O Termination Voltage (system)
V
TT
V
REF
- 0.04 V
REF
+ 0.04
V
7, 39
Input High (Logic 1) Voltage
V
IH
(DC)
V
REF
+ 0.15
V
DD
+ 0.3
V
25
Input Low (Logic 0) Voltage
V
IL
(DC)
-0.3
V
REF
- 0.15
V
25
INPUT LEAKAGE CURRENT
Any input 0V
V
IN
V
DD
, V
REF
pin 0V
V
IN
1.35V (All other pins not under test = 0V)
Command/
Address, RAS#,
CAS#, WE#, S0#,
CKE0
I
I
-5
5
A
48
CK, CK#
-10
10
DQ, DQS
-2
-2
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V
V
OUT
V
DD
Q)
I
OZ
-5
-5
A
48
OUTPUT LEVELS
High Current (V
OUT
= V
DD
Q - 0.373V, minimum V
REF
, minimum V
TT
)
Low Current (V
OUT
= 0.373V, maximum V
REF
, maximum V
TT
)
I
OH
-16.8
mA
33, 34
I
OL
16.8
mA
Table 10: AC Input Operating Conditions
Notes: 15, 14; notes appear following parameter tables; 0C
T
A
+70C; V
DD
= +2.5V 0.2V, V
DD
Q = +2.5V 0.2V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
(
AC
)
V
REF
+ 0.310
V
12, 25, 35
Input Low (Logic 0) Voltage
V
IL
(
AC
)
V
REF
- 0.310
V
12, 25, 35
I/O Reference Voltage
V
REF
(
AC
)
0.49
X
V
DD
Q
0.51
X
V
DD
Q
V
6
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
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DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
13
2003 Micron Technology, Inc. All rights reserved.
Table 11: IDD Specifications and Conditions (DDR SDRAM Components Only)
256MB Modules
Notes: 15,8, 10, 12; notes appear following parameter tables; 0C
T
A
+70C; V
DD
= V
DD
Q = +2.5V 0.2V
MAX
PARAMETER/CONDITION
SYMBOL
-335
-26A/-
265
-202
UNITS
NOTES
OPERATING CURRENT: One device bank; Active-
Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM and DQS
inputs changing once per clock cyle; Address and
control inputs changing once every two clock cycles
I
DD
0
TBD
1,890
1,800
mA
20, 43
OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
I
OUT
= 0mA; Address and control inputs changing once
per clock cycle
I
DD1
TBD
2,160
1,980
mA
20, 43
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode;
t
CK =
t
CK (MIN);
CKE = (LOW)
I
DD2P
TBD
54
54
mA
21, 28, 45
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
idle;
t
CK =
t
CK MIN; CKE = HIGH; Address and other
control inputs changing once per clock cycle. V
IN
= V
REF
for DQ, DQS, and DM
I
DD2F
TBD
810
630
mA
46
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;
t
CK =
t
CK (MIN); CKE =
LOW
I
DD3P
TBD
360
360
mA
21, 28, 45
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank; Active-Precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM andDQS inputs changing
twice per clock cycle; Address and other control inputs
changing once per clock cycle
I
DD3N
TBD
810
630
mA
42
OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One bank active; Address and control inputs
changing once per clock cycle;
t
CK =
t
CK (MIN); I
OUT
=
0mA
I
DD4R
TBD
2,250
1,890
mA
20, 43
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle;
t
CK =
t
CK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle
I
DD4W
TBD
2,070
1,890
mA
20
AUTO REFRESH CURRENT
t
RC =
t
RC(MIN)
I
DD5
TBD
3,780
3,690
mA
20, 45
t
RC = 15.625s
I
DD5A
TBD
90
90
mA
24, 45
SELF REFRESH CURRENT: CKE
0.2V
I
DD6
TBD
36
36
mA
9
OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge,
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control inputs change
only during Active READ, or WRITE commands
I
DD7
TBD
5,850
4,950
mA
20, 44
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
14
2003 Micron Technology, Inc. All rights reserved.
Table 12: IDD Specifications And Conditions (DDR SDRAM Components Only)
512MB Modules
Notes: 15, 8, 10, 12; notes appear following parameter tables; 0C
T
A
+70C; V
DD
= V
DD
Q = +2.5V 0.2V
MAX
PARAMETER/CONDITION
SYMBOL
-335
-26A/-
265
-202
UNITS
NOTES
OPERATING CURRENT: One device bank; Active-
Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM and DQS
inputs changing once per clock cyle; Address and
control inputs changing once every two clock cycles
I
DD
0
TBD
2,160
2,070
mA
20, 43
OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
I
OUT
= 0mA; Address and control inputs changing once
per clock cycle
I
DD1
TBD
2,520
2,250
mA
20, 43
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode;
t
CK =
t
CK (MIN);
CKE = (LOW)
I
DD2P
TBD
72
72
mA
21, 28, 45
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
idle;
t
CK =
t
CK MIN; CKE = HIGH; Address and other
control inputs changing once per clock cycle. V
IN
= V
REF
for DQ, DQS, and DM
I
DD2F
TBD
720
720
mA
46
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;
t
CK =
t
CK (MIN); CKE =
LOW
I
DD3P
TBD
540
450
mA
21, 28, 45
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank; Active-Precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM andDQS inputs changing
twice per clock cycle; Address and other control inputs
changing once per clock cycle
I
DD3N
TBD
810
720
mA
42
OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One bank active; Address and control inputs
changing once per clock cycle;
t
CK =
t
CK (MIN); I
OUT
=
0mA
I
DD4R
TBD
3,240
2,700
mA
20, 43
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle;
t
CK =
t
CK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle
I
DD4W
TBD
3,420
2,880
mA
20
AUTO REFRESH CURRENT
t
RC =
t
RC(MIN)
I
DD
5
TBD
4,410
3,870
mA
20, 45
t
RC = 7.8125s
I
DD5A
TBD
108
108
mA
24, 45
SELF REFRESH CURRENT: CKE
0.2V
I
DD6
TBD
72
72
mA
9
OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge,
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control inputs change
only during Active READ, or WRITE commands
I
DD7
TBD
6,570
6,300
mA
20, 44
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
15
2003 Micron Technology, Inc. All rights reserved.
Table 13: Capacitance
Note: 11; notes appear following parameter tables
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input/Output Capacitance: DQ, DQS
C
I0
4
5
pF
Input Capacitance: Command and Address, S0#, CKE0
C
I1
2.5
3.5
pF
Input Capacitance:CK0, CK0#
C
I2
2
3
pF
Table 14: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions
Notes: 15, 14; notes appear following parameter tables; 0C
T
A
+70C; V
DD
= +2.5V 0.2V, V
DD
Q = +2.5V 0.2V
AC CHARACTERISTICS
-335
-26A/-265
-202
PARAMETER
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
UNITS NOTES
Access window of DQs from CK/CK#
t
AC
-0.7
+0.7
-0.75
+0.75
-0.8
+0.8
ns
CK high-level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
26
CK low-level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
26
Clock cycle time
CL = 2.5
t
CK (2.5)
6
13
7.5
13
8
13
ns
40,47
CL = 2
t
CK (2)
7.5
13
7.5/10
13
10
13
ns
40, 47
DQ and DM input hold time relative to DQS
t
DH
0.45
0.5
0.6
ns
23, 27
DQ and DM input setup time relative to DQS
t
DS
0.45
0.5
0.6
ns
23, 27
DQ and DM input pulse width (for each input)
t
DIPW
1.75
1.75
2
ns
27
Access window of DQS from CK/CK#
t
DQSCK -0.60
+0.60
-0.75
+0.75
-0.8
+0.8
ns
DQS input high pulse width
t
DQSH
0.35
0.35
0.35
t
CK
DQS input low pulse width
t
DQSL
0.35
0.35
0.35
t
CK
DQS-DQ skew, DQS to last DQ valid, per group, per access
t
DQSQ
0.35
0.5
0.6
ns
22, 23
Write command to first DQS latching transition
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS falling edge to CK rising - setup time
t
DSS
0.2
0.2
0.2
t
CK
DQS falling edge from CK rising - hold time
t
DSH
0.2
0.2
0.2
t
CK
Half clock period
t
HP
t
CH,
t
CL
t
CH,
t
CL
t
CH,
t
CL
ns
30
Data-out high-impedance window from CK/CK#
t
HZ
+0.70
+0.75
+0.8
ns
16, 37
Data-out low-impedance window from CK/CK#
t
LZ
-0.70
-0.75
-0.8
ns
16, 38
Address and control input hold time (fast slew rate)
t
IH
F
.75
.90
1.1
ns
12
Address and control input setup time (fast slew rate)
t
IS
F
.75
.90
1.1
ns
12
Address and control input hold time (slow slew rate)
t
IH
S
.80
1
1.1
ns
12
Address and control input setup time (slow slew
rate)
t
IS
S
.80
1
1.1
ns
12
LOAD MODE REGISTER command cycle time
t
MRD
12
15
16
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
t
QH
t
HP -
t
QHS
t
HP -
t
QHS
t
HP -
t
QHS
ns
22, 23
Data hold skew factor
t
QHS
0.50
0.75
1
ns
ACTIVE to PRECHARGE command
t
RAS
42
120,000
40
120,000
40
120,000
ns
31
ACTIVE to READ with Auto precharge command
(256MB Modules)
t
RAP
18
t
RAS(MIN )-(burst
length*
t
CK/2)
ns
ACTIVE to READ with Auto precharge command
(512MB Modules)
t
RAP
18
20
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
t
RC
60
65
70
ns
AUTO REFRESH command period
t
RFC
72
75
80
ns
45
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
16
2003 Micron Technology, Inc. All rights reserved.
ACTIVE to READ or WRITE delay
t
RCD
18
20
20
ns
PRECHARGE command period
t
RP
18
20
20
ns
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
37
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
ACTIVE bank a to ACTIVE bank b
command
t
RRD
12
15
15
ns
DQS write preamble
t
WPRE
0.25
0.25
0.25
t
CK
DQS write preamble setup time
t
WPRES
0
0
0
ns
18, 19
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
17
Write recovery time
t
WR
15
15
15
ns
Internal WRITE to READ command delay
t
WTR
1
1
1
t
CK
Data valid output window
NA
t
QH -
t
DQSQ
t
QH -
t
DQSQ
t
QH -
t
DQSQ
ns
22
REFRESH to REFRESH command interval
(256MB Modules)
t
REFC
140.6
140.6
140.6
s
21
REFRESH to REFRESH command interval
(512 MB Modules)
t
REFC
70.3
70.3
70.3
s
21
Average periodic refresh interval
(256MB Modules)
t
REFI
15.6
15.6
15.6
s
21
Average periodic refresh interval
(512MB Modules)
t
REFI
7.8
7.8
7.8
s
21
Terminating voltage delay to V
DD
t
VTD
0
0
0
ns
Exit SELF REFRESH to non-READ command
t
XSNR
75
75
80
ns
Exit SELF REFRESH to READ command
t
XSRD
200
200
200
t
CK
Table 14: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (Continued)
Notes: 15, 14; notes appear following parameter tables; 0C
T
A
+70C; V
DD
= +2.5V 0.2V, V
DD
Q = +2.5V 0.2V
AC CHARACTERISTICS
-335
-26A/-265
-202
PARAMETER
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
UNITS NOTES
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
17
2003 Micron Technology, Inc. All rights reserved.
Notes
1. All voltages referenced to V
SS
.
2. Tests for AC timing, I
DD
, and electrical AC and DC
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs measured with equivalent load:
4. AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 1.5V in the test environment, but
input timing is still referenced to V
REF
(or to the
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V
IL
(
AC
)
and V
IH
(
AC
).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. V
REF
is expected to equal V
DD
Q/2 of the transmit-
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
REF
may not exceed 2 percent of the
DC value. Thus, from V
DD
Q/2, V
REF
is allowed
25mV for DC error and an additional 25mV for
AC noise. This measurement is to be taken at the
nearest V
REF
by-pass capacitor.
7. V
TT
is not applied directly to the device. V
TT
is a
system supply for signal termination resistors, is
expected to be set equal to V
REF
and must track
variations in the DC level of V
REF
.
8. I
DD
is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -26A and -202, CL =
2.5 for -335 and -265 with the outputs open.
9. Enables on-chip refresh and address counters.
10. I
DD
specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
11. This parameter is sampled. V
DD
= +2.5V 0.2V,
V
DDQ
= +2.5V 0.2V, V
REF
= V
SS
, f = 100 MHz,
T
A
= 25C, V
OUT
(DC) = V
DD
Q/2, V
OUT
(peak to
peak) = 0.2V. DM input is grouped with I/O pins,
reflecting the fact that they are matched in load-
ing.
12. Command/Address input slew rate = 0.5V/ns. For
-75 with slew rates 1V/ns and faster,
t
IS and
t
IH
are reduced to 900ps. If the slew rate is less than
0.5V/ ns, timing must be derated:
t
IS has an addi-
tional 50ps per each 100mV/ns reduction in slew
rate from the 500mV/ns.
t
IH has 0ps added, that
is, it remains constant. If the slew rate exceeds
4.5V/ns, functionality is uncertain.
13. The CK/CK# input reference level (for timing ref-
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V
REF
.
14. Inputs are not recognized as valid until V
REF
stabi-
lizes. Exception: during the period before V
REF
stabilizes, CKE
0.3 x V
DD
Q is recognized as LOW.
15. The output timing reference level, as measured at
the timing reference point indicated in Note 3, is
V
TT
.
16.
t
HZ and
t
LZ transitions occur in the same access
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
17. The maximum limit for this parameter is not a
device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
18. This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
19. It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
t
DQSS.
20. MIN (
t
RC or
t
RFC) for I
DD
measurements is the
smallest multiple of
t
CK that meets the minimum
absolute value for the respective parameter.
t
RAS
(MAX) for I
DD
measurements is the largest multi-
ple of
t
CK that meets the maximum absolute
value for
t
RAS.
Output
(V
OUT
)
Reference
Point
50
V
TT
30pF
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
18
2003 Micron Technology, Inc. All rights reserved.
21. The refresh period 64ms. This equates to an aver-
age refresh rate of 15.625s (256MB modules) or
7.8125s (512MB modules). However, an AUTO
REFRESH command must be asserted at least
once every 140.6s (256MB modules) or 70.3s
(512MB modules); burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
22. The valid data window is derived by achieving
other specifications -
t
HP (
t
CK/2),
t
DQSQ, and
t
QH (
t
QH =
t
HP -
t
QHS). The data valid window
derates directly porportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data
valid window derating curves are provided below
for duty cycles ranging between 50/50 and 45/55.
23. Referenced to each output group: x4 = DQS with
DQ0-DQ4.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (
t
RFC [MIN]) else
CKE is LOW (i.e., during standby).
25. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, V
IL
(AC)
or V
IH
(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, V
IL
(DC)
or V
IH
(DC).
26. JEDEC specifies CK and CK# input slew rate must
be
1V/ns (2V/ns differentially).
27. DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
DS and
t
DH for each 100mv/ns reduction in slew rate. If
slew rate exceeds 4V/ns, functionality is uncer-
tain.
28. V
DD
must not vary more than 4 percent if CKE is
not active while any bank is active.
29. The clock is allowed up to 150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
30.
t
HP min is the lesser of
t
CL minimum and
t
CH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
Figure 7: Derating Data Valid Window
(
t
QH -
t
DQSQ)
3.750
3.700
3.650
3.600
3.550
3.500
3.450
3.400
3.350
3.300
3.250
3.400
3.350
3.300
3.250
3.200
3.150
3.100
3.050
3.000
2.950
2.900
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
50/50
49.5/50.5 49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
ns
-26A/-265 @
t
CK = 10ns
-202 @
t
CK = 10ns
-26A/-265 @
t
CK = 7.5ns
-202 @
t
CK = 8ns
-335 @
t
CK = 6ns
TBD
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
19
2003 Micron Technology, Inc. All rights reserved.
31. READs and WRITEs with auto precharge are not
allowed to be issued until
t
RAS (MIN) can be satis-
fied prior to the internal precharge command
being issued.
32. Any positive glitch must be less than 1/3 of the
clock and not more than +400mV or 2.9V, which-
ever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -
300mV or 2.2V, whichever is more positive.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 8.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 9.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
34. The voltage levels used are derived from a mini-
mum V
DD
level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
35. V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 1.5V for a
pulse width
3ns and the pulse width can not be
greater than 1/3 of the cycle rate. V
IL
undershoot:
V
IL
(MIN) = -1.5V for a pulse width
3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
36. V
DD
and V
DD
Q must track each other.
37. This maximum value is derived from the refer-
enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for
t
HZ (MAX) and the last DVW.
t
HZ
(MAX) will prevail over
t
DQSCK (MAX) +
t
RPST
(MAX) condition.
t
LZ (MIN) will prevail over
t
DQSCK (MIN) +
t
RPRE (MAX) condition.
38. For slew rates greater than 1V/ns the (LZ) transi-
tion will start about 310ps earlier.
39. During initialization, V
DD
Q, V
TT
, and V
REF
must
be equal to or less than V
DD
+ 0.3V. Alternatively,
V
TT
may be 1.35V maximum during power up,
even if V
DD
/V
DD
Q are 0V, provided a minimum of
42
W of series resistance is used between the V
TT
supply and the input pin.
40. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
41.
t
RAP
t
RCD.
42. For the -335, -26A and -265, I
DD
3
N
is specified to
be 35mA at 100 MHz.
43. Random address changing and 50 percent of data
changing at every transfer.
44. Random address changing and 100 percent of
data changing at every transfer.
Figure 8: Pull-Down
Figure 9: Pull-Up
160
140
I
OUT
(mA)
V
OUT
(V)
Nominal low
Minimum
Nominal high
Maximum
120
100
80
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
V
OUT
(V)
0
-20
I
OUT
(mA)
Nominal low
Minimum
Nominal high
Maximum
-40
-60
-80
-100
-120
-140
-160
-180
-200
0.0
0.5
1.0
1.5
2.0
2.5
V
DDQ
V
OUT
(V)
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
20
2003 Micron Technology, Inc. All rights reserved.
45. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
REF later.
46. I
DD
2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. I
DD
2Q is
similar to I
DD
2
F
except I
DD
2Q specifies the
address and control inputs to remain stable.
Although I
DD
2
F
, I
DD
2
N
, and I
DD
2Q are similar,
I
DD
2
F
is "worst case."
47. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
48. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
21
2003 Micron Technology, Inc. All rights reserved.
SPD Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions
(Figure 10 and Figure 11).
SPD Start Condition
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 12).
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.
Figure 10: Data Validity
Figure 11: Definition of Start and Stop
Figure 12: Acknowledge Response From Receiver
SCL
SDA
DATA STABLE
DATA STABLE
DATA
CHANGE
SCL
SDA
START
BIT
STOP
BIT
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
9
8
Acknowledge
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
22
2003 Micron Technology, Inc. All rights reserved.
Table 15: EEPROM Device Select Code
The most significant bit (b7) is sent first
DEVICE TYPE IDENTIFIER
CHIP ENABLE
RW
b7
b6
b5
b4
b3
b2
b1
b0
Memory Area Select Code (two arrays)
1
0
1
0
SA2
SA1
SA0
RW
Protection Register Select Code
0
1
1
0
SA2
SA1
SA0
RW
Table 16: EEPROM Operating Modes
MODE
RW BIT
WC
BYTES
INITIAL SEQUENCE
Current Address Read
1
V
IH
or V
IL
1
START, Device Select, RW = `1'
Random Address Read
0
V
IH
or V
IL
1
START, Device Select, RW = `0', Address
1
V
IH
or V
IL
1
reSTART, Device Select, RW = `1'
Sequential Read
1
V
IH
or V
IL
1
Similar to Current or Random Address Read
Byte Write
0
V
IL
1
START, Device Select, RW = `0'
Page Write
0
V
IL
16
START, Device Select, RW = `0'
Table 17: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
SS
; V
DDSPD
= +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
SUPPLY VOLTAGE
V
DDSPD
2.3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
V
DD
x 0.7
V
DD
+ 0.5
V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-1
V
DD
x 0.3
V
OUTPUT LOW VOLTAGE: I
OUT
= 3mA
V
OL
0.4
V
INPUT LEAKAGE CURRENT: V
IN
= GND to V
DD
I
LI
10
A
OUTPUT LEAKAGE CURRENT: V
OUT
= GND to V
DD
I
LO
10
A
STANDBY CURRENT:
I
SB
30
A
SCL = SDA = V
DD
- 0.3V; All other inputs = GND or 3.3V 10%
POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz
I
CC
2
mA
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
23
2003 Micron Technology, Inc. All rights reserved.
Figure 13: SPD EEPROM Timing Diagram
NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
SCL
SDA IN
SDA OUT
tLOW
tSU:STA
tHD:STA
tF
tHIGH
tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
Table 18: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
SS
; V
DDSPD
= +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SCL LOW to SDA data-out valid
t
AA
0.2
0.9
s
1
Time the bus must be free before a new transition can start
t
BUF
1.3
s
Data-out hold time
t
DH
200
ns
SDA and SCL fall time
t
F
300
ns
2
Data-in hold time
t
HD:DAT
0
s
Start condition hold time
t
HD:STA
0.6
s
Clock HIGH period
t
HIGH
0.6
s
Noise suppression time constant at SCL, SDA inputs
t
I
50
ns
Clock LOW period
t
LOW
1.3
s
SDA and SCL rise time
t
R
0.3
s
2
SCL clock frequency
f
SCL
400
KHz
Data-in setup time
t
SU:DAT
100
ns
Start condition setup time
t
SU:STA
0.6
s
3
Stop condition setup time
t
SU:STO
0.6
s
WRITE cycle time
t
WRC
10
ms
4
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
24
2003 Micron Technology, Inc. All rights reserved.
Table 19: Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes at end of Serial Presence-Detect Matrix
BYTE
DESCRIPTION
ENTRY (VERSION)
MT18VDDF3272
MT18VDDF6472
0
NUMBER OF SPD BYTES USED BY MICRON
128
80
80
1
TOTAL NUMBER OF BYTES IN SPD DEVICE
256
08
08
2
FUNDAMENTAL MEMORY TYPE
SDRAM DDR
07
07
3
NUMBER OF ROW ADDRESSES ON ASSEMBLY
12 or13
0C
0D
4
NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
11
0B
0B
5
NUMBER OF PHYSICAL BANKS ON DIMM
1
01
01
6
MODULE DATA WIDTH
72
48
48
7
MODULE DATA WIDTH (continued)
0
00
00
8
MODULE VOLTAGE INTERFACE LEVELS (V
DD
Q)
SSTL 2.5V
04
04
9
SDRAM CYCLE TIME, (
t
CK), CAS LATENCY = 2.5
(See note 1)
6n (-335)s
7ns (-262/-26A)
7.5ns (-265)
8ns (-202)
60
70
75
80
60
70
75
80
10
SDRAM ACCESS FROM CLOCK,(
t
AC)
(CAS LATENCY = 2.5)
0.7ns (-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
11
MODULE CONFIGURATION TYPE
ECC
02
02
12
REFRESH RATE/TYPE
15.62s or 7.81s/
SELF
80
82
13
SDRAM DEVICE WIDTH (PRIMARY SDRAM)
4
04
04
14
ERROR-CHECKING SDRAM DATA WIDTH
4
04
04
15
MINIMUM CLOCK DELAY, BACK-TO-BACK
RANDOM COLUMN ACCESS
1 clock
01
01
16
BURST LENGTHS SUPPORTED
2, 4, 8
0E
0E
17
NUMBER OF BANKS ON SDRAM DEVICE
4
04
04
18
CAS LATENCIES SUPPORTED
2, 2.5
0C
0C
19
CS LATENCY
0
01
01
20
WE LATENCY
1
02
02
21
SDRAM MODULE ATTRIBUTES
Registered, PLL/Diff.
Clock
26
26
22
SDRAM DEVICE ATTRIBUTES: GENERAL
Fast/Concurrent AP
C0
C0
23
SDRAM CYCLE TIME, (
t
CK) (CAS LATENCY = 2)
7.5ns (-262/-335/-26A)
10ns (-265/-202)
75
A0
75
A0
24
SDRAM ACCESS FROM CK , (
t
AC)
(CAS LATENCY = 2)
0.70ns (-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
25
SDRAM CYCLE TIME, (
t
CK)
(CAS LATENCY = 1.5)
N/A
00
00
26
SDRAM ACCESS FROM CK , (
t
AC)
(CAS LATENCY = 1.5)
N/A
00
00
27
MINIMUM ROW PRECHARGE TIME, (
t
RP)
18ns (-335)
15ns (-262)
20ns (-26A/-265/-202)
48
3C
50
48
3C
50
28
MINIMUM ROW ACTIVE TO ROW ACTIVE, (
t
RRD)
12ns (-335)
15ns (-262/-26A/-265/-202
30
3C
30
3C
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
25
2003 Micron Technology, Inc. All rights reserved.
29
MINIMUM RAS# TO CAS# DELAY, (
t
RCD)
18ns (-335)
15ns (-262)
20ns (-202/-265/-26A)
48
3C
50
48
3D
50
30
MINIMUM RAS# PULSE WIDTH, (
t
RAS)
(See note 2)
42ns (-335)
45ns (-262/-26A/-265)
40ns (-202)
2A
2D
28
2A
2D
28
31
MODULE BANK DENSITY
256MB or 512MB
40
80
32
ADDRESS AND COMMAND SETUP TIME, (
t
IS),
Value set to slow slew rate
t
IS
s
(See note 3)
0.80ns (-335)
1ns (-262/-26A/-265)
1.1ns (-202)
80
A0
B0
80
A0
B0
33
ADDRESS AND COMMAND HOLD TIME, (
t
IH),
Value set to slow slew rate
t
IH
s,
(Note 3)
0.80ns (-335)
1ns (-262/-26A/-265)
1.1ns (-202)
80
A0
B0
80
A0
B0
34
DATA/DATA MASK INPUT SETUP TIME, (
t
DS)
0.45ns (-335)
0.50ns (-262-26A/-265)
0.60ns (-202)
45
50
60
45
50
60
35
DATA/DATA MASK INPUT HOLD TIME, (
t
DH)
0.45ns (-335)
0.50ns (-262/-26A/-265)
0.60ns. (-202)
45
50
60
45
50
60
36-40 RESERVED
00
00
41
MIN ACTIVE AUTO REFRESH TIME (
t
RC)
60ns (-335/-262)
65ns (-26A/-265)
70ns (-202)
3C
41
46
3C
41
46
42
MINIMUM AUTO REFRESH TO ACTIVE/
AUTO REFRESH COMMAND PERIOD, (
t
RFC)
72ns (-335)
75ns (-262/-26A/-265)
80ns (-202)
48
4B
50
48
4B
50
43
SDRAM DEVICE MAX CYCLE TIME (
t
CK
MAX
)
12ns (-335)
13ns (-262/-26A/-265/-202)
30
34
30
34
44
SDRAM DEVICE MAX DQS-DQ SKEW TIME (
t
DQSQ)
0.4ns (-335)
0.5ns (-262/-26A/-265)
0.6ns (-202)
28
32
3C
28
32
3C
45
SDRAM DEVICE MAX READ DATA HOLD SKEW
FACTOR (
t
QHS)
0.50ns (-335)
0.75ns (-262/-26A/-265)
1.0ns (-202)
50
75
A0
50
75
A0
46
RESERVED
00
00
47
DIMM HEIGHT
01
01
4861 RESERVED
00
00
62
SPD REVISION
Release 1.0
10
10
46-61 RESERVED
00
00
63
CHECKSUM FOR BYTES 0-62
-335
-262
-26A
-265
-202
2B
C8
F5
25
C0
6E
0B
38
68
03
64
MANUFACTURER'S JEDEC ID CODE
MICRON
2C
2C
65-71 MANUFACTURER'S JEDEC ID CODE
(Continued)
FF
FF
72
MANUFACTURING LOCATION
0112
010C
010C
73-90 MODULE PART NUMBER (ASCII)
Variable Data
Variable Data
91
PCB IDENTIFICATION CODE
1-9
01-09
01-09
Table 19: Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes at end of Serial Presence-Detect Matrix
BYTE
DESCRIPTION
ENTRY (VERSION)
MT18VDDF3272
MT18VDDF6472
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
26
2003 Micron Technology, Inc. All rights reserved.
NOTE:
1. Value for -26A
t
CK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. vaule is 7.5ns.
2. The value of
t
RAS used for -26A/-265 modules is calculated from
t
RC -
t
RP. Actual device spec value is 40 ns.
3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is
represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.
92
IDENTIFICATION CODE (continued)
0
00
00
93
YEAR OF MANUFACTURE IN BCD
Variable Data
Variable Data
94
WEEK OF MANUFACTURE IN BCD
Variable Data
Variable Data
95-98 MODULE SERIAL NUMBER
Variable Data
Variable Data
99-127 MANUFACTURER-SPECIFIC DATA (RSVD)
Table 19: Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes at end of Serial Presence-Detect Matrix
BYTE
DESCRIPTION
ENTRY (VERSION)
MT18VDDF3272
MT18VDDF6472
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
ADVANCE
32, 64 Meg x 72 DDR SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
27
2003 Micron Technology, Inc. All rights reserved.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
Figure 14: 184-Pin DIMM DDR Module
NOTE:
All dimensions in inches (millimeters) with
or typical where noted.
Data Sheet Designation
Advance: This datasheet contains initial descrip-
tions of products still under development.
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
1.131 (28.73)
1.119 (28.42)
PIN 1
.700 (17.78)
TYP.
.098 (2.50) D
(2X)
.091 (2.30) TYP.
.250 (6.35) TYP.
4.750 (120.65)
.050 (1.27)
TYP.
.091 (2.30)
TYP.
.040 (1.02)
TYP.
.079 (2.00) R
(4X)
.035 (0.90) R
PIN 92
FRONT VIEW
.054 (1.37)
.046 (1.17)
5.256 (133.50)
5.244 (133.20)
2.55 (64.77)
1.95 (49.53)
.394 (10.00)
TYP.
.125 (3.175)
MAX
PIN 184
PIN 93
BACK VIEW
MAX
MIN
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