PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

09005aef80bcd58d
MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

FLASH AND CellularRAM

COMBO MEMORY

MT28C256532W18S
MT28C256564W18S

Low Voltage, Wireless Temperature

Features

· Stacked die Combo package

Includes two 128Mb Flash devices
Choice of either one 32Mb or one 64Mb

CellularRAM

Ô device

· Basic configuration

Flash

Flexible multibank architecture
8 Meg x 16 Async/Page/Burst interface
Support for true concurrent operations with
no latency

CellularRAM

Low-power, high-density design
2 Meg x 16 or 4 Meg x 16 configurations
Async/Page

· F_V

, V

Q, F_V

, PS_V

voltages

1.70V (MIN)/1.95V (MAX) F_V

, PS_V

1.70V (MIN)/2.24V (MAX) V

1.80V (TYP) F_V

(in-system PROGRAM/ERASE)

12V ±5% (HV) F_V

(in-house programming and

accelerated programming algorithm [APA]
activation)

· Asynchronous access time

Flash/CellularRAM access time: 60ns @ 1.70V V

· Page Mode read access

Interpage read access: 60ns @ 1.8V F_V

, PS_V

Intrapage read access: 20ns @ 1.8V F_V

, PS_V

· Burst Mode Read Access

Max Operating Frequency: 66 MHz
Flash Initial Latency: 60ns @ 1.8V F_V

/66 MHz

CellularRAM Initial Latency: 60ns @ 1.8V PS_V

/66 MHz

ACLK: 11ns @ 1.8V Vcc

· Enhanced suspend options

ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank

· Each Flash contains two 64-bit chip protection

registers for security purposes

· Flash PROGRAM/ERASE cycles

100,000 WRITE/ERASE cycles per block

· Cross-compatible command set support

Extended command set
Common Flash interface (CFI) compliant

Part Number Example:

MT28C256564W18S-705 BBWT

Options

Marking

· Timing

60ns
70ns

-60
-70

· Burst Frequency

66 MHz
54 MHz

6
5

· Boot Block Configuration

Top/Top
Top/Bottom
Bottom/Top
Bottom/Bottom

TT
TB
BT
BB

· Operating Voltage Range

PS_V

1.70V1.95V

· Operating Temperature Range

Wireless Temperature (-25°C to +85°C)

· Package

88-ball FBGA
(8 x 10 grid with eight support balls)

Figure 1: 88-Ball FBGA

1 2 3 4 5 6 7 8

Top View

(Ball Down)

PS_V

F_V

F_WP#

F_RP#

DQ10

DQ3

DQ11

F_VCC

A19

A23

PS_UB#

DQ2

DQ1

DQ9

PS_OE#

F_CE#1

PS_V

F_V

CLK

PS_CE#

A20

DQ13

DQ14

DQ6

F_V

A11

A12

A13

A15

A16

PS_ZZ#

PS_V

F_V

PS_WE#

ADV#

F_WE#

DQ5

DQ12

DQ4

PS_V

A18

PS_LB#

A17

DQ8

DQ0

F_OE#1

A21

A22

A10

A14

WAIT#

DQ7

DQ15

F_V

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

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MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Flash Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
MultiChip Packaging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Unique IDs, State Machines, and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Flash Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Flash Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

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MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

List of Figures

Figure 1:

88-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2:

Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 3:

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 4:

Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5:

88-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

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MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

List of Tables

Table 1:

Cross-Reference for Abbreviated Device Marks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 2:

Valid Part Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 3:

Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 4:

Possible Boot Configurations for Flash Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 5:

Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 6:

Absolute Maximum Ratings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 7:

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 8:

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 9:

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 10:

CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

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MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

General Description

The MT28C256532W18S/MT28C256564W18S com-

bination Flash and CellularRAM is a high-performance,
high-density, memory solution that can significantly
improve system performance. The Flash architecture
features a multipartition configuration that supports
READ-while-PROGRAM/ERASE operations with no
latency. An 8Mb partition size enables optimal design
flexibility.

Two Flash devices are stacked to achieve the 256Mb

density. Both Flash die share a dedicated CE# and OE#
control.

The MT28C256532W18S/MT28C256564W18S

stacked Flash device enables soft protection for blocks,
as read only, by configuring soft protection registers
with dedicated command sequences. For security pur-
poses, two user-programmable 64-bit chip protection
registers are provided for each Flash device.

The embedded WORD PROGRAM and BLOCK

ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.

Each Flash device has a read configuration register

(RCR) that defines how the Flash interacts with the
memory bus. For device specifications and additional
documentation concerning Flash and CellularRAM fea-
tures, please refer to the MT28F1284W18 data sheet at

www.micron.com/flash

and the MT45W2MW16PFA and

MT45W4MW16PFA data sheets at

http://

www.micron.com/cellularram

The CellularRAM architecture features high-speed

CMOS, dynamic random-access memories developed for
low-power portable applications The CellularRAM device
is available in either 32Mb or 64Mb densities.

To operate seamlessly on a burst Flash bus, Cellular-

RAM products have incorporated a transparent self-
refresh mechanism. The hidden refresh requires no
additional support from the system memory controller
and has no significant impact on device read/write per-
formance.

The refresh configuration register (CR) is used to con-

trol how refresh is performed on the DRAM array. These
registers are automatically loaded with default settings
during power-up and can be updated any time during
normal operation. Special attention has been focused
on standby current consumption during self-refresh.

CellularRAM products include three system-acces-

sible mechanisms used to minimize standby current.
Partial array refresh (PAR) limits refresh to the portion
of the memory array being used. Temperature com-
pensated refresh (TCR) is used to adjust the refresh
rate according to the ambient temperature. The
refresh rate can be decreased to lower temperatures to
minimize current consumption during standby. Deep
sleep mode halts the refresh operation altogether and
is used when no vital information is stored in the
device. These three refresh mechanisms are adjusted
through the CR.

Please refer to Micron's Web site

www.micron.com/

flash

for the latest MT28F1284W18

Flash data sheet

sheet and

http://www.micron.com/cellularram

for the

latest MT45W2MW16PFA and MT45W4MW16PFA Cel-
lularRAM data sheet.

Flash Configurations

Each Flash memory implements a multibank archi-

tecture (16 banks of 8Mb each) to allow concurrent
operations. Any address within a block address range
selects that block for the required READ, PROGRAM, or
ERASE operation.

Each Flash memory features eight 8K-word sectors

(8 x 65,536 bits), designated as parameter blocks, and
the remaining part is organized in main blocks of 64K
words each (524,288 bits). The parameter blocks are
addressed either by the low order addresses (bottom
boot) or by the higher order addresses (top boot).

The two Flash devices can be supplied with any

combination of top or bottom boot (e.g., top/top, bot-
tom/bottom, top/bottom, or bottom/top). Please see
Figures 2 and 3 for more information.

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

Part Numbering Information

Micron's low-power devices are available with sev-

eral different combinations of features (see Figure 4).

Valid combinations of features and their correspond-
ing part numbers are listed in Table 2.

Figure 4: Part Number Chart

MT 28C 2565 64 W18 S FT -70 5 BB WT ES

Micron Technology

Flash Family

28C = Dual-Supply Flash/CellularRAM Combo

Density/Organization/Banks

256 = 256Mb (8,192K x 16)
bank x = 5 Multibank 32 Banks
(all banks have the same dimensions)

Access Time

-60 = 60ns
-70 = 70ns

CellularRAM Density

64 = 64Mb CellularRAM (4 Meg x 16)
32 = 32Mb CellularRAM (2 Meg x 16)

Flash Read Mode Operation

W = Flash Async/Page/Burst Read

Package Code

FT = 80-ball FBGA with eight
support balls (8 x 10 grid)

Operating Temperature Range

WT = Wireless (-25ºC to +85ºC)

Burst Mode Frequency

5 = 54 MHz
6 = 66 MHz

Boot Block Starting Address

BB = Bottom boot/Bottom boot
BT = Bottom boot/Top boot
TT = Top boot/Top boot
TB = Top boot/Bottom boot

Operating Voltage Range

18 = 1.7V1.95V Vcc

CE Select/Special Mark

S = Single CE Flash with Asynchronous PSRAM

Production Status

Blank = Production
ES = Engineering Samples
MS = Mechanical Samples

Table 2:

Valid Part Number Combinations

PART NUMBER

ACCESS TIME

(ns)

BOOT BLOCK STARTING

ADDRESS

BURST FREQUENCY

(MHz)

MT28C256532W18SFT-705 BTWT

-70

Bottom/Top

MT28C256532W18SFT-705 TTWT

-70

Top/Top

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

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MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

Table 3:

Ball Descriptions

88-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTIONS

B1, B2, B3, B7, B8,

C1, C3, C7, C8, D1,

D2, D7, D8, E1, E2,

E6, E7, E8, F1, F2,

F6, F7, F8, G1

A0A23

Input

Addresses:
Flash: A0A23
CellularRAM: A0A21 (64Mb)
CellularRAM: A0A20 (32Mb)

F_CE#

Input

Flash Chip Enable

F_OE#

Input

Flash Output Enable

F_WE#

Input

Flash Write Enable

F_WP#

Input

Flash Write Protect

PS_LB#

Input

CellularRAM Lower Byte Control

PS_UB#

Input

CellularRAM Upper Byte Control

PS_WE#

Input

CellularRAM Write Enable

PS_OE#

Input

CellularRAM Output Enable

PS_CE#

Input

CellularRAM Chip Enable

PS_ZZ#

Input

CellularRAM Deep Sleep Mode and Configuration Mode

ADV#

Input

Flash Address Valid (Burst operation only)

CLK

Input

Flash Clock (Burst operation only)

F_RP#

Input

Flash Reset

G2, G3, G4, G5,
G6, H2, H3, H4,

H5, H6, H7, J3, J4,

J5, J6, J7

DQ0DQ15

I/O

Flash/CellularRAM Data Input/Output

WAIT#

Output

Flash/ WAIT#

F_V

Supply

Flash Core Ground

F_V

Supply

Flash V

F_V

Supply

Flash Core Power Supply

PS_V

Supply

CellularRAM Core Ground

PS_V

Supply

CellularRAM Core Power supply

Supply

Flash/CellularRAM I/O supply

Supply

Flash/CellularRAM I/O ground

A1, A2, A7, A8, C5,

D3, E3, G8, H8, J1,

K2, K3, K4, M1,

M2, M7, M8

No Connect

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80bcd58d

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MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

Boot Configurations

The possible configurations for Flash die are shown

in Table 4 below. This table shows the possible config-
urations of the two Flash devices for either top boot or
bottom boot.

MultiChip Packaging Considerations

Multichip packaging presents unique chal-

lenges when controlling complex memory devices.

The MT28C256532W18 and MT28C256564W18

devices combine two Micron Flash devices with a
single CellularRAM device.

Unique IDs, State Machines, and
Registers

Each Flash device has a separate command state

machine (CSM) and status register (SR) and read con-
figuration register (RCR). The RCR settings are sepa-
rate and can be different for the upper and lower
device. Each Flash device has its own OTP, CFI, and
device code. Depending on the boot configuration of
each Flash device, the OTP, CFI, and device code infor-
mation may differ.

The CellularRAM device has a refresh configuration

Command Codes

All Flash command codes are independent

within each device. Care must be taken when
crossing the array boundary between the upper
and lower Flash device and the CellularRAM
device to ensure that only one device is enabled at
one time.

In a two-cycle command sequence such as word

program (0x40/data), it is required that both com-
mands be issued to the same device.

It is not recommended that READ and ERASE

operations occur simultaneously on two devices.

READ Operation

Page and burst read modes are limited to the

address boundaries of each device. A new page/ burst
operation must be started when crossing a device
boundary.

Flash Reset

The reset control is shared by both Flash die.

Bringing RST# conrol LOW will reset both the
upper and lower device.

Power Consumption

Multiple chip packaging requires that power

calculations consider the active operation of the
upper and lower Flash device as well as that of the
CellularRAM device. Total power consumed will
be the sum of the currents associated with the
state of each device. Table 10 on page 14 shows the
power consumption specifications.

Table 4:

Possible Boot Configurations
for Flash Die

CONFIGURATION

F_CE1#

ORDER CODE

Top/Top

Top

Bottom/Top

Bottom

Top/Bottom

Top

Bottom/Bottom

Bottom

256Mb MU

IBAN

BURST FL

ASH

32
Mb/

b ASYNC/

PAGE C

ularRAM

COM

ADV

ANCE

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e

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Table 5:

Truth Table

MODES

FLASH SIGNALS

SHARED SIGNALS

CellularRAM SIGNALS

MEMORY OUPUT

F_CE#

F_OE#

F_WE#

F_RP# ADV#

WAIT#

PS_CE#

PS_CRE# PS_OE# PS_UB/LB PS_WE#

MEMORY

BUS

CONTROL

D0D15

FLA

CE#

Read

Valid

CellularRAM must be in High-Z

Flash

OUT

Write

Valid

Flash

Standby

CellularRAM any mode allowable

Other

High-Z

Output
Disable

Other

High-Z

Reset

None

High-Z

CellularRAM

Read

Flash must be in High-Z

Valid

PSRAM

OUT

Write

Valid

PSRAM

Standby

Flash any mode allowable

Other

High-Z

Output
Disable

Other

High-Z

Deep
Sleep
Mode

Other

High-Z

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

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MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

Flash Electrical Specifications

NOTE:

1. Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.

2. Maximum DC voltage on V

may overshoot to +14V for periods < 20ns.

NOTE:

This parameter overrides the value given in the discrete Flash data sheet.

Table 6:

Absolute Maximum Ratings

PARAMETERS/CONDITIONS

MIN

MAX

UNITS

NOTES

Voltage to any ball except V

, V

Q, and V

-0.5

+2.45

Voltage

-0.2

+14

Supply Voltage

-0.2

+2.45

Q Supply Voltage

-0.2

+2.45

Output Short Circuit Current

100

Operating Temperature Range

-25

+85

°C

Storage Temperature Range

-55

+125

°C

Soldering Cycle

+260°C for 10s

Table 7:

Recommended Operating Conditions

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Operating Temperature

-25

+85

°C

Supply Voltage

1.70

1.95

I/O Supply Voltage

1.70

2.24

Input/Output Capacitance: DQs

4.0

6.5

Voltage

0.9

1.95

In-factory Programming Voltage

11.4

12.6

Block Erase Cycling (V

= V

)

100,000

Cycles

Block Erase Cycling (V

= V

)

1,000

Cycles

Time for V

at V

PPH

100

Hours

Table 8:

Capacitance

= +25

°C; f = 1 MHz

PARAMETER/CONDITION

SYMBOL

TYP

MAX

UNITS

Input Capacitance

TBD

Output Capacitance

OUT

TBD

Table 9:

AC Characteristics

PARAMETER

SYMBOL

-70/-60

UNITS

MIN

MAX

CE# hold from WE# HIGH

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80bcd58d

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

Table 10: DC Characteristics

Notes appear following table; all currents are in RMS unless otherwise noted

PARAMETER

CONDITIONS

SYM

MIN

TYP

MAX

UNITS NOTES

Input Low Voltage

0.4

Input High Voltage

Q - 0.4

Output Low Voltage
I

= 100µA

0.1

Output High Voltage
I

= -100µA

Q - 0.1

Lockout Voltage

F_V

PPLK

0.4

Lock

F_V

LKO

1.0

VccQ Lock

F_V

ILKOQ

TBD

Input Load Current

F_I

±1

µA

Output Leakage Current

F_I

±1

µA

Standby Current

with 32Mb PSRAM
with 64Mb PSRAM

F_I

CCS

140
150

µA

Asynchronous Read Current

F_I

CCR

TBD

Page Read Current

F_I

CCR

TBD

Burst Read Current

4-word Burst Read Current at 54 MHz
4-word Burst Read Current at 66 MHz

F_I

CCR

2
3

4
5

TBD

2, 3, 5

Burst Read Current

8-word Burst Read Current at 54 MHz
8-word Burst Read Current at 66 MHz

F_I

CCR

2
3

4
5

TBD

2, 3, 5

Burst Read Current

16-word Burst Read Current at 54 MHz
16-word Burst Read Current at 66 MHz

F_I

CCR

2
3

4
5

TBD

2, 3, 5

Continuous Burst Read Current

Continuous Burst Read Current at 54 MHz
Continuous Burst Read Current at 66 MHz

F_I

CCR

5
7

8
9

TBD

2, 3, 5

F_V

Program Current

F_V

= F_V

, Program in Progress

F_V

= F_V

, Program in Progress

F_I

CCW

25
15

F_V

Block Erase Current

F_V

= F_V

, Block Erase in Progress

F_V

= F_V

, Block Erase in Progress

F_I

CCE

30
15

F_V

Program Suspend Current

F_I

CCWS

µA

F_V

Erase Suspend Current

F_I

CCES

µA

F_V

Automatic Power Save Current

F_I

CCAPS

µA

F_V

Standby Current

F_V

Program Suspend Current

F_I

PPS

F_I

PPWS

0.2
0.2

5
5

µA

F_V

Erase Suspend Current

F_V

Read Current

F_I

PPES

F_I

PPR

0.2

µA

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80bcd58d

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

NOTE:

1. V

may decrease to -0.4V and V

may increase to V

Q + 0.3V for durations not to exceed 20ns.

2. APS mode reduces I

to approximately I

CCS

levels.

3. Test conditions: V

= V

(MAX), CE# = V

, OE# = V

. All other inputs = V

or V

4. I

CCES

and I

CCWS

values are valid when the device is deselected. Any READ operation performed while in suspend

mode will have an additional current draw of suspend current (I

CCES

or I

CCWS

5. Synchronous clock = 54 MHz/burst length = continuous is worst case for V

burst read current.

6. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current

required to drive output capacitance expected in the actual system.

7. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby

mode whenever all input signals are quiescent (not toggling), regardless of the state of CE#, UB#, and LB#. In order
to achieve low standby current all inputs must be either V

or V

F_V

Program Current

F_V

= F_V

, Program in Progress

F_V

= F_V

, Program in Progress

F_I

PPW

0.05

0.10

F_V

Erase Current

F_V

= F_V

, Erase in Progress

F_V

= F_V

, Erase in Progress

F_I

PPE

0.05

0.10

Read Operating Current

Asynchronous Random READ
Asynchronous Page READ

= V

or 0V

Chip Enabled,

OUT

= 0

PS_I

(-60)

25
15

(-70)

21
13

6, 7

Write Operating Current

= V

or 0V

Chip Enabled,

OUT

= 0

PS_I

(-60)
(-70)

25
21

6, 7

Table 10: DC Characteristics (continued)

Notes appear following table; all currents are in RMS unless otherwise noted

PARAMETER

CONDITIONS

SYM

MIN

TYP

MAX

UNITS NOTES

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80bcd58d

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

Table 11:

CFI

OFFSET

DATA

DESCRIPTION

2Ch

Manufacturer code

44C6h

Top boot block device code

44C7h

Bottom boot block device code

02 0F

reserved

Reserved

10, 11

0051, 0052

"QR"

0059

"Y"

13, 14

0003, 0000

Primary OEM command set

15, 16

0039, 0000

Address for primary extended table

17, 18

0000, 0000

Alternate OEM command set

19, 1A

0000, 0000

Address for OEM extended table

0017

MIN for Erase/Write; Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

0019

MAX for Erase/Write; Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

00B4

MIN for Erase/Write; Bit 7bit 4 volts in hex; Bit 3bit 0 100mV in BCD

00C6

MAX for Erase/Write; Bit 7bit 4 Volts in hex; Bit 3bit 0 100mV in BCD

0004

Typical timeout for single byte/word program, 2

µs, 0000 = not supported

0000

Typical timeout for maximum size multiple byte/word program, 2

µs, 0000 = not supported

000A

Typical timeout for individual block erase, 2

s, 0000 = not supported

0000

Typical timeout for full chip erase, 2

s, 0000 = not supported

0004

Maximum timeout for single byte/word program, 2

µs, 0000 = not supported

0000

Maximum timeout for maximum size multiple byte/word program, 2

µs, 0000 = not

supported

0002

Maximum timeout for individual block erase, 2

s, 0000 = not supported

0000

Maximum timeout for full chip erase, 2

s, 0000 = not supported

0017

Device size, 2

bytes

0001

Bus interface x8 = 0, x16 = 1, x32 = 2, x64 = 3

0000

Flash device interface description 0000 = async

2A, 2B

0000, 0000

Maximum number of bytes in multibyte program or page, 2

0002

Number of erase block regions within device (4K words and 32K words)

2D, 2E

007E, 0000

Top boot block device erase block region information 1

0007, 0000

Bottom boot block device erase block region information 1

2F, 30

0000, 0001

Top boot block device erase block region information 1

0020, 0000

Bottom boot block device erase block region information 1

31, 32

0007, 0000

Top boot block device erase block region information 2

007E, 0000

Bottom boot block device erase block region information 2

33, 34

0020, 0000

Top boot block device erase block region information 2

0000, 0001

Bottom boot block device erase block region information 2

35, 36

0000, 0000

Reserved for future erase block region information

37, 38

0000, 0000

Reserved for future erase block region information

39, 3A

0050, 0052

"PR"

0049

"I"

0031

Major version number, ASCII

0033

Minor version number, ASCII

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80bcd58d

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

3E
3F
40
41

00E6
0003
0000
0000

Optional Feature and Command Support
Bit 0 Chip erase supported no = 0
Bit 1 Suspend erase supported = yes = 1
Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes = 1
Bit 8 Synchronous read supported = no = 0
Bit 9 Simultaneous operation supported = yes = 1

0001

Program supported after erase suspend = yes

43, 44

0003, 0000

Bit 0 block lock status active = yes; Bit 1 block lock down active = yes

0018

supply optimum, 00 = not supported, Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

00C0

supply optimum, 00 = not supported, Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

0001

Number of protection register fields in JEDEC ID space

48, 49

0080, 0000

Lock bytes LOW address, lock bytes HIGH address

4A, 4B

0003, 0003

factory programmed bytes, 2

user programmable bytes

0004

Page mode read capability

0004

Number of synchronous mode read configuration fields that follow

0001

Synchronous mode read capability configuration 1

0002

Synchronous mode read capability configuration 2

0007

Synchronous mode read capability configuration 3

0000

Synchronous mode read capability configuration 4

Top: 0002

Number of device hardware partition regions within the device

Bot :0002

Top: 000F

Number of identical partitions within the partition region

Bot: 0001

Top: 0000

Number of identical partitions within the partition region

Bot: 0000

Top: 0011

Number of identical partitions within the partition region

Bot: 0011

Top: 0000

Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in program mode

Bot: 0000

Top: 0000

Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in erase mode

Bot: 0000

Top: 0001

Types of erase block regions in this partition region

Bot: 0002

Top: 0007

Partition region 1 erase block type 1 information

Bot: 0007

Top: 0000

Partition region 1 erase block type 1 information

Bot: 0000

Top: 0000

Partition region 1 erase block type 1 information

Bot: 0020

Top: 0001

Partition region 1 erase block type 1 information

Bot: 0000

Table 11:

CFI (continued)

OFFSET

DATA

DESCRIPTION

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80bcd58d

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

Top: 0064

Partition 1 (erase block type 1)

Bot: 0064

Top: 0000

Partition 1 (erase block type 1)

Bot: 0000

Top: 0001

Partition 1 (erase block type 1) bits per cell; internal ECC

Bot: 0001

Top: 0003

Partition 1 (erase block type 1) page mode and synchronous mode capabilities

Bot: 0003

Bot: 61

Partition region 1 erase block type 2 information

Bot: 0006

Bot: 62

Partition region 1 erase block type 2 information

Bot: 0000

Bot: 63

Partition region 1 erase block type 2 information

Bot: 0000

Bot: 64

Partition region 1 erase block type 2 information

Bot: 0001

Bot: 65

Partition region 1 (erase block type 2)

Bot: 0064

Bot: 66

Partition region 1 (erase block type 2)

Bot: 0000

Bot: 67

Partition region 1 (erase block type 2) bits per cell

Bot: 0001

Bot: 68

Partition region 1 (erase block type 2) page mode and synchronous mode capabilities

Bot: 0003

Top: 61

Top: 0001

Number of identical partitions within the partition region

Bot: 69

Bot: 000F

Top: 62

Top: 0000

Number of identical partitions within the partition region

Bot: 6A

Bot: 0000

Top: 63

Top: 0011

Number of PROGRAM/ERASE operations allowed in a partition

Bot: 6B

Bot: 0011

Top: 64

Top: 0000

Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in program mode

Bot: 6C

Bot: 0000

Top: 65

Top: 0000

Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in erase mode

Bot: 6D

Bot: 0000

Top: 66

Top: 0002

Types of erase block regions in this partition region

Bot: 6E

Bot: 0001

Top: 67

Top: 0006

Partition region 2 erase block type 1 information

Bot: 6F

Bot: 0007

Top: 68

Top: 0000

Partition region 2 erase block type 1 information

Bot: 70

Bot: 0000

Top: 69

Top: 0000

Partition region 2 erase block type 1 information

Bot: 71

Bot: 0000

Top: 6A

Top: 0001

Partition region 2 erase block type 1 information

Bot: 72

Bot: 0001

Table 11:

CFI (continued)

OFFSET

DATA

DESCRIPTION

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80bcd58d

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

Top: 6B

Top: 0064

Partition 2 (erase block type 1)

Bot: 73

Bot: 0064

Top: 6C

Top: 0000

Partition 2 (erase block type 1)

Bot: 74

Bot: 0000

Top: 6D

Top: 0001

Partition 2 (erase block type 1) bits per cell

Bot: 75

Bot: 0001

Top: 6E

Top: 0003

Partition 2 (erase block type 1) page mode and synchronous mode capabilities

Bot: 76

Bot: 0003

Top: 6F

Top: 0007

Partition region 2 erase block type 2 information

Top: 70

Top: 0000

Partition region 2 erase block type 2 information

Top: 71

Top: 0020

Partition region 2 erase block type 2 information

Top: 72

Top: 0000

Partition region 2 erase block type 2 information

Top: 73

Top: 0064

Partition 2 (erase block type 2)

Top: 74

Top: 0000

Partition 2 (erase block type 2)

Top: 75

Top: 0001

Partition 2 (erase block type 2) bits per cell

Top: 76

Top: 0003

Partition 2 (erase block type 2) page mode and synchronous mode capabilities

TBD

32Mb: 0020

PSRAM Density

64Mb: 0040

79 7H

Reserved

Table 11:

CFI (continued)

OFFSET

DATA

DESCRIPTION

256Mb MULTIBANK BURST FLASH

32Mb/64Mb ASYNC/PAGE CellularRAM COMBO

ADVANCE

09005aef80bcd58d

Micron Technology, Inc., reserves the right to change products or specifications without notice..

MT28C256564W18S_A.fm - Rev. A, Pub 6/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S.

All other trademarks are the property of their respective owners.

Figure 5: 88-Ball FBGA

NOTE:

1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.

Data Sheet Designation

Advance:

This data sheet contains initial descriptions of products still under development.

For additional documentation concerning Flash and CellularRAM features, functional descriptions, program-

ming, and timing, please refer to the MT28F644W18 data sheet at

www.micron.com/flash

and the

MT45W2MW16FPA and MT45W4MW16FPA data sheets at

http://www.micron.com/cellularram

BALL A1 ID

BALL A1

BALL A8

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

1.40 MAX

0.25 ±0.05

SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø 0.30mm SOLDER MASK DEFINED

5.60

9.00 ±0.10

2.80 ±0.05

4.50 ±0.05

8.80

4.40 ±0.05

6.00 ±0.05

12.00 ±0.10

88X 0.35

SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE
PRE-REFLOW DIAMETER
IS Ø 0.35

SEATING PLANE

1.025 ±0.075

0.10 C

0.80
TYP

0.10

(4X)

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