Document Outline

Features/Options
Ball Assignment, 67-Ball FBGA (Top View)
General Description
Architecture and Memory Organization
Device Marking
- Table 1, Cross Reference for Abbreviated Device Marks
Part Numbering Information
- Figure 1, Part Number Chart
- Table 2, Valid Part Number Combinations
Block Diagram
Flash Functional Block Diagram
Ball Descriptions
Ball Descriptions (continued)
Truth Table - Flash
Truth Table - SRAM
Figure 2, Bottom Boot Block Device
Figure 3, Top Boot Block Device
Flash Memory Operating Modes
- Command State Machine
- Operations
- Command Definition
- Status Register
- Table 3, Command State Machine Codes For Device Mode Selection
- Command State Machine Operations
- Table 4, Command Definitions
- Table 5, Command Descriptions
- Table 5, Command Descriptions (conrinued)
- CLEAR STATUS REGISTER
READ Operations
- Read Array
- Read Chip Protection Identification Data
- Read Query
- Read Status Register
Table 6, Command State Machine Transition Table
- Table 6, Command State Machine Transition Table (continued)
- Table 6, Command State Machine Transition Table (continued)
- Table 6, Command State Machine Transition Table (continued)
- Table 6, Command State Machine Transition Table (continued)
Table 7, Bus Operations
Programming Operations
- PROGRAM SETUP Command
- Accelerated Programming Algorithm
ERASE Operations
Table 8, Status Register Bit Definition
Figure 4, Automated Word Programming Flowchart
Figure 5, PROGRAM SUSPEND/ PROGRAM RESUME Flowchart
Figure 6, Accelerated Program Algorithm Flowchart
Figure 7, BLOCK ERASE Flowchart
Figure 8, ERASE SUSPEND/ERASE RESUME Flowchart
Figure 9, CHECK BLOCK ERASE Flowchart
READ-While-WRITE/ERASE Concurrency
- Figure 10, READ-While-WRITE Concurrency
Block Locking
- Locked State
- Unlocked State
- Table 9, Block Locking State Transition
- Locked Down State
- Reading a Block's Lock Status
- Locking Operations During ERASE SUSPEND
- Status Register Error Checking
Chip Protection Register
- Reading the Chip Protection Register
- Figure 12, Protection Register Memory Map
Table 10, Chip Configuration Addressing
Page Read Mode
Asynchronous READ Cycle
Standby Mode
Automatic Power Save (APS) Mode
Deep Power-Down Mode
F_VPP/F_VCC Program and Erase Voltages
- Table 11, F_VPP Ranges (V)
Device Reset
Power-Up Sequence
Flash Electrical Specifications
- Flash Timing Diagrams
  - Two-Cycle PROGRAMMING/ERASE Operation
  - Single Asynchronous READ Operation
  - Single Asynchronous Page Mode READ Operation
  - Reset Operation
- Table 12, CFI
  - Table 12, CFI (continued)
- Absolute Maximum Ratings
- Recommended Operating Conditions
- Figure 13, AC Input/Output Reference Waveform
- Figure 14, Output Load Circuit
- Combined DC Charactersitics
  - Combined DC Charactersitics (continued)
- Capacitance
- Flash READ Cycle Timing Requirements
- Flash WRITE Cycle Timing Requirements
- Flash ERASE and PROGRAM Cycle Timing Requirements
SRAM Operating Modes
- SRAM Read Array
- SRAM Write Array
- SRAM Functional Block Diagram
- Timing Test Conditions
- SRAM READ Cycle Timing
- SRAM WRITE Cycle Timing
- SRAM Timing Diagrams
  - READ Cycle 1
  - READ Cycle 2
  - WRITE Cycle
  - WRITE Cycle 2
67-Ball FBGA Package Drawing

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE

SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S

PRODUCTION DATA SHEET SPECIFICATIONS.

FLASH AND SRAM
COMBO MEMORY

MT28C6428P20
MT28C6428P18

Low Voltage, Extended Temperature
0.18µm Process Technology

FEATURES

· Flexible dual-bank architecture
· Support for true concurrent operations with no

latency:

Read bank b during program bank a and vice versa
Read bank b during erase bank a and vice versa

· Organization: 4,096K x 16 (Flash)

512K x 16 (SRAM)

· Basic configuration:

Flash

Bank a (16Mb Flash for data storage)
Eight 4K-word parameter blocks
Thirty-one 32K-word blocks
Bank b (48Mb Flash for program storage)
Ninety-six 32K-word main blocks

SRAM

8Mb SRAM for data storage
512K-words

· F_V

, V

Q, F_V

, S_V

voltages

MT28C6428P20

1.80V (MIN)/2.20V (MAX) F_V

read voltage

1.80V (MIN)/2.20V (MAX) S_V

read voltage

1.80V (MIN)/2.20V (MAX) V

MT28C6428P18

1.70V (MIN)/1.90V (MAX) F_V

read voltage

1.70V (MIN)/1.90V (MAX) S_V

read voltage

1.70V (MIN)/1.90V (MAX) V

MT28C6428P20/P18

1.80V (TYP) F_V

(in-system PROGRAM/ERASE)

1.0V (MIN) S_V

(SRAM data retention)

12V ±5% (HV) F_V

(in-house programming and

accelerated programming algorithm [APA]
activation)

· Asynchronous access time

Flash access time: 80ns @ 1.80V F_V

SRAM access time: 80ns @ 1.80V S_V

· Page Mode read access

Interpage read access: 80ns @ 1.80V F_V

Intrapage read access: 30ns @ 1.80V F_V

· Low power consumption
· Enhanced suspend options

ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank

· Read/Write SRAM during program/erase of Flash

· Dual 64-bit chip protection registers for security

purposes

· PROGRAM/ERASE cycles

100,000 WRITE/ERASE cycles per block

· Cross-compatible command set support

Extended command set
Common flash interface (CFI) compliant

OPTIONS

MARKING

· Timing

80ns

-80

85ns

-85

· Boot Block Configuration

Top

Bottom

· Operating Voltage Range

F_V

= 1.70V1.90V

F_V

= 1.80V2.20V

· Operating Temperature Range

Commercial (0

C to +70

None

Extended (-40

C to +85

· Package

67-ball FBGA (8 x 8 grid)

Part Number Example:

MT28C6428P20FM-80 BET

BALL ASSIGNMENT

67-Ball FBGA (Top View)

1 2 3 4 5 6 7 8 9 10 11

Top View

(Ball Down)

A14

DQ11

A15

A10

A21

A19

S_OE#

A20

A16

F_WE#

VSS

F_WP#

S_LB#

A18

F_VCC

A12

S_WE#

DQ6

S_CE2

DQ10

DQ8

F_VSS

DQ14

DQ4

S_VCC

DQ2

DQ0

F_OE#

VccQ

DQ7

DQ5

F_VCC

DQ3

DQ1

S_CE1#

A13

DQ15

DQ13

DQ12

DQ9

F_CE#

A11

F_RP#

F_VPP

S_UB#

A17

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Table 1

Cross Reference for Abbreviated Device Marks

PRODUCT

SAMPLE

MECHANICAL

PART NUMBER

MARKING

SAMPLE MARKING

MT28C6428P20FM-80 BET

FW454

FX454

FY454

MT28C6428P20FM-80 TET

FW453

FX453

FY453

MT28C6428P18FM-85 BET

FW455

FX455

FY455

MT28C6428P18FM-85 TET

FW452

FX452

FY452

GENERAL DESCRIPTION

The MT28C6428P20 and MT28C6428P18 combi-

nation Flash and SRAM memory devices provide a com-
pact, low-power solution for systems where PCB real
estate is at a premium. The dual-bank Flash devices
are high-performance, high-density, nonvolatile
memory with a revolutionary architecture that can sig-
nificantly improve system performance.

This new architecture features:
· A two-memory-bank configuration supporting

dual-bank operation;

· A high-performance bus interface providing a fast

page data transfer; and

· A conventional asynchronous bus interface.
The devices also provide soft protection for blocks

by configuring soft protection registers with dedicated
command sequences. For security purposes, dual 64-
bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state
machine (WSM). The WSM simplifies these operations
and relieves the system processor of secondary tasks.
An on-chip status register, one for each bank, can be
used to monitor the WSM status to determine the
progress of a PROGRAM/ERASE command.

The erase/program suspend functionality allows

compatibility with existing EEPROM emulation soft-
ware packages.

The devices take advantage of a dedicated power

source for the Flash memory (F_V

) and a dedicated

power source for the SRAM (S_V

), both at 1.70V2.20V

for optimized power consumption and improved noise
immunity. A dedicated I/O power supply (V

Q) is pro-

vided with an extended range (1.70V2.20V), to allow a
direct interface to most common logic controllers and
to ensure improved noise immunity. The separate
S_V

pin for the SRAM provides data retention capa-

bility when required. The data retention S_V

is speci-

fied as low as 1.0V. The MT28C6428P20 and
MT28C6428P18 devices support two F_V

voltage

ranges, an in-circuit voltage of 0.9V2.2V and a produc-
tion compatibility voltage of 12V ±5%. The 12V ±5%
F_V

is supported for a maximum of 100 cycles and 10

cumulative hours.

The MT28C6428P20 and MT28C6428P18 contain

an asynchronous 8Mb SRAM organized as 512K-words
by 16 bits. The devices are fabricated using an ad-
vanced CMOS process and high-speed/ultra-low-
power circuit technology, and then are packaged in a
67-ball FBGA package with 0.80mm pitch.

ARCHITECTURE AND MEMORY
ORGANIZATION

The Flash devices contain two separate banks of

memory (bank a and bank b) for simultaneous READ
and WRITE operations, which are available in the fol-
lowing bank segmentation configuration:

· Bank a comprises one-fourth of the memory and

contains 8 x 4K-word parameter blocks, while the
remainder of bank a is split into 31 x 32K-word
blocks.

· Bank b represents three-fourths of the memory, is

equally sectored, and contains 96 x 32K-word
blocks.

Figures 2 and 3 show the bottom and top memory

organizations.

DEVICE MARKING

Due to the size of the package, Micron's standard

part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

PART NUMBERING INFORMATION

Micron's low-power devices are available with sev-

eral different combinations of features (see Figure 1).

Table 2

Valid Part Number Combinations

BOOT BLOCK

OPERATING

ACCESS

STARTING

TEMPERATURE

PART NUMBER

TIME (ns)

ADDRESS

RANGE

MT28C6428P20FM-80 BET

Bottom

-40

C to +85

MT28C6428P20FM-80 TET

Top

-40

C to +85

MT28C6428P18FM-85 BET

Bottom

-40

C to +85

MT28C6428P18FM-85 TET

Top

-40

C to +85

NOTE: 1. For part number combinations not listed in this table, please contact

your Micron representative.

Figure 1

Part Number Chart

Valid combinations of features and their correspond-
ing part numbers are listed in Table 2.

MT 28C 642 8 P 20 FM-80 T ET

Micron Technology

Flash Family

28C = Dual-Supply Flash/SRAM Combo

Density/Organization/Banks

642 = 64Mb (4,096K x 16)
bank a = 1/4; bank b = 3/4

SRAM Density

8 = 8Mb SRAM (512K x 16)

Access Time

-80 = 80ns
-85 = 85ns

Read Mode Operation

P = Asynchronous/Page Read

Package Code

FM = 67-ball FBGA (8 x 8 grid)

Operating Temperature Range

None = Commercial (0ºC to +70ºC)
ET = Extended (-40ºC to +85ºC)

Boot Block Starting Address

B = Bottom boot
T = Top boot

Operating Voltage Range

20 = 1.80V2.20V V

18 = 1.70V1.90V

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

BALL DESCRIPTIONS

67-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

H6, G9, G8, G7,

A0A21

Input

Address Inputs: Inputs for the addresses during READ and WRITE

H5, H4, G6, G5,

operations. Addresses are internally latched during READ and WRITE

B4, B6, B5, A4,

cycles. Flash: A0A21; SRAM: A0A18.

A8, A7, A6, A5,

B3, G4, G3, E5,

A3, C5

F_CE#

Input

Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,
the device is disabled and goes into standby power mode.

F_OE#

Input

Flash Output Enable: Enables Flash output buffers when LOW. When
F_OE# is HIGH, the output buffers are disabled.

F_WE#

Input

Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.
F_WE# is active LOW.

F_RP#

Input

Reset. When F_RP# is a logic LOW, the device is in reset, which drives
the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,
the device is in standard operation. When F_RP# transitions from logic
LOW to logic HIGH, the device resets all blocks to locked and defaults to
the read array mode.

F_WP#

Input

Flash Write Protect. Controls the lock down function of the flexible
locking feature.

G10

S_CE1#

Input

SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.

S_CE2

Input

SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.

S_OE#

Input

SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.

S_WE#

Input

SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.
S_WE# is active LOW.

S_LB#

Input

SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0DQ7).

S_UB#

Input

SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8DQ15).

F9, F10, E9,

DQ0DQ15

Input/

Data Inputs/Outputs: Input array data on the second CE# and WE#

E10, C9, C10,

Output

cycle during PROGRAM command. Input commands to the command

C8, B10, F8,

user interface when CE# and WE# are active. Output data when CE#

F7, E8, E6, D7,

and OE# are active.

C7, B9, B7

(continued on next page)

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

BALL DESCRIPTIONS (continued)

67-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

F_V

Input/

Flash Program/Erase Power Supply: [0.9V2.2V or 11.4V12.6V].

Supply

Operates as input at logic levels to control complete device protection.
Provides backward compatibility for factory programming when driven
to 11.4V12.6V. A lower F_V

voltage range (0.0V2.2V) is available.

Contact factory for more information.

D10, H3

F_V

Supply

Flash Power Supply: [1.70V1.90V or 1.80V2.20V]. Supplies power for
device operation.

A9, H8

F_V

Supply

Flash Specific Ground: Do not float any ground ball.

S_V

Supply

SRAM Power Supply: [1.70V1.90V or 1.80V2.20V]. Supplies power for
device operation.

S_V

Supply

SRAM Specific Ground: Do not float any ground ball.

A10

Supply

I/O Power Supply: [1.701.90V or 1.80V2.20V].

A1, A2, A11,

No Connect: Lead is not internally connected; it may be driven or

A12, C4, H1,

floated.

H2, H10, H11,

H12

C6, D5, D6,

Contact balls not mounted; corresponding position on PCB can be used

E7, F6

to reduce routing complexity.

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

NOTE: 1. Two devices may not drive the memory bus at the same time.

2. Allowable Flash read modes include read array, read query, read configuration, and read status.
3. Outputs are dependent on a separate device controlling bus outputs.
4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.
5. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2.
6. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to

control the bus outputs at a time.

7. Data output on lower byte only; upper byte High-Z.
8. Data output on upper byte only; lower byte High-Z.
9. Data input on lower byte only.

10. Data input on upper byte only.

TRUTH TABLE FLASH

FLASH SIGNALS

SRAM SIGNALS

MEMORY OUPUT

MODES

F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#

MEMORY

DQ0DQ15

NOTES

BUS CONTROL

Read

SRAM must be High-Z

Flash

OUT

1, 2, 3

Write

Flash

Standby

Other

High-Z

Output Disable

SRAM any mode allowable

Other

High-Z

4, 5

Reset

Other

High-Z

4, 6

TRUTH TABLE SRAM

FLASH SIGNALS

SRAM SIGNALS

MEMORY OUPUT

MODES

F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#

MEMORY

DQ0DQ15

NOTES

BUS CONTROL

Read

DQ0DQ15

SRAM

OUT

1, 3

DQ0DQ7

SRAM

OUT

DQ8DQ15

Flash must be High-Z

SRAM

OUT

Write

DQ0DQ15

SRAM

1, 3

DQ0DQ7

SRAM

DQ8DQ15

SRAM

Standby

Other

High-Z

Flash any mode allowable

Other

High-Z

Output Disable

Other

High-Z

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Figure 2

Bottom Boot Block Device

Bank a = 16Mb

Block

Block Size

Address Range

(K-bytes/

(x16)

K-words)

64/32

0F8000h0FFFFFh

64/32

0F0000h0F7FFFh

64/32

0E8000h0EFFFFh

64/32

0E0000h0E7FFFh

64/32

0D8000h0DFFFFh

64/32

0D0000h0D7FFFh

64/32

0C8000h0CFFFFh

64/32

0C0000h0C7FFFh

64/32

0B8000h0BFFFFh

64/32

0B0000h0B7FFFh

64/32

0A8000h0AFFFFh

64/32

0A0000h0A7FFFh

64/32

098000h097FFFh

64/32

090000h097FFFh

64/32

088000h087FFFh

64/32

080000h087FFFh

64/32

078000h07FFFFh

64/32

070000h077FFFh

64/32

068000h067FFFh

64/32

060000h067FFFh

64/32

058000h05FFFFh

64/32

050000h057FFFh

64/32

048000h04FFFFh

64/32

040000h047FFFh

64/32

038000h03FFFFh

64/32

030000h037FFFh

64/32

028000h02FFFFh

64/32

020000h027FFFh

64/32

018000h01FFFFh

64/32

010000h017FFFh

64/32

008000h00FFFFh

8/4

007000h007FFFh

8/4

006000h006FFFh

8/4

005000h005FFFh

8/4

004000h004FFFh

8/4

003000h003FFFh

8/4

002000h002FFFh

8/4

001000h001FFFh

8/4

000000h000FFFh

Bank b = 48Mb

Block

Block Size

Address Range

(K-bytes/

(x16)

K-words)

134

64/32

3F8000h3FFFFFh

133

64/32

3F0000h3F7FFFh

132

64/32

3E8000h3EFFFFh

131

64/32

3E0000h3E7FFFh

130

64/32

3D8000h3DFFFFh

129

64/32

3D0000h3D7FFFh

128

64/32

3C8000h3CFFFFh

127

64/32

3C0000h3C7FFFh

126

64/32

3B8000h3BFFFFh

125

64/32

3B0000h3B7FFFh

124

64/32

3A8000h3AFFFFh

123

64/32

3A0000h3A7FFFh

122

64/32

398000h39FFFFh

121

64/32

390000h397FFFh

120

64/32

388000h38FFFFh

119

64/32

380000h387FFFh

118

64/32

378000h37FFFFh

117

64/32

370000h377FFFh

116

64/32

368000h36FFFFh

115

64/32

360000h367FFFh

114

64/32

358000h35FFFFh

113

64/32

350000h357FFFh

112

64/32

348000h34FFFFh

111

64/32

340000h347FFFh

110

64/32

338000h33FFFFh

109

64/32

330000h337FFFh

108

64/32

328000h32FFFFh

107

64/32

320000h327FFFh

106

64/32

318000h31FFFFh

105

64/32

310000h317FFFh

104

64/32

308000h30FFFFh

103

64/32

300000h307FFFh

102

64/32

2F8000h2FFFFFh

101

64/32

2F0000h2F7FFFh

100

64/32

2E8000h2EFFFFh

64/32

2E0000h2E7FFFh

64/32

2D8000h2DFFFFh

64/32

2D0000h2D7FFFh

64/32

2C8000h2CFFFFh

64/32

2C0000h2C7FFFh

64/32

2B8000h2BFFFFh

64/32

2B0000h2B7FFFh

64/32

2A8000h2AFFFFh

64/32

2A0000h2A7FFFh

64/32

298000h29FFFFh

64/32

290000h297FFFh

64/32

288000h28FFFFh

64/32

280000h287FFFh

Bank b = 48Mb

Block

Block Size

Address Range

(K-bytes/

(x16)

K-words)

64/32

278000H27FFFFh

64/32

270000h277FFFh

64/32

268000h26FFFFh

64/32

260000h267FFFh

64/32

258000h25FFFFh

64/32

250000h257FFFh

64/32

248000h24FFFFh

64/32

240000h247FFFh

64/32

238000h23FFFFh

64/32

230000h237FFFh

64/32

228000h22FFFFh

64/32

220000h227FFFh

64/32

218000h21FFFFh

64/32

210000h217FFFh

64/32

208000h20FFFFh

64/32

200000h207FFFh

64/32

1F8000h1FFFFFh

64/32

1F0000h1F7FFFh

64/32

1E8000h1EFFFFh

64/32

1E0000h1E7FFFh

64/32

1D8000h1DFFFFh

64/32

1D0000h1D7FFFh

64/32

1C8000h1CFFFFh

64/32

1C0000h1C7FFFh

64/32

1B8000h1BFFFFh

64/32

1B0000h1B7FFFh

64/32

1A8000h1AFFFFh

64/32

1A0000h1A7FFFh

64/32

198000h19FFFFh

64/32

190000h197FFFh

64/32

188000h18FFFFh

64/32

180000h187FFFh

64/32

178000h17FFFFh

64/32

170000h177FFFh

64/32

168000h16FFFFh

64/32

160000h167FFFh

64/32

158000h15FFFFh

64/32

150000h157FFFh

64/32

148000h14FFFFh

64/32

140000h147FFFh

64/32

138000h13FFFFh

64/32

130000h137FFFh

64/32

128000h12FFFFh

64/32

120000h127FFFh

64/32

118000h11FFFFh

64/32

110000h117FFFh

64/32

108000h10FFFFh

64/32

100000h107FFFh

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Figure 3

Top Boot Block Device

Bank a = 16Mb

Block

Block Size

Address Range

(K-bytes/

(x16)

K-words)

134

8/4

3FF000h3FFFFFh

133

8/4

3FE000h3FEFFFh

132

8/4

3FD000h3FDFFFh

131

8/4

3FC000h3FCFFFh

130

8/4

3FB000h3FBFFFh

129

8/4

3FA000h3FAFFFh

128

8/4

3F9000h3F9FFFh

127

8/4

3F8000h3F8FFFh

126

64/32

3F0000h3F7FFFh

125

64/32

3E8000h3EFFFFh

124

64/32

3E0000h3E7FFFh

123

64/32

3D8000h3DFFFFh

122

64/32

3D0000h3D7FFFh

121

64/32

3C8000h3CFFFFh

120

64/32

3C0000h3C7FFFh

119

64/32

3B8000h3BFFFFh

118

64/32

3B0000h3B7FFFh

117

64/32

3A8000h3AFFFFh

116

64/32

3A0000h3A7FFFh

115

64/32

398000h39FFFFh

114

64/32

390000h397FFFh

113

64/32

388000h38FFFFh

112

64/32

380000h387FFFh

111

64/32

378000h37FFFFh

110

64/32

370000h377FFFh

109

64/32

368000h36FFFFh

108

64/32

360000h367FFFh

107

64/32

358000h35FFFFh

106

64/32

350000h357FFFh

105

64/32

348000h34FFFFh

104

64/32

340000h347FFFh

103

64/32

338000h33FFFFh

102

64/32

330000h337FFFh

101

64/32

328000h32FFFFh

100

64/32

320000h327FFFh

64/32

318000h31FFFFh

64/32

310000h317FFFh

64/32

308000h30FFFFh

64/32

300000h307FFFh

Bank b = 48Mb

Block

Block Size

Address Range

(K-bytes/

(x16)

K-words)

64/32

2F8000h2FFFFFh

64/32

2F0000h2F7FFFh

64/32

2E8000h2EFFFFh

64/32

2E0000h2E7FFFh

64/32

2D8000h2DFFFFh

64/32

2D0000h2D7FFFh

64/32

2C8000h2CFFFFh

64/32

2C0000h2C7FFFh

64/32

2B8000h2BFFFFh

64/32

2B0000h2B7FFFh

64/32

2A8000h2AFFFFh

64/32

2A0000h2A7FFFh

64/32

298000h29FFFFh

64/32

290000h297FFFh

64/32

288000h28FFFFh

64/32

280000h287FFFh

64/32

278000h27FFFFh

64/32

270000h277FFFh

64/32

268000h26FFFFh

64/32

260000h267FFFh

64/32

258000h25FFFFh

64/32

250000h257FFFh

64/32

248000h24FFFFh

64/32

240000h247FFFh

64/32

238000h23FFFFh

64/32

230000h237FFFh

64/32

228000h22FFFFh

64/32

220000h227FFFh

64/32

218000h21FFFFh

64/32

210000h217FFFh

64/32

208000h20FFFFh

64/32

200000h207FFFh

64/32

1F8000h1FFFFFh

64/32

1F0000h1F7FFFh

64/32

1E8000h1EFFFFh

64/32

1E0000h1E7FFFh

64/32

1D8000h1DFFFFh

64/32

1D0000h1D7FFFh

64/32

1C8000h1CFFFFh

64/32

1C0000h1C7FFFh

64/32

1B8000h1BFFFFh

64/32

1B0000h1B7FFFh

64/32

1A8000h1AFFFFh

64/32

1A0000h1A7FFFh

64/32

198000h19FFFFh

64/32

190000h197FFFh

64/32

188000h18FFFFh

64/32

180000h187FFFh

Bank b = 48Mb

Block

Block Size

Address Range

(K-bytes/

(x16)

K-words)

64/32

178000h17FFFFh

64/32

170000h177FFFh

64/32

168000h16FFFFh

64/32

160000h167FFFh

64/32

158000h15FFFFh

64/32

150000h157FFFh

64/32

148000h14FFFFh

64/32

140000h147FFFh

64/32

138000h13FFFFh

64/32

130000h137FFFh

64/32

128000h12FFFFh

64/32

120000h127FFFh

64/32

118000h11FFFFh

64/32

110000h117FFFh

64/32

108000h10FFFFh

64/32

100000h107FFFh

64/32

0F8000h0FFFFFh

64/32

0F0000h0F7FFFh

64/32

0E8000h0EFFFFh

64/32

0E0000h0E7FFFh

64/32

0D8000h0DFFFFh

64/32

0D0000h0D7FFFh

64/32

0C8000h0CFFFFh

64/32

0C0000h0C7FFFh

64/32

0B8000h0BFFFFh

64/32

0B0000h0B7FFFh

64/32

0A8000h0AFFFFh

64/32

0A0000h0A7FFFh

64/32

098000h09FFFFh

64/32

090000h097FFFh

64/32

088000h08FFFFh

64/32

080000h087FFFh

64/32

078000h07FFFFh

64/32

070000h077FFFh

64/32

068000h06FFFFh

64/32

060000h067FFFh

64/32

058000h05FFFFh

64/32

050000h057FFFh

64/32

048000h04FFFFh

64/32

040000h047FFFh

64/32

038000h03FFFFh

64/32

030000h037FFFh

64/32

028000h02FFFFh

64/32

020000h027FFFh

64/32

018000h01FFFFh

64/32

010000h017FFFh

64/32

008000h00FFFFh

64/32

000000h007FFFh

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

FLASH MEMORY OPERATING MODES

COMMAND STATE MACHINE

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 3,
their definitions are given in Table 4 and their descrip-
tions in Table 5. Program and erase algorithms are au-
tomated by the on-chip WSM. Table 7 shows the CSM
transition states.

Once a valid PROGRAM/ERASE command is en-

tered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally. A command is valid only if the
exact sequence of WRITEs is completed. After the WSM
completes its task, the write state machine status
(WSMS) bit (SR7) (see Table 8) is set to a logic HIGH
level (V

), allowing the CSM to respond to the full com-

mand set again.

OPERATIONS

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/Os DQ0DQ7. The number of bus cycles required to
activate a command is typically one or two. The first
operation is always a WRITE. Control signals F_CE#
and F_WE# must be at a logic LOW level (V

), and F_OE#

and F_RP# must be at logic HIGH (V

). The second

operation, when needed, can be a WRITE or a READ
depending upon the command. During a READ opera-
tion, control signals F_CE# and F_OE# must be at a
logic LOW level (V

), and F_WE# and F_RP# must be at

logic HIGH (V

Table 7 illustrates the bus operations for all the

modes: write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of opera-
tion. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two Flash memory partitions, an on-chip status
register is available. These two registers allow the moni-
toring of the progress of various operations that can
take place on a memory bank. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specify-
ing an address within the memory partition boundary,
and reading the register data on I/O pins DQ0DQ7
(cycle 2). Status register bits SR0-SR7 correspond to
DQ0DQ7 (see Table 8).

COMMAND DEFINITION

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 4 for the CSM command defini-
tions and data for each of the bus cycles.

STATUS REGISTER

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling F_OE# and F_CE# and reading the result-
ing status code on I/Os DQ0DQ7. The high-order I/Os
(DQ8DQ15) are set to 00h internally, so only the low-
order I/Os (DQ0DQ7) need to be interpreted. Address
lines select the status register pertinent to the selected
memory partition.

Table 3

Command State Machine Codes For

Device Mode Selection

COMMAND

DQ0DQ7

CODE ON DEVICE MODE

10h

Accelerated Programming Algorithm
(APA)

20h

Block erase setup

40h

Program setup

50h

Clear status register

60h

Protection configuration setup

60h

Enable/disable deep power-down

70h

Read status register

90h

Read protection configuration
register

98h

Read query

B0h

Program/erase suspend

C0h

Protection register program/lock

D0h

Program/erase resume erase
confirm

D1h

Check block erase confirm

FFh

Read array

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

edge of F_OE# or F_CE#, whichever occurs last. The
latest falling edge of either of these two signals up-
dates the latch within a given READ cycle. Latching the
data prevents errors from occurring if the register input
changes during a status register read.

The status register provides the internal state of the

WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 8 defines the sta-
tus register bits.

After monitoring the status register during a

PROGRAM/ERASE operation, the data appearing on
DQ0DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.

COMMAND STATE MACHINE OPERATIONS

The CSM decodes instructions for the commands

listed in Table 3. The 8-bit command code is input to
the device on DQ0DQ7 (see Table 4 for command
definitions). During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE cycle
has been requested.

During a PROGRAM cycle, the WSM controls the

program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.

During an ERASE cycle, the CSM responds to an

ERASE SUSPEND command only. When the WSM has
completed its task, the WSMS bit (SR7) is set to a logic
HIGH level and the CSM responds to the full command
set. The CSM stays in the current command state until
the microprocessor issues another command.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when F_V

is within its correct

voltage range.

Table 4

Command Definitions

FIRST BUS CYCLE

SECOND BUS CYCLE

COMMAND

OPERATION ADDRESS

DATA

OPERATION ADDRESS

DATA

READ ARRAY

WRITE

FFh

READ PROTECTION CONFIGURATION REGISTER

WRITE

90h

READ

READ STATUS REGISTER

WRITE

70h

READ

SRD

CLEAR STATUS REGISTER

WRITE

50h

READ QUERY

WRITE

98h

READ

BLOCK ERASE SETUP

WRITE

20h

WRITE

D0h

PROGRAM SETUP

WRITE

40h

WRITE

ACCELERATED PROGRAMMING ALGORITHM (APA)

WRITE

10h

WRITE

PROGRAM/ERASE SUSPEND

WRITE

B0h

PROGRAM/ERASE RESUME ERASE CONFIRM

WRITE

D0h

LOCK BLOCK

WRITE

60h

WRITE

01h

UNLOCK BLOCK

WRITE

60h

WRITE

D0h

LOCK DOWN BLOCK

WRITE

60h

WRITE

2Fh

CHECK BLOCK ERASE

WRITE

20h

WRITE

D1h

PROTECTION REGISTER PROGRAM

WRITE

C0h

WRITE

PROTECTION REGISTER LOCK

WRITE

LPA

C0h

WRITE

LPA

FFFDh

ENABLE/DISABLE DEEP POWER-DOWN

WRITE

DPW

60h

WRITE

DPW

03h

NOTE: 1. BA:

Address within the block

DPW: BBCFh = Disable deep power-down

BBDFh = Enable deep power-down

IA:

Identification code address

ID:

Identification code data

LPA: Lock protection register address
PA:

Protection register address

PD:

Data to be written at location PA

QA: Query code address
QD: Query code data
SRD: Data read from the status register
WA: Word address of memory location to be written, or read
WD: Data to be written at the location WA
X:

"Don't Care"

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Table 5

Command Descriptions

CODE DEVICE MODE

BUS CYCLE

DESCRIPTION

10h

APA

First

Prepares for an accelerated program operation.

20h

Erase Setup

First

Prepares the CSM for the ERASE command. If the next command is
not a CHECK BLOCK ERASE OR ERASE CONFIRM command, the
command will be ignored, and the device will go to read status
mode and wait for another command.

40h

Program Setup

First

A two-cycle command: The first cycle prepares for a PROGRAM
operation, the second cycle latches addresses and data and initiates
the WSM to execute the program algorithm. The Flash outputs status
register data on the falling edge of F_OE# or F_CE#, whichever
occurs first.

50h

Clear Status

First

The WSM can set the program status (SR4), and erase status (SR5) bits

in the status register to "1," but it cannot clear them to "0." Issuing
this command clears those bits to "0."

60h

Protection

First

Prepares the CSM for changes to the block locking status. If the next

Configuration

command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK

Setup

DOWN, the command will be ignored, and the device will go to read
status mode.

Set Read

First

Puts the device into the set read configuration mode so that it will be

Configuration

possible to set the option bits related to burst read mode.

70h

Read Status

First

Places the device into read status register mode. Reading the device

outputs the contents of the status register for the addressed bank.
The device automatically enters this mode for the addressed bank
after a PROGRAM or ERASE operation has been initiated.

90h

Read Protection

First

Puts the device into the read protection configuration mode so that

Configuration

reading the device outputs the manufacturer/device codes or block
lock status.

98h

Read Query

First

Puts the device into the read query mode so that reading the device
outputs common Flash interface information.

B0h

Program Suspend

First

Suspends the currently executing PROGRAM/ERASE/CHECK BLOCK
ERASE operation. The status register indicates when the operation

Erase Suspend

First

has been successfully suspended by setting either the program
suspend (SR2) or erase suspend (SR6) and the WSMS bit (SR7) to a

Check Block

First

"1" (ready). The WSM continues to idle in the suspend state,

Erase Suspend

regardless of the state of all input control pins except F_RP#, which
immediately shuts down the WSM and the remainder of the chip if
F_RP# is driven to V

C0h

Program Device

First

Writes a specific code into the device protection register.

Protection Register

Lock Device

First

Locks the device protection register; data can no longer be changed.

Protection Register

(continued on the next page)

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Table 5

Command Descriptions (continued)

CODE DEVICE MODE

BUS CYCLE

DESCRIPTION

D0h

Erase Confirm

Second

If the previous command was an ERASE SETUP command, then the
CSM closes the address and data latches, and it begins erasing the
block indicated on the address pins. During programming/erase, the
device responds only to the READ STATUS REGISTER, PROGRAM
SUSPEND, or ERASE SUSPEND commands and outputs status register
data on the falling edge of F_OE# or F_CE#, whichever occurs last.

Program/Erase/

First

If a PROGRAM, ERASE or CHECK BLOCK ERASE operation was

Check Block Erase

previously suspended, this command resumes the operation.

Resume

FFh

Read Array

First

During the array mode, array data is output on the data bus.

01h

Lock Block

Second

If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM latches the address and locks the block indicated on the
address bus.

2Fh

Lock Down

Second

If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM latches the address and locks down the block indicated on
the address bus.

D0h

Unlock Block

Second

If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM latches the address and unlocks the block indicated on the
address bus. If the block had been previously set to lock down, this
operation has no effect.

00h

Invalid/Reserved

Unassigned command that should not be used.

D1h

Check Block

Second

If the previous command was ERASE SETUP command, the CSM

Erase Confirm

closes the address latches and checks that the block is completely
erased.

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

CLEAR STATUS REGISTER

The internal circuitry can set, but not clear, the block

lock status bit (SR1), the F_V

status bit (SR3), the

program status bit (SR4), and the erase status bit (SR5)
of the status register. The CLEAR STATUS REGISTER
command (50h) allows the external microprocessor to
clear these status bits and synchronize to the internal
operations. When the status bits are cleared, the de-
vice returns to the read array mode.

READ OPERATIONS

The following READ operations are available: READ

ARRAY, READ PROTECTION CONFIGURATION REG-
ISTER, READ QUERY and READ STATUS REGISTER.

READ ARRAY

The array is read by entering the command code

FFh on DQ0DQ7. Control signals F_CE# and F_OE#
must be at a logic LOW level (V

), and F_WE# and F_RP#

must be at a logic HIGH level (V

) to read data from the

array. Data is available on DQ0DQ15. Any valid ad-
dress within any of the blocks selects that address and
allows data to be read from that address. Upon initial
power-up or device reset, the device defaults to the
read array mode.

READ CHIP PROTECTION IDENTIFICATION DATA

The chip identification mode outputs three types

of information: the manufacturer/device identifier, the
block locking status, and the protection register. Two
bus cycles are required for this operation: the chip iden-
tification data is read by entering the command code
90h on DQ0DQ7 to the bank containing address 00h
and the identification code address on the address

lines. Control signals F_CE# and F_OE# must be at a
logic LOW level (V

), and F_WE# and F_RP# must be at

a logic HIGH level (V

) to read data from the protection

configuration register. Data is available on DQ0DQ15.
After data is read from protection configuration regis-
ter, the READ ARRAY command, FFh, must be issued to
the bank containing address 00h prior to issuing other
commands. See Table 10 for further details.

READ QUERY

The read query mode outputs common flash inter-

face (CFI) data when the device is read (see Table 12).
Two bus cycles are required for this operation. It is
possible to access the query by writing the read query
command code 98h on DQ0DQ7 to the bank contain-
ing address 0h. Control signals F_CE# and F_OE# must
be at a logic LOW level (V

), and F_WE# and F_RP#

must be at a logic HIGH level (V

) to read data from the

query. The CFI data structure contains information
such as block size, density, command set, and electri-
cal specifications. To return to read array mode, write
the read array command code FFh on DQ0DQ7.

READ STATUS REGISTER

The status register is read by entering the command

code 70h on DQ0DQ7. Two bus cycles are required for
this operation: one to enter the command code and a
second to read the status register. In a READ cycle, the
address is latched and register data is updated on the
falling edge of F_OE# or F_CE#, whichever occurs last.
Register data is updated and latched on the falling
edge of F_OE# or F_CE#, whichever occurs last.

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

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MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Table 6

Command State Machine Transition Table

)

(

c
t

o
n

e
g

s
t

(continued on next page)

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

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MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Table 6

Command State Machine Transition Table (continued)

)

(

(continued on next page)

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Table 6

Command State Machine Transition Table (continued)

)

(

(continued on next page)

FLASH

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MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Table 6

Command State Machine Transition Table (continued)

)

(

Table 7

Bus Operations

MODE

F_RP#

F_CE#

F_OE#

F_WE#

ADDRESS DQ0DQ15

Read (array, status registers,

OUT

device identification register, or
query)

Standby

High-Z

Output Disable

High-Z

Reset

High-Z

Write

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

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MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

For in-system programming, when 0.9V

F_V

2.2V, the APA and the 32 single-word buffer signifi-
cantly improve both the system throughput and the
average programming time when compared with stan-
dard programming practices. The accelerated pro-
gramming functionality executes and verifies the APA
without microprocessor intervention. This relieves the
microprocessor from constantly monitoring the
progress of the programming and erase activity, free-
ing up valuable memory bus bandwidth. This increases
the system throughput.

ERASE OPERATIONS

An ERASE operation must be used to initialize all

bits in an array block to "1s." After BLOCK ERASE con-
firm is issued, the CSM responds only to an ERASE
SUSPEND command until the WSM completes its task.

Block erasure inside the memory array sets all bits

within the address block to logic 1s. Erase is accom-
plished only by blocks; data at single address locations
within the array cannot be erased individually. The
block to be erased is selected by using any valid ad-
dress within that block. Block erasure is initiated by a
command sequence to the CSM: BLOCK ERASE SETUP
(20h) followed by BLOCK ERASE CONFIRM (D0h) (see
Table 5). A two-command erase sequence protects
against accidental erasure of memory contents.

When the BLOCK ERASE CONFIRM command is

complete, the WSM automatically executes a sequence
of events to complete the block erasure. During this
sequence, the block is programmed with logic 0s, data
is verified, all bits in the block are erased, and finally
verification is performed to ensure that all bits are cor-
rectly erased. Monitoring of the ERASE operation is
possible through the status register (see the Status
Register section).

During the execution of an ERASE operation, the

ERASE SUSPEND command (B0h) can be entered to
direct the WSM to suspend the ERASE operation. Once
the WSM has reached the suspend state, it allows the
CSM to respond only to the READ ARRAY, READ
STATUS REGISTER, READ QUERY, READ CHIP PRO-
TECTION CONFIGURATION, PROGRAM SETUP, PRO-
GRAM RESUME, ERASE RESUME and LOCK SETUP
(see the Block Locking section). During the ERASE SUS-
PEND operation, array data must be read from a block
other than the one being erased. To resume the ERASE
operation, an ERASE RESUME command (D0h) must
be issued to cause the CSM to clear the suspend state
previously set (see Figure 8). It is also possible that an
ERASE in any bank can be suspended and a WRITE to
another block in the same bank can be initiated. After

PROGRAMMING OPERATIONS

There are two CSM commands for programming:

PROGRAM SETUP and ACCELERATED PROGRAM-
MING ALGORITHM (see Table 3).

PROGRAM SETUP COMMAND

After the 40h command code is entered on DQ0

DQ7, the WSM takes over and correctly sequences the
device to complete the PROGRAM operation. The
WRITE operation may be monitored through the sta-
tus register (see the Status Register section). During
this time, the CSM will only respond to a PROGRAM
SUSPEND command until the PROGRAM operation
has been completed, after which time, all commands
to the CSM become valid again. The PROGRAM opera-
tion can be suspended by issuing a PROGRAM SUS-
PEND command (B0h).

Once the WSM reaches the suspend state, it allows

the CSM to respond only to READ ARRAY, READ STA-
TUS REGISTER, READ PROTECTION CONFIGURA-
TION, READ QUERY, PROGRAM SETUP, or PROGRAM
RESUME. During the PROGRAM SUSPEND operation,
array data should be read from an address other than
the one being programmed. To resume the PROGRAM
operation, a PROGRAM RESUME command (D0h) must
be issued to cause the CSM to clear the suspend state
previously set (see Figure 4 for programming operation
and Figure 5 for program suspend and program re-
sume).

Taking RP# to V

during programming aborts the

PROGRAM operation.

ACCELERATED PROGRAMMING ALGORITHM

The accelerated programming algorithm (APA) is

intended for in-system and in-factory use. Its 32
single-word internal buffer enables fast data stream
programming.

The APA is activated when the WSM executes com-

mand code 10h. Upon activation, the word address
and the data sequences must be provided to the WSM,
without polling SR7. The same starting address must
be provided for each data word. After all 32 sequences
are issued, the status register reports a busy condition.
Figure 6 shows the APA flowchart.

If the data stream is shorter than 32 words, use

FFFFh to fill in the missing data. Also, be sure the start-
ing address is aligned with a 32-word boundary.

The APA is fully concurrent. For example, it can be

interrupted and resumed during programming. When
loading the programming buffer, only a read access in
the other bank is allowed.

For in-factory programming, the APA, along with an

optimized set of programming parameters, minimizes
chip programming time when 11.4V

F_V

12.6V.

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

STATUS

BIT #

STATUS REGISTER BIT

DESCRIPTION

SR7

WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word
1 = Ready

program or block erase completion, before checking

0 = Busy

program or erase status bits.

SR6

ERASE SUSPEND STATUS (ESS)

When ERASE SUSPEND is issued, WSM halts execution and

1 = BLOCK ERASE Suspended

sets both WSMS and ESS bits to "1." ESS bit remains set to

0 = BLOCK ERASE in

"1" until an ERASE RESUME command is issued.

Progress/Completed

SR5

ERASE/CHECK BLOCK ERASE

When this bit is set to "1" and ERASE CONFIRM is issued, WSM

STATUS (ES)

has applied the maximum number of erase pulses to the

1 = Error in BLOCK ERASE/

block and is still unable to verify successful block erasure.

CHECK BLOCK ERASE

When this bit is set to "1" and CHECK BLOCK ERASE CONFIRM

0 = Successful BLOCK ERASE

is issued, WSM has checked the block for its erase state, and
the block is not erased.

SR4

PROGRAM STATUS (PS)

When this bit is set to "1," WSM has attempted but failed to

1 = Error in PROGRAM

program a word.

0 = Successful PROGRAM

SR3

F_V

STATUS (V

The F_V

status bit does not provide continuous indication

1 = F_V

Low Detect, Operation Abort of the F_V

level. The WSM interrogates the F_V

level only

0 = F_V

= OK

after the program or erase command sequences have been
entered and informs the system if F_V

< 0.9V. The F_V

level is also checked before the PROGRAM/ERASE operation
is verified by the WSM. A factory option allows PROGRAM or
ERASE at 0V, in which case SR3 is held at "0."

SR2

PROGRAM SUSPEND STATUS (PSS)

When PROGRAM SUSPEND is issued, WSM halts execution

1 = PROGRAM Suspended

and sets both WSM and PSS bits to "1." PSS bit remains set to

0 = PROGRAM in Progress/Completed

"1" until a PROGRAM RESUME command is issued.

SR1

BLOCK LOCK STATUS (BLS)

If a PROGRAM or ERASE operation is attempted to one of

1 = PROGRAM/ERASE Attempted on a

the locked blocks, this is set by the WSM. The operation

Locked Block; Operation Aborted

specified is aborted, and the device is returned to read status

0 = No Operation to Locked Blocks

mode.

SR0

RESERVED FOR FUTURE

This bit is reserved for future use.

ENHANCEMENT

Table 8

Status Register Bit Definition

WSMS

ESS

PSS

BLS

the completion of a WRITE, an ERASE can be resumed
by writing an ERASE RESUME command.

After an ERASE command completion, it is possible

to check if the block has been erased successfully, us-
ing the CHECK BLOCK ERASE command. Two bus
cycles are required for this operation: one to set up the

CHECK BLOCK ERASE and the second one to start the
execution of the command. If after the operation the
bit SR5 is set to 0 the operation has been completed
succesfully, if it is set to 1, there has been an error
during the BLOCK ERASE operation.

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Figure 4

Automated Word Programming

Flowchart

NOTE: 1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation

attempts.

BUS
OPERATION COMMAND COMMENTS

WRITE

Data =

40h

PROGRAM

Addr =

Address of word to be

SETUP

programmed

WRITE

Data =

Word to be

DATA

programmed

Addr =

Address of word to be
programmed

READ

Status register data;
toggle OE# or CE# to update
status register.

Standby

Check SR7
1 = Ready, 0 = Busy

Repeat for subsequent words.
Write FFh after the last word programming operation
to reset the device to read array mode.

BUS
OPERATION COMMAND COMMENTS

Standby

Check SR1
1 = Detect locked block

Standby

Check SR3

1 = Detect F_V

low

Standby

Check SR4

1 = Word program error

YES

Full Status Register

Check (optional)

YES

PROGRAM

SUSPEND?

SR7 = 1?

Issue PROGRAM SETUP

Command and

Word Address

Start

Word Program Passed

Range Error

Word Program Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

Issue Word Address

and Word Data

PROGRAM

SUSPEND Loop

YES

SR1 = 0?

YES

SR3 = 0?

YES

SR4 = 0?

Word Program

Completed

Read Status Register

Bits

PROGRAM Attempted

on a Locked Block

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

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MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

YES

Full Status Register

Check (optional)

YES

ERASE

SUSPEND?

SR 7 = 1?

Start

BLOCK ERASE Passed

Range Error

BLOCK ERASE Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

ERASE

SUSPEND Loop

YES

SR1 = 0?

YES

BLOCK ERASE

Completed

Read Status Register

Bits

ERASE Attempted
on a Locked Block

SR3 = 0?

SR5 = 0?

Issue ERASE SETUP

Command and

Block Address

Issue BLOCK ERASE

CONFIRM Command

and Block Address

Figure 7

BLOCK ERASE Flowchart

NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

BUS
OPERATION COMMAND COMMENTS

WRITE

Data = 20h

ERASE

Block Addr = Address

SETUP

within block to be erased

WRITE

ERASE

Data = D0h
Block Addr = Address
within block to be erased

READ

Status register data;
toggle OE# or CE# to
update status register.

Standby

Check SR7
1 = Ready, 0 = Busy

Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to
reset the device to read array mode.

BUS
OPERATION COMMAND COMMENTS

Standby

Check SR1
1 = Detect locked block

Standby

Check SR3

1 = Detect F_V

block

Standby

Check SR4 and SR5
1 = BLOCK ERASE

command error

Standby

Check SR5

1 = BLOCK ERASE error

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

READ

PROGRAM

Issue READ ARRAY

Command

PROGRAM

Loop

ERASE

Complete

READ or

PROGRAM?

YES

Issue ERASE

RESUME Command

READ or

PROGRAM
Complete?

YES

SR6 = 1?

Start

ERASE Continued

Read Status Register

Bits

Issue ERASE

SUSPEND Command

(Note 1)

YES

SR7 = 1?

Figure 8

ERASE SUSPEND/ERASE RESUME

Flowchart

NOTE: 1. See Word Programming Flowchart for complete programming procedure.

2. See BLOCK ERASE Flowchart for complete erasure procedure.

BUS
OPERATION COMMAND COMMENTS

WRITE

ERASE

Data = B0h

SUSPEND

READ

Status register data;
toggle OE# or CE# to
update status register.

Standby

Check SR7
1 = Ready

Standby

Check SR6
1 = Suspended

WRITE

READ

Data = FFh

MEMORY

READ

Read data from block
other than that being
erased.

WRITE

ERASE

Data = D0h

RESUME

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

READ-WHILE-WRITE/ERASE
CONCURRENCY

It is possible for the device to read from one bank

while erasing/writing to another bank. Once a bank
enters the WRITE/ERASE operation, the other bank
automatically enters read array mode. For example,
during a READ CONCURRENCY operation, if a PRO-
GRAM/ERASE command is issued in bank a, then bank
a changes to the read status mode and bank b defaults
to the read array mode. The device reads from bank b if
the latched address resides in bank b (see Figure 10).
Similarly, if a PROGRAM/ERASE command is issued in
bank b, then bank b changes to read status mode and
bank a defaults to read array mode. When returning to
bank a, the device reads program/erase status if the
latched address resides in bank a.

A correct bank address must be specified to read

status register after returning from concurrent read in
the other bank.

When reading the CFI or the chip protection regis-

ter, concurrent operation is not allowed on the top boot
device. Concurrent READ of the CFI or the chip protec-
tion register is only allowed when a PROGRAM or ERASE
operation is performed on bank b on the bottom boot
device. For a bottom boot device, reading of the CFI
table or the chip protection register is only allowed if
bank b is in read array mode. For a top boot device,
reading of the CFI table or the chip protection register
is only allowed if bank a is in read array mode.

BLOCK LOCKING

The Flash memory of the MT28C6428P20 and

MT28C6428P18 devices provide a flexible locking
scheme which allows each block to be individually
locked or unlocked with no latency.

The devices offer two-level protection for the blocks.

The first level allows software-only control of block lock-
ing (for data which needs to be changed frequently),
while the second level requires hardware interaction
before locking can be changed (code which does not
require frequent updates).

Control signals F_WP#, DQ0, and DQ1 define the

state of a block; for example, state [001] means
F_WP# = 0, DQ0 = 0 and DQ1 = 1.

Table 9 defines all of the possible locking states.

NOTE: All blocks are software-locked upon comple-

tion of the power-up sequence.

Figure 10

READ-While-WRITE Concurrency

Bank a
1 - Erasing/writing to bank a
2 - Erasing in bank a can be

suspended, and a WRITE to
another block in bank a
can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.

1 - Reading bank a

Bank b

1 - Reading from bank b

1 - Erasing/writing to bank b
2 - Erasing in bank b can be

suspended, and a WRITE to
another block in bank b
can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.

LOCKED STATE

After a power-up sequence completion, or after a

reset sequence, all blocks are locked (states [001] or
[101]). This means full protection from alteration. Any
PROGRAM or ERASE operations attempted on a locked
block will return an error on bit SR1 of the status regis-
ter. The status of a locked block can be changed to
unlocked or lock down using the appropriate software
commands. Writing the lock command sequence, 60h
followed by 01h, can lock an unlocked block.

UNLOCKED STATE

Unlocked blocks (states [000], [100], [110]) can be

programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked down
using the appropriate software command sequence,
60h followed by D0h. (See Table 4.)

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

LOCKED DOWN STATE

Blocks locked down (state [011]) are protected from

PROGRAM and ERASE operations, but their protection
status cannot be changed using software commands
alone. A locked or unlocked block can be locked down
by writing the lock down command sequence, 60h fol-
lowed by 2Fh. Locked down blocks revert to the locked
state when the device is reset or powered down.

The LOCK DOWN function is dependent on the

F_WP# input. When F_WP# = 0, blocks in lock down
[011] are protected from program, erase, and lock sta-
tus changes. When F_WP# = 1, the LOCK DOWN func-
tion is disabled ([111]) and locked down blocks can be
individually unlocked by a software command to the
[110] state, where they can be erased and programmed.
These blocks can then be relocked [111] and unlocked
[110], as desired, as long as F_WP# remains HIGH.
When F_WP# goes LOW, blocks that were previously
locked down return to the lock down state [011] regard-
less of any changes made while F_WP# was HIGH. De-
vice reset or power-down resets all locks, including
those in lock down, to the locked state (see Table 10).

READING A BLOCK'S LOCK STATUS

The lock status of every block can be read in the

read device identification mode. To enter this mode,
write 90h to the bank containing address 00h. Subse-
quent READs at block address +00002h will output the
lock status of that block. The lowest two outputs, DQ0
and DQ1, represent the lock status. DQ0 indicates the
block lock/unlock status and is set by the LOCK com-
mand and cleared by the UNLOCK command. It is also
automatically set when entering lock down. DQ1 indi-
cates lock down status and is set by the LOCK DOWN
command. It can only be cleared by reset or power-
down, not by software. Table 9 shows the block locking
state transition scheme. The READ ARRAY command,

FFh, must be issued to the bank containing address
00h prior to issuing other commands.

LOCKING OPERATIONS DURING ERASE
SUSPEND

Changes to block lock status can be performed dur-

ing an ERASE SUSPEND by using the standard locking
command sequences to unlock, lock, or lock down. This
is useful in the case when another block needs to be
updated while an ERASE operation is in progress.

To change block locking during an ERASE opera-

tion, first write the ERASE SUSPEND command (B0h),
then check the status register until it indicates that the
ERASE operation has been suspended. Next, write the
desired lock command sequence to block lock, and the
lock status will be changed. After completing any de-
sired LOCK, READ, or PROGRAM operations, resume
the ERASE operation with the ERASE RESUME com-
mand (D0h).

If a block is locked or locked down during an ERASE

SUSPEND on the same block, the locking status bits
are changed immediately. When the ERASE is resumed,
the ERASE operation completes.

A locking operation cannot be performed during a

PROGRAM SUSPEND.

STATUS REGISTER ERROR CHECKING

Using nested locking or program command se-

quences during ERASE SUSPEND can introduce ambi-
guity into status register results.

Following protection configuration setup (60h), an

invalid command produces a lock command error (SR4
and SR5 are set to "1") in the status register. If a lock
command error occurs during an ERASE SUSPEND,
SR4 and SR5 are set to "1" and remain at "1" after the
ERASE SUSPEND command is issued. When the ERASE

Table 9

Block Locking State Transition

ERASE/PROGRAM

LOCK

F_WP#

DQ1

DQ0

NAME

ALLOWED

LOCK

UNLOCK

DOWN

Unlocked

Yes

To [001]

To [011]

Locked (Default)

To [000]

To [011]

Lock Down

Unlocked

Yes

To [101]

To [111]

Locked

To [100]

To [111]

Lock Down

Yes

To [111]

Disabled

Lock Down

To [110]

Disabled

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

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4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

is complete, any possible error during the ERASE can-
not be detected via the status register because of the
previous locking command error.

A similar situation happens if an error occurs during

a program operation error nested within an ERASE
SUSPEND.

CHIP PROTECTION REGISTER

A 128-bit chip protection register can be used to

fullfill the security considerations in the system (pre-
venting device substitution).

The 128-bit security area is divided into two 64-bit

segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit number. The
other segment is left blank for customers to program as
desired. (See Figure 12).

READING THE CHIP PROTECTION REGISTER

The chip protection register is read in the device

identification mode. To enter this mode, load the 90h
command the bank containing address 00h. Once in
this mode, READ cycles from addresses shown in Table
10 retrieve the specified information. To return to the
read array mode, write the READ ARRAY command
(FFh). The READ ARRAY command, FFh, must be is-
sued to the bank containing address 00h prior to issu-
ing other commands.

PAGE READ MODE

The initial portion of the page mode cycle is the

same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0A2 allows random ac-
cess of other words in the page.

The page size can be customized at the factory to

four or eight words as required; but if no specification is
made, the normal size is four words.

ASYNCHRONOUS READ CYCLE

When accessing addresses in a random order or

when switching between pages, the access time is given
by

AA.

When F_CE# and F_OE# are LOW, the data is placed

on the data bus and the processor can read the data.

Figure 12

Protection Register Memory Map

4 Words

Factory-Programmed

4 Words

User-Programmed

PR Lock

88h

85h

84h

81h

80h

ITEM

ADDRESS

DATA

Manufacturer Code (x16)

00000h

002Ch

Device Code

00001h

Top boot configuration

44B6h

Bottom boot configuration

44B7h

Block Lock Configuration

XX002h

Lock

Block is unlocked

DQ0 = 0

Block is locked

DQ0 = 1

Block is locked down

DQ1 = 1

Chip Protection Register Lock

80h

PR Lock

Chip Protection Register 1

81h84h

Factory Data

Chip Protection Register 2

85h88h

User Data

NOTE: 1. Other locations within the configuration address space are reserved by

Micron for future use.

2. "XX" specifies the block address of lock configuration.

Table 10

Chip Configuration Addressing

FLASH

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512K x 16 SRAM COMBO MEMORY

ADVANCE

STANDBY MODE

supply current is reduced by applying a logic

HIGH level on F_CE# and F_RP# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on F_CE#
and F_RP# reduces the current to I

(MAX). If the

device is deselected during an ERASE operation or dur-
ing programming, the device continues to draw cur-
rent until the operation is complete.

AUTOMATIC POWER SAVE (APS) MODE

Substantial power savings are realized during peri-

ods when the Flash array is not being read and the
device is in the active mode. During this time the de-
vice switches to the automatic power save (APS) mode.
When the device switches to this mode, I

is reduced

to a level comparable to I

. Further power savings can

be realized by applying a logic HIGH level on CE# to
place the device in standby mode. The low level of
power is maintained until another operation is initi-
ated. In this mode, the I/Os retain the data from the
last memory address read until a new address is read.
This mode is entered automatically if no addresses or
control signals toggle.

DEEP POWER-DOWN MODE

By issuing an ENABLE DEEP POWER-DOWN com-

mand (see Table 3) it is possible to enable the DEEP
POWER-DOWN function. In this configuration, apply-
ing a logic LOW to RST# reduces the current to I

, and

resets all the internal registers with the exception of the
individual block protection status. To exit this mode, a
wait time of 100µs (

RWHDP) must elapse after a logic

HIGH is applied to RST#. During the wait time, the
device performs a full power-up sequence, and the
power consumption may exceed the standby current
limits.

F_V

/F_V

PROGRAM AND ERASE

VOLTAGES

The Flash memory devices provide in-system

programming and erase with F_V

in the 0.9V2.2V

range. In addition to the flexible block locking, the F_V

programming voltage can be held LOW for absolute
hardware write protection of all blocks in the Flash de-
vice. When F_V

is below V

PPLK

, any PROGRAM or ERASE

operation results in an error, prompting the corre-
sponding status register bit (SR3) to be set.

A factory option provides in-system programming

and erase with F_V

in the 0.0V2.2V range.

F_V

at 12V ±5% (F_V

) is supported for a maxi-

mum of 100 cycles and 10 cumulative hours. The de-
vice can withstand 100,000 WRITE/ERASE operations
when F_V

= F_V

During WRITE and ERASE operations, the WSM

monitors the F_V

voltage level. WRITE/ERASE opera-

tions are allowed only when F_V

is within the ranges

specified in Table 11.

When F_V

is below V

LKO

or F_V

is below

VPPLK

, any

WRITE/ERASE operation is prevented.

DEVICE RESET

To correctly reset the device, the RST# signal must

be asserted (RST# = V

) for a minimum of

RP. After

reset, the device can be accessed for a READ operation
with a delayed access time of

RWH from the rising edge

of RST#. The circuitry used for generating the RST#
signal needs to be common with the rest of the system
reset to ensure that correct system initialization occurs.
Please refer to the timing diagram for further details.

POWER-UP SEQUENCE

The following power-up sequence is recommended

to properly initialize internal chip operations:

· At power-up, RST# should be kept at V

for 2µs

after F_V

reaches F_V

(MIN).

· V

Q should not come up before F_V

· F_V

should be kept at V

to maximize data

integrity.

When the power-up sequence is completed, RST#

should be brought to V

. To ensure proper power-up,

the rise time of RST# (10%90%) should be < 10µs.

Table 11

F_V

Ranges (V)

DEVICE

MIN

MAX

In-System

0.9

2.2

In-Factory

11.4

12.6

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

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512K x 16 SRAM COMBO MEMORY

ADVANCE

ABSOLUTE MAXIMUM RATINGS*

Voltage to Any Ball Except F_V

and F_V

with Respect to V

............................ -0.5V to +2.45V

F_V

Voltage (for BLOCK ERASE and PROGRAM

with Respect to V

) ....................... -0.5V to +13.5V**

F_V

and V

Q Supply Voltage

with Respect to V

............................ -0.3V to +2.45V

Output Short Circuit Current ............................... 100mA
Operating Temperature Range .............. -40

C to +85

Storage Temperature Range ................. -55

C to +125

Soldering Cycle ........................................... 260

C for 10s

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Maximum DC voltage on F_V

may overshoot to

+13.5V for periods <20ns.

RECOMMENDED OPERATING CONDITIONS

(-40ºC

+85ºC)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

supply voltage (MT28C6428P18)

F_V

, S_V

1.70

1.90

supply voltage (MT28C6428P20)

F_V

, S_V

1.80

2.20

I/O supply voltage (MT28C6428P18)

1.70

1.90

I/O supply voltage (MT28C6428P20)

1.80

2.20

F_V

voltage (when used as logic control)

F_V

0.9

2.2

F_V

in-factory programming voltage

F_V

11.4

12.6

Data retention supply voltage

S_V

1.0

Block erase cycling (F_V

)

F_V

100,000

Cycles

F_V

100

Cycles

FLASH ELECTRICAL SPECIFICATIONS

NOTE: 1. F_V

= F_V

is a maximum of 10 cumulative hours.

Figure 14

Output Load Circuit

I/O

14.5K

30pF

14.5K

Output

Test Points

Input

AC test inputs are driven at V

for a logic 1 and V

for a logic 0. Input timing begins at V

/2,

and output timing ends

at V

Q/2. Input rise and fall times (10% to 90%) < 5ns.

Q/2

Figure 13

AC Input/Output Reference Waveform

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

COMBINED DC CHARACTERISTICS

F_V

Q = 1.70V1.90V

or 1.80V2.20V

DESCRIPTION

CONDITIONS

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Input Low Voltage

0.0

0.4

Input High Voltage

Q - 0.4

Output Low Voltage

0.10

= 100µA (Flash)

Output Low Voltage

0.3

= 100µA (SRAM)

Output High Voltage

Q - 0.1

= -100µA (Flash)

Output High Voltage

Q - 0.3

= -100µA (SRAM)

F_V

Lockout Voltage

PPLK

0.4

F_V

During PROGRAM/ERASE

F_V

0.9

2.2

Operations

F_V

11.4

12.6

F_V

Program/Erase Lock Voltage

LKO

1.0

Input Leakage Current

1.0

µA

Output Leakage Current

1.0

µA

F_V

Read Current

4, 5

Asynchronous Random Read,

100ns cycle

Asynchronous Page Read,

4, 5

100ns/35ns cycle

F_V

plus S_V

Standby Current

µA

F_V

Program Current

F_V

Erase Current

F_V

Erase Suspend Current

µA

F_V

Program Suspend Current

µA

Read-While-Write Current

NOTE: 1. All currents are in RMS unless otherwise noted.

2. V

may decrease to -0.4V and V

may increase to V

Q + 0.3V for durations not to exceed 20ns.

3. 12V F_V

is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

4. APS mode reduces I

to approximately I

levels.

5. Test conditions: Vcc = V

(MAX), CE# = V

, OE# = V

. All other inputs = V

or V

6. I

and I

values are valid when the device is deselected. Any read operation performed while in suspend mode will

add a current draw of I

or I

(continued on next page)

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

COMBINED DC CHARACTERISTICS

(continued)

F_V

Q = 1.70V1.90V

or 1.80V2.20V

DESCRIPTION

CONDITIONS

SYMBOL

MIN

TYP

MAX

UNITS NOTES

S_V

Read/Write Operating

= V

or V

Supply Current Random

chip enabled,

Access Mode

= 0

S_V

Read/Write Operating

= V

or V

Supply Current Page Access

chip enabled,

Mode

= 0

Deep Power-Down Current

µA

F_V

Current

F_V

0.5

µA

(Read, Standby Erase Suspend,

F_V

200

µA

Program Suspend)

NOTE: 1. All currents are in RMS unless otherwise noted.

2. V

may decrease to -0.4V and V

may increase to V

Q + 0.3V for durations not to exceed 20ns.

3. 12V F_V

is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

4. APS mode reduces I

to approximately I

levels.

5. Test conditions: Vcc = V

(MAX), CE# = V

, OE# = V

. All other inputs = V

or V

6. I

and I

values are valid when the device is deselected. Any read operation performed while in suspend mode will

add a current draw of I

or I

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

FLASH WRITE CYCLE TIMING REQUIREMENTS

-80

-85

F_V

= 1.80V

2.20V

F_V

= 1.70V

1.90V

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

Reset HIGH recovery to F_WE# going LOW

150

F_CE# setup to F_WE# going LOW

Write pulse width

Data setup to F_WE# going HIGH

Address setup to F_WE# going HIGH

F_CE# hold from F_WE# HIGH

Data hold from F_WE# HIGH

Address hold from F_WE# HIGH

Write pulse width HIGH

WPH

F_WP# setup to F_WE# going HIGH

RHS

F_V

setup to F_WE# going HIGH

VPS

200

Write recovery before READ

WOS

Write recovery before READ in opposite bank

WOA

F_WP# hold from valid SRD

RHH

F_V

hold from valid SRD

VPPH

F_WE# HIGH to data valid

AA + 50

FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS

-80/-85

PARAMETER

TYP

MAX

UNITS

4KW parameter block program time

800

32KW parameter block program time

320

6,400

Word program time

10,000

µs

4KW parameter block erase time

0.3

32KW parameter block erase time

0.5

Program suspend latency

µs

Erase suspend latency

µs

Chip programming time

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

TWO-CYCLE PROGRAMMING/ERASE OPERATION

VALID ADDRESS

UNDEFINED

RHS

A0A21

F_OE#

F_CE#

F_WE#

F_V

F_RP#

F_WP#

I L

IPPLK

IPPH

WPH

WOS

CMD

CMD/

DATA

DQ0DQ15

RHH

VPS

VPPH

STATUS

High-Z

NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle.

-80

-85

F_V

= 1.80V2.20V

F_V

= 1.70V1.90V

SYMBOL

MIN

MAX

MIN

MAX

UNITS

WRITE TIMING PARAMETERS

-80

-85

F_V

= 1.80V2.20V

F_V

= 1.70V1.90V

SYMBOL

MIN

MAX

MIN

MAX

UNITS

150

RHS

VPS

200

WOS

RHH

VPPH

AA + 50

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Table 12

CFI

OFFSET

DATA

DESCRIPTION

2Ch

Manufacturer code

B6h

Top boot block device code

B7h

Bottom boot block device code

020F

reserved

Reserved

10, 11

0051,0052

"QR"

0059

"Y"

13, 14

0003, 0000

Primary OEM command set

15, 16

0039, 0000

Address for primary extended table

17, 18

0000, 0000

Alternate OEM command set

19, 1A

0000, 0000

Address for OEM extended table

0017

F_V

MIN for Erase/Write; Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in BCD

0022

F_V

MAX for Erase/Write; Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in BCD

00B4

F_V

MIN for Erase/Write; Bit7Bit4 Volts in Hex; Bit3Bit0 100mV in BCD

00C6

F_V

MAX for Erase/Write; Bit7Bit4 Volts in Hex; Bit3Bit0 100mV in BCD, 0000 = F_V

ball

0003

Typical timeout for single byte/word program, 2

µs, 0000 = not supported

0000

Typical timeout for maximum size multiple byte/word program, 2

µs, 0000 = not

supported

0009

Typical timeout for individual block erase, 2

ms, 0000 = not supported

0000

Typical timeout for full chip erase, 2

ms, 0000 = not supported

000C

Maximum timeout for single byte/word program, 2

µs, 0000 = not supported

0000

Maximum timeout for maximum size multiple byte/word program, 2

µs, 0000 = not

supported

0003

Maximum timeout for individual block erase, 2

ms, 0000 = not supported

0000

Maximum timeout for full chip erase, 2

ms, 0000 = not supported

0017

Device size, 2

bytes

0001

Bus interface x8 = 0, x16 = 1, x8/x16 = 2

0000

Flash device interface description 0000 = async

2A, 2B

0000, 0000

Maximum number of bytes in multibyte program or page, 2

0003

Number of erase block regions within device (4K words and 32K words)

2D, 2E

5F00, 0001

Top boot block device erase block region information 1, 8 blocks ...

0007, 0000

Bottom boot block device erase block region information 1, 8 blocks ...

2F, 30

0000, 0001

Erase block region information 1, 8 blocks ...

0020, 0000

...of 8KB

31, 32

000E, 0000

15 blocks of ....

33, 34

0000, 0001

......64KB

35, 36

0007, 0000

Top boot block device ......96KB blocks of

5F00, 0001

Bottom boot block device ......96KB blocks of

(continued on the next page)

FLASH

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

Table 12

CFI (continued)

OFFSET

DATA

DESCRIPTION

37, 38

0020, 0000

Top boot block device......64KB

0000, 0001

Bottom boot block device......64KB

39, 3A

0050, 0052

"PR"

0049

"I"

0030

Major version number, ASCII

0031

Minor version number, ASCII

00E6

Optional Feature and Command Support

0002

Bit 0 Chip erase supported no = 0

0000

Bit 1 Suspend erase supported = yes = 1

0000

Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes = 1
Bit 8 Synchronous read supported = yes = 1
Bit 9 Simultaneous operation supported = yes = 1

0001

Program supported after erase suspend = yes

43, 44

0003,0000

Bit 0 block lock status active = yes; Bit 1 block lock down active = yes

0018

F_V

supply optimum; Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in BCD

00C0

F_V

supply optimum; Bit7Bit4 Volts in Hex; Bit3Bit0 100mV in BCD

0001

Number of protection register fields in JEDEC ID space

48, 49

0080, 0000

Lock bytes LOW address, lock bytes HIGH address

4A, 4B

0003, 0003

factory programmed bytes, 2

user programmable bytes

0003

Background Operation
0000 = Not used
0001 = 4% block split
0002 = 12% block split
0003 = 25% block split
0004 = 50% block split

0000

Burst Mode Type
0000 = No burst mode
00x1 = 4 words MAX
00x2 = 8 words MAX
00x3 = 16 words MAX
001x = Linear burst, and/or
002x = Interleaved burst, and/or
004x = Continuous burst

0002

Page Mode Type
0000 = No page mode
0001 = 4-word page
0002 = 8-word page
0003 = 16-word page
0004 = 32-word page

0008

SRAM density, 8Mb (512K x 16)

SRAM

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

SRAM OPERATING MODES

SRAM READ ARRAY

The operational state of the SRAM is determined by

S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as
indicated in the Truth Table. To perform an SRAM
READ operation, S_CE1#, and S_OE#, must be at V

and S_CE2 and S_WE# must be at V

. When in this

state, S_UB# and S_LB# control whether the lower byte
is read (S_UB# V

, S_LB# V

), the upper byte is read

(S_UB# V

, S_LB# V

), both upper and lower bytes are

read (S_UB# V

, S_LB# V

), or neither are read (S_UB#

, S_LB# V

) and the device is in a standby state.

While performing an SRAM READ operation, cur-

rent consumption may be reduced by reading within a
16-word page. This is done by holding S_CE1# and

SRAM FUNCTIONAL BLOCK DIAGRAM

DQ0DQ7

WORD

ADDRESS

DECODE

LOGIC

PAGE

ADDRESS

DECODE

LOGIC

CONTROL

LOGIC

16K-PAGE

x16 WORD

x16 BIT

RAM ARRAY

WORD

MUX

DQ8DQ15

INPUT/

OUTPUT

MUX

AND

BUFFERS

S_CE1#

A4A18

A0A3

S_OE#
S_UB#

S_LB#

S_CE2

S_WE#

S_OE# at V

, S_WE# and S_CE2 at V

, and toggling

addresses A0A3. S_UB# and S_LB# control the data
width as described above.

SRAM WRITE ARRAY

In order to perform an SRAM WRITE operation,

S_CE1# and S_WE# must be at V

, and S_CE2 and

S_OE# must be at V

. When in this state, S_UB# and

S_LB# control whether the lower byte is written (S_UB#
V

, S_LB# V

), the upper byte is written (S_UB# V

S_LB# V

), both upper and lower bytes are written

(S_UB# V

, S_LB# V

), or neither are written (S_UB#

, S_LB# V

) and the device is in a standby state.

SRAM

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

TIMING TEST CONDITIONS

Input pulse levels ........... 0.1V S_V

to 0.9V S_V

Input rise and fall times .................................... 5ns

Input timing reference levels ......................... 0.5V

Output timing reference levels ..................... 0.5V

Operating Temperature ............... -40

C to +85

SRAM WRITE CYCLE TIMING

-80

-85

S_V

= 1.80V2.20V

S_V

= 1.70V1.90V

DESCRIPTION

SYMBOL

MIN

MAX

MIN

MAX

UNITS

WRITE cycle time

Chip enable to end of write

Address valid to end of write

Byte select to end of write

LBW,

UBW

Address setup time

Write pulse width

Write recovery time

Write to High-Z output

WHZ

Data to write time overlap

Data hold from write time

End write to Low-Z output

O W

NOTE: For input/output contacts, refer to the Capacitance Table.

SRAM READ CYCLE TIMING

-80

-85

S_V

= 1.80V2.20V

S_V

= 1.70V1.90V

DESCRIPTION

SYMBOL

MIN

MAX

MIN

MAX

UNITS

READ cycle time

Address access time

Address access time (word mode)

AAW

Chip enable to valid output

C O

Output enable to valid output

Byte select to valid output

LB,

Chip enable to Low-Z output

Output enable to Low-Z output

OLZ

Byte select to Low-Z output

LBZ,

UBZ

Chip enable to High-Z output

Output disable to High-Z output

OHZ

Byte select disable to High-Z output

LBHZ,

UBHZ

Output hold from address change

SRAM

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

DON'T CARE

ADDRESS

S_CE1#

S_CE2

S_OE#

S_LB#, S_UB#

DATA-OUT

tRC

tAA

tHZ (1, 2)

tCO

tLBLZ, tUBLZ

tLBHZ, tUBHZ

DATA VALID

High-Z

tOE

tLZ(2)

tOLZ

tOHZ (1)

tLB, tUB

READ CYCLE

(S_CE1# = S_OE# = V

; S_CE2, S_WE# = V

)

ADDRESS

DATA-OUT

tRC

tAA

tOH

PREVIOUS
DATA VALID

DATA VALID

READ CYCLE

(S_WE# = V

)

OLZ

OHZ

LBHZ,

UBHZ

-80

-85

S_V

= 1.80V2.20V

S_V

= 1.70V1.90V

SYMBOL

MIN

MAX

MIN

MAX

UNITS

READ TIMING PARAMETERS

-80

-85

S_V

= 1.80V2.20V

S_V

= 1.70V1.90V

SYMBOL

MIN

MAX

MIN

MAX

UNITS

LB,

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

67-BALL FBGA

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.

0.12 C

SEATING PLANE

1.05 ±0.075

67X

0.35

BALL A12

5.60

2.80 ±0.05

4.40 ±0.05

5.75 ±0.05

9.00 ±0.10

4.50 ±0.05

BALL A1 ID

1.40 MAX

BALL A1

0.80 (TYP)

8.80

11.50 ±0.10

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .27mm

SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS Ø 0.33

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.

DATA SHEET DESIGNATION

Advance: This data sheet contains initial descriptions of products still under development.

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28C6428P20_3.p65 Rev. 3, Pub. 7/02

4 MEG x 16 ASYNCHRONOUS/PAGE FLASH

512K x 16 SRAM COMBO MEMORY

ADVANCE

REVISION HISTORY

Rev. 3, ADVANCE .............................................................................................................................................................. 7/02
· Corrected bottom boot block device address ranges
· Updated command descriptions
· Updated SR5 status register bit description
· Updated flowcharts
· Updated DC Characteristics
· Corrected Status Register section
· Updated the Read-While-Write/Erase Concurrency section
· Changed

RHS from 200ns (MIN) to 0ns (MIN)

· Changed C

OUT

from 9 (TYP) and 12 (MAX) to 13 (TYP) and 15 (MAX)

Rev. 2, ADVANCE .............................................................................................................................................................. 4/02
· Updated the Combined DC Characteristics table
· Updated

AH and

RWH

· Updated the chip protection mode register information
· Updated the block locking information

Initial published release, ADVANCE, Rev. 1 ............................................................................................................... 1/02

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