PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

09005aef808cfe29
MT28F322P3FJ_F.fm - Rev. F 7/03 EN

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

FLASH MEMORY

MT28F322P3

LOW VOLTAGE, EXTENDED TEMPERATURE

Features

· Flexible dual-bank architecture

Support for true concurrent operation with zero
latency
Read bank a during program bank b and vice versa
Read bank a during erase bank b and vice versa

· Basic configuration:

Seventy-one erasable blocks
Bank a (8Mb for data storage)
Bank b (24Mb for program storage)

· V

, V

Q, V

voltages

2.7V (MIN), 3.3V (MAX) V

2.2V (MIN), 3.3V (MAX) V

3.0V (TYP) V

(in-system PROGRAM/ERASE)

12V ±5% (HV) V

tolerant (factory programming

compatibility)

· Random access time: 70ns @ 2.7V V

· Page Mode read access

Eight-word page
Interpage read access: 70ns @ 2.7V
Intrapage read access: 30ns @ 2.7V

· Low power consumption (V

= 3.3V)

Asynchronous/interpage READ < 15mA
Intrapage READ < 7mA
WRITE < 20mA (MAX)
ERASE < 25mA (MAX)
Standby < 15µA (TYP), 50µA (MAX) @ 3.3V
Automatic power save (APS) feature

· Enhanced write and erase suspend options

ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank

· Dual 64-bit chip protection registers for security

purposes

· Cross-compatible command support

Extended command set
Common flash interface

· PROGRAM/ERASE cycle

100,000 WRITE/ERASE cycles per block

· Fast programming algorithm
· V

= 12V ±5%

Part Number Example:

MT28F322P3FJ-70 BET

OPTIONS

MARKING

· Timing

70ns access

-70

80ns access

-80

· Boot Block Configuration

Top

Bottom

· Package

48-ball FBGA (6 x 8 ball grid)

· Operating Temperature Range

Extended (-40

°C to +85°C)

1 2 3 4 5 6 7 8

Top View

(Ball Down)

A13

A14

A15

A16

A19

A17

DQ8

DQ9

DQ10

WP#

A18

A20

DQ2

DQ3

WE#

DQ5

DQ6

DQ13

OE#

CE#

DQ0

DQ1

A11

A10

A12

DQ14

DQ15

DQ7

RST#

DQ11

DQ12

DQ4

Ball Assignment

48-Ball FBGA

NOTE:

See page 7 for Ball Description Table.

See page 39 for mechanical drawing.

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

General Description

The MT28F322P3 is a high-performance, high-den-

sity, nonvolatile memory solution that can signifi-
cantly improve system performance. This new
architecture features a two-memory-bank configura-
tion that supports background operation with no
latency.

A high-performance bus interface allows a fast page

mode data transfer; a conventional asynchronous bus
interface is provided as well.

The MT28F322P3 allows soft protection for blocks,

as read only, by configuring soft protection registers
with dedicated command sequences. For security pur-
poses, two 64-bit chip protection registers are pro-
vided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state
machine (WSM). Two on-chip status registers, one for
each of the two memory partitions, can be used to
monitor the WSM status and to determine the progress
of the program/erase \k.

The erase/program suspend functionality allows

compatibility with existing EEPROM emulation soft-
ware packages.

The device is manufactured using 0.18µm process

technology.

Refer to Micron's Web site

www.micron.com/flash

for the latest data sheet.

Architecture and Memory Organization

The MT28F322P3 Flash device contains two sepa-

rate banks of memory (bank a and bank b) for simulta-
neous READ and WRITE operations.

The MT28F322P3 Flash memory is available in the

following bank segmentation configuration:
· Bank a comprises one-fourth of the memory and

contains 8 x 4K-word parameter blocks and 15 x
32K-word blocks.

· Bank b represents three-fourths of the memory, is

equally sectored, and contains 48 x 32K-word
blocks.
Figure 2 and Figure 3 show the bottom and top

memory organizations.

Device Marking

Due to the size of the package, Micron's standard

part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.

Table 1:

Cross Reference for Abbreviated Device Marks

PART NUMBER

PRODUCT

MARKING

SAMPLE

MARKING

MECHANICAL

SAMPLE MARKING

MT28F322P3FJ-70 BET

FW816

FX816

FY816

MT28F322P3FJ-70 TET

FW817

FX817

FY817

MT28F322P3FJ-80 BET

FW814

FX814

FY814

MT28F322P3FJ-80 TET

FW815

FX815

FY815

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Part Numbering Information

Micron's low-power devices are available with sev-

eral different combinations of features (see Figure 1).
Valid combinations of features and their correspond-
ing part numbers are listed in Table 2.

Figure 1: Part Number Chart

MT 28F 322 P 3 FJ -70 T ET

Micron Technology

Flash Family

28F = Dual-Supply Flash

Density/Organization/Banks

322 = 32Mb (2,048K x 16)
bank a = 1/4; bank b = 3/4

Access Time

-70 = 70ns
-80 = 80ns

Read Mode Operation

P = Asynchronous/Page Read

Package Code

FJ = 48-ball FBGA (6 x 8 grid)

Operating Temperature Range

ET = Extended Temperature (-40°C to +85°C)

Boot Block Starting Address

B = Bottom boot
T = Top boot

Operating Voltage Range

3 = 2.7V3.3V Vcc

Table 2:

Valid Part Number Combinations

PART NUMBER

ACCESS TIME

(ns)

BOOT BLOCK

STARTING

ADDRESS

OPERATING

TEMPERATURE RANGE

MT28F322P3FJ-70 BET

Bottom

-40

°C to +85°C

MT28F322P3FJ-70 TET

Top

-40

°C to +85°C

MT28F322P3FJ-80 BET

Bottom

-40

°C to +85°C

MT28F322P3FJ-80 TET

Top

-40

°C to +85°C

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Figure 2: Bottom Boot Block Device

BANK b = 24Mb

BLOCK

BLOCK SIZE

(K-bytes/K-words)

ADDRESS RANGE

(x16)

64/32

1F8000h-1FFFFFh

64/32

1F0000h-1F7FFFh

64/32

1E8000h-1EFFFFh

64/32

1E0000h-1E7FFFh

64/32

1D8000h-1DFFFFh

64/32

1D0000h-1D7FFFh

64/32

1C8000h-1CFFFFh

64/32

1C0000h-1C7FFFh

64/32

1B8000h-1BFFFFh

64/32

1B0000h-1B7FFFh

64/32

1A8000h-1AFFFFh

64/32

1A0000h-1A7FFFh

64/32

198000h-19FFFFh

64/32

190000h-197FFFh

64/32

188000h-18FFFFh

64/32

180000h-187FFFh

64/32

178000h-17FFFFh

64/32

170000h-177FFFh

64/32

168000h-16FFFFh

64/32

160000h-167FFFh

64/32

158000h-15FFFFh

64/32

150000h-157FFFh

64/32

148000h-14FFFFh

64/32

140000h-147FFFh

64/32

138000h-13FFFFh

64/32

130000h-137FFFh

64/32

128000h-12FFFFh

64/32

120000h-127FFFh

64/32

118000h-11FFFFh

64/32

110000h-117FFFh

64/32

108000h-10FFFFh

64/32

100000h-107FFFh

64/32

0F8000h-0FFFFFh

64/32

0F0000h-0F7FFFh

64/32

0E8000h-0EFFFFh

64/32

0E0000h-0E7FFFh

64/32

0D8000h-0DFFFFh

64/32

0D0000h-0D7FFFh

64/32

0C8000h-0CFFFFh

64/32

0C0000h-0C7FFFh

64/32

0B8000h-0BFFFFh

64/32

0B0000h-0B7FFFh

64/32

0A8000h-0AFFFFh

64/32

0A0000h-0A7FFFh

64/32

098000h-097FFFh

64/32

090000h-097FFFh

64/32

088000h-087FFFh

64/32

080000h-087FFFh

BANK a = 8Mb

BLOCK

BLOCK SIZE

(K-bytes/K-words)

ADDRESS RANGE

(x16)

64/32

078000h-07FFFFh

64/32

070000h-077FFFh

64/32

068000h-067FFFh

64/32

060000h-067FFFh

64/32

058000h-05FFFFh

64/32

050000h-057FFFh

64/32

048000h-04FFFFh

64/32

040000h-047FFFh

64/32

038000h-03FFFFh

64/32

030000h-037FFFh

64/32

028000h-02FFFFh

64/32

020000h-027FFFh

64/32

018000h-01FFFFh

64/32

010000h-017FFFh

64/32

008000h-00FFFFh

8/4

007000h-007FFFh

8/4

006000h-006FFFh

8/4

005000h-005FFFh

8/4

004000h-004FFFh

8/4

003000h-003FFFh

8/4

002000h-002FFFh

8/4

001000h-001FFFh

8/4

000000h-000FFFh

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Figure 3: Top Boot Block Device

BANK a = 8Mb

BLOCK

BLOCK SIZE

(K-bytes/K-words)

ADDRESS RANGE

(x16)

8/4

1FF000h-1FFFFFh

8/4

1FE000h-1FEFFFh

8/4

1FD000h-1FDFFFh

8/4

1FC000h-1FCFFFh

8/4

1FB000h-1FBFFFh

8/4

1FA000h-1FAFFFh

8/4

1F9000h-1F9FFFh

8/4

1F8000h-1F8FFFh

64/32

1F0000h-1F7FFFh

64/32

1E8000h-1EFFFFh

64/32

1E0000h-1E7FFFh

64/32

1D8000h-1DFFFFh

64/32

1D0000h-1D7FFFh

64/32

1C8000h-1CFFFFh

64/32

1C0000h-1C7FFFh

64/32

1B8000h-1BFFFFh

64/32

1B0000h-1B7FFFh

64/32

1A8000h-1AFFFFh

64/32

1A0000h-1A7FFFh

64/32

198000h-19FFFFh

64/32

190000h-197FFFh

64/32

188000h-18FFFFh

64/32

180000h-187FFFh

BANK b= 24Mb

BLOCK

BLOCK SIZE

(K-bytes/K-words)

ADDRESS RANGE

(x16)

64/32

178000h-17FFFFh

64/32

170000h-177FFFh

64/32

168000h-16FFFFh

64/32

160000h-167FFFh

64/32

158000h-15FFFFh

64/32

150000h-157FFFh

64/32

148000h-14FFFFh

64/32

140000h-147FFFh

64/32

138000h-13FFFFh

64/32

130000h-137FFFh

64/32

128000h-12FFFFh

64/32

120000h-127FFFh

64/32

118000h-11FFFFh

64/32

110000h-117FFFh

64/32

108000h-10FFFFh

64/32

100000h-107FFFh

64/32

0F8000h-0FFFFFh

64/32

0F0000h-0F7FFFh

64/32

0E8000h-0EFFFFh

64/32

0E0000h-0E7FFFh

64/32

0D8000h-0DFFFFh

64/32

0D0000h-0D7FFFh

64/32

0C8000h-0CFFFFh

64/32

0C0000h-0C7FFFh

64/32

0B8000h-0BFFFFh

64/32

0B0000h-0B7FFFh

64/32

0A8000h-0AFFFFh

64/32

0A0000h-0A7FFFh

64/32

098000h-09FFFFh

64/32

090000h-097FFFh

64/32

088000h-08FFFFh

64/32

080000h-087FFFh

64/32

078000h-07FFFFh

64/32

070000h-077FFFh

64/32

068000h-06FFFFh

64/32

060000h-067FFFh

64/32

058000h-05FFFFh

64/32

050000h-057FFFh

64/32

048000h-04FFFFh

64/32

040000h-047FFFh

64/32

038000h-03FFFFh

64/32

030000h-037FFFh

64/32

028000h-02FFFFh

64/32

020000h-027FFFh

64/32

018000h-01FFFFh

64/32

010000h-017FFFh

64/32

008000h-00FFFFh

64/32

000000h-007FFFh

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Ball Descriptions

48-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

D8, C8, B8, C7,

A8, B7, C6, A7,
A3, C3, B2, A2,

C2, A1, B1, C1,

D1, B6, B5, A6,

A0A20

Input

Address Inputs: Inputs for the address during READ and WRITE
operations. Addresses are internally latched during READ and WRITE
cycles.

CE#

Input

Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.

OE#

Input

Output Enable: Enables the output buffer when LOW. When OE# is HIGH,
the output buffers are disabled.

WE#

Input

Write Enable: Determines if a given cycle is a WRITE cycle. if WE# is LOW,
the cycle is either a WRITE to the command state machine (CSM) or to the
memory array.

RST#

Input

Reset: When RST# is a logic LOW#, the device is in reset mode, which
drives the outputs to High-Z and resets the write state machine (WSM).
When RST# is at logic HIGH, the device is in standard operation. When
RST# transitions from logic LOW to logic HIGH, the device resets all blocks
to locked and defaults to the read array mode.

WP#

Input

Write Protect: Controls the lock down function of the flexible locking
feature.

Input

Program/Erase Enable: [1.8V3.3V] Operates as input at logic levels to
control complete device protection. Provides factory programming
compatibility when driven to 11.4V12.6V.

E7, F7, D5, E5,

F4, D3, E3, F2,

D6, E6, F6, D4,

E4, F3, D2, E2

DQ0DQ15

Input/Output Data Inputs/Outputs: Input array data on the second CE# and WE# cycle

during PROGRAM command. Input commands to the command user
interface when CE# and WE# are active. DQ0DQ15 output data when
CE# and OE# are active.

E8, F1

Supply

Do not float any ground ball.

Supply

Device Power Supply: [2.7V3.3V] Supplies power for device operation.

Supply

I/O Power Supply: [2.2V3.3V] Supplies power for input/output buffers.

Internally not connected.

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Command State Machine (CSM)

Commands are issued to the command state

machine (CSM) using standard microprocessor write
timings. The CSM acts as an interface between exter-
nal microprocessors and the internal WSM. The avail-
able commands are listed in Table 3, their definitions
are given in Table 4, and their descriptions in Table 5.
Program and erase algorithms are automated by an
on-chip WSM. For more specific information about
the CSM transition states, see Micron technical note
TN-28-33, Command State Machine Description and
Command Definition.

Once a valid PROGRAM/ERASE command is

entered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally and accomplish the
requested operation. A command is valid only if the
exact sequence of WRITEs is completed. After the
WSM completes its task, the WSM status bit (SR7) (see
Table 8) is set to a logic HIGH level (1), allowing the
CSM to respond to the full command set again.

Operations

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/Os DQ0DQ7. The number of bus cycles required to
activate a command is typically one or two. The first
operation is always a WRITE. Control signals CE# and
WE# must be at a logic LOW level (V

), and OE# and

RST# must be at logic HIGH (V

). The second opera-

tion, when needed, can be a WRITE or a READ
depending upon the command. During a READ opera-
tion, control signals CE# and OE# must be at a logic
LOW level (V

), and WE# and RST# must be at logic

HIGH (V

Table 6 shows the bus operations for all the modes:

write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of oper-
ation. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two memory partitions, an on-chip status regis-
ter is available. These two registers allow the progress
of the various operations that can take place on a
memory bank to be monitored. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specify-
ing an address within the memory partition boundary,
and reading the register data on I/Os DQ0DQ7 (cycle
2). Status register bits SR0SR7 correspond to DQ0
DQ7 (see Table 8).

Command Definition

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 4 for the CSM command defini-
tions and data for each of the bus cycles.

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Status Register

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling OE# and CE# and reading the resulting sta-
tus code on I/Os DQ0DQ7. The high-order I/Os
(DQ8DQ15) are set to 00h internally, so only the low
order I/Os (DQ0DQ7) need to be interpreted. Address
lines select the status register pertinent to the selected
memory partition.

edge of OE# or CE#, whichever occurs last. Latching
the data prevents errors from occurring if the register
input changes during a status register read.

The status register provides the internal state of the

WSM to the external microprocessor. During periods
when the WSM is active, the status register can be
polled to determine the WSM status. Table 8 defines
the status register bits.

After monitoring the status register during a PRO-

GRAM/ERASE operation, the data appearing on DQ0
DQ7 remains as status register data until a new com-
mand is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.

Command State Machine Operations

The CSM decodes instructions for read array, read

protection configuration register, read query, read sta-
tus register, clear status register, program, erase, erase
suspend, erase resume, program suspend, program
resume, lock block, unlock block, and lock down block,
chip protection program, and set read configuration
register. The 8-bit command code is input to the
device on DQ0DQ7 (see Table 3 for CSM codes,
Table 4 for command definitions, and Table 6 for CSM
transition states). During a PROGRAM or ERASE cycle,
the CSM informs the WSM that a PROGRAM or ERASE
cycle has been requested.

During a PROGRAM cycle, the WSM controls the

program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an ERASE
SUSPEND command only. When the WSM has com-
pleted its task, the WSM status bit (SR7) is set to a logic
HIGH level and the CSM responds to the full com-
mand set. The CSM stays in the current command
state until the microprocessor issues another com-
mand.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when V

is within its correct

voltage range.

Table 3:

Command State Machine Codes for Device Mode Selection

COMMAND DQ0DQ7

CODE ON DEVICE MODE

40h/10h

Program setup/alternate program setup

20h

Block erase setup

30h

Fast programming algorithm setup

50h

Clear status register

60h

Protection configuration setup

70h

Read status register

90h

Read protection configuration register

98h

Read query

B0h

Program/erase suspend

C0h

Protection register program/lock

D0h

Program/erase resume erase confirm

FFh

Read array

01h

Lock Block

2Fh

Lock Down

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

NOTE:

1.BA:Address within the block

IA: Identification code address
ID: Identification code data
LPA: Lock protection register address
PA: Protection register address
PD: Data to be written at location PA
QA: Query code address

QD: Query code data
SRD: Data read from the status register
WA: Word address of memory location to be

written, or read

WD: Data to be written at the location WA
X: "Don't Care"

Table 4:

Command Definitions

COMMAND

FIRST BUS CYCLE

SECOND BUS CYCLE

OPERATION ADDRESS

DATA

OPERATION ADDRESS

DATA

READ ARRAY

WRITE

FFh

READ PROTECTION CONFIGURATION REGISTER

WRITE

90h

READ

READ STATUS REGISTER

WRITE

70h

READ

SRD

CLEAR STATUS REGISTER

WRITE

50h

READ QUERY

WRITE

98h

READ

BLOCK ERASE SETUP

WRITE

20h

WRITE

D0h

PROGRAM SETUP/ALTERNATE PROGRAM SETUP

WRITE

40h/10h

WRITE

FAST PROGRAMMING ALGORITHM SETUP

WRITE

30h

WRITE

D0h

PROGRAM/ERASE SUSPEND

WRITE

B0h

PROGRAM/ERASE RESUME - ERASE CONFIRM

WRITE

D0h

LOCK BLOCK

WRITE

60h

WRITE

01h

UNLOCK BLOCK

WRITE

60h

WRITE

D0h

LOCK DOWN BLOCK

WRITE

60h

WRITE

2Fh

PROTECTION REGISTER PROGRAM

WRITE

C0h

WRITE

PROTECTION REGISTER LOCK

WRITE

LPA

C0h

WRITE

LPA

FFFDh

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Table 5:

Command Descriptions

CODE

DEVICE MODE

BUS CYCLE

DESCRIPTION

10h

Alt. Program Setup

First

Operates the same as a PROGRAM SETUP command.

20h

Erase Setup

First

Prepares the CSM for an ERASE CONFIRM command. If the next
command is not an ERASE CONFIRM command, the command will be
ignored, and the bank will go to the read array mode and wait for
another command.

30h

FPA Setup

First

Prepares the CSM for an FPA CONFIRM command.

40h

Program Setup

First

A two-cycle command: The first cycle prepares for a PROGRAM
operation, and the second cycle latches addresses and data and initiates
the WSM to execute the program algorithm. The Flash device outputs
status register data on the falling edge of OE# or CE#, whichever occurs
first.

50h

Clear Status
Register

First

The WSM can set the block lock status (SR3), program status (SR4), and
erase status (SR5) bits in the status register to "1," but it cannot clear
them to "0." Issuing this command clears those bits to "0."

60h

Protection
Configuration
Setup

First

Prepares the CSM for changes to the block locking status. If the next
command is not BLOCK UNLOCK, BLOCK LOCK, or BLOCK LOCK DOWN,
the command will be ignored, and the device will go to read status
mode.

70h

Read Status
Register

First

Places the device into read status register mode. Reading the device will
output the contents of the status register for the addressed bank. The
device will automatically enter this mode for the addressed bank after a
PROGRAM or ERASE operation has been initiated.

90h

Read Protection
Configuration

First

Puts the device into the read protection configuration mode so that
reading the device will output the manufacturer/device codes or block
lock status.

98h

Read Query

First

Puts the device into read query mode so that reading the device will
output common Flash interface information.

B0h

Program/Erase
Suspend

First

Suspends the currently executing PROGRAM/ERASE operation. The
status register will indicate when the operation has been successfully
suspended by setting either the program suspend (SR2) or erase suspend
(SR6), and the WSM status bit (SR7) to a "1" (ready). The WSM will
continue to idle in the suspend state, regardless of the state of all input
control signals except RST#, which will immediately shut down the WSM
and the remainder of the chip if RST# is driven to V

C0h

Program Device
Protection Register

First

Writes a specific code into the device protection register.

Lock Device
Protection Register

First

Locks the device protection register; data can no longer be changed.

D0h

Erase Confirm

Second

If the previous command was an ERASE SETUP command, then the CSM
will close the address and data latches, and it will begin erasing the
block indicated on the address bus. During programming/erase, the
device will respond only to the READ STATUS REGISTER, PROGRAM
SUSPEND, or ERASE SUSPEND commands and will output status register
data on the falling edge of OE# or CE#, whichever occurs last.

Program/Erase
Resume

First

If a PROGRAM or ERASE operation was previously suspended, this
command will resume the operation.

D0h

FPA Confirm

Second

If the previous command was FPA SETUP, the CSM will latch the address
indicated on the address bus and enter the FPA mode.

FFh

Read Array

First

During the array mode, array data will be output on the data bus.

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

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MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Clear Status Register

The internal circuitry can set, but not clear, the

block lock status bit (SR1), the V

status bit (SR3), the

program status bit (SR4), and the erase status bit (SR5)
of the status register. The CLEAR STATUS REGISTER
command (50h) allows the external microprocessor to
clear these status bits and synchronize to the internal
operations. When the status bits are cleared, the device
returns to the read array mode.

Read Operations

The following READ operations are available: READ

ARRAY, READ PROTECTION CONFIGURATION REG-
ISTER, READ QUERY, and READ STATUS REGISTER.

Read Array

The array is read by entering the command code

FFh on DQ0DQ7. Control signals CE# and OE# must
be at a logic LOW level (V

), and WE# and RST# must

be at logic HIGH level (V

) to read data from the array.

Data is available on DQ0DQ15. Any valid address
within any of the blocks selects that address and allows
data to be read from that address. Upon initial power-
up or device reset, the device defaults to the read array
mode.

Read Protection Configuration Data

The chip identification mode outputs three types of

information: the manufacturer/device identifier, the
block locking status, and the protection register. Two
bus cycles are required for this operation: the chip
identification data is read by entering the command
code 90h on DQ0DQ7 to the bank containing address

0h and the identification code address on the address
lines. Control signals CE# and OE# must be at a logic
LOW level (V

), and WE# and RST# must be at a logic

HIGH level (V

) to read data from the protection con-

figuration register. Data is available on DQ0DQ15.
After data is read from the protection configuration
register, the read array command, FFh, must be issued
to the bank containing address 00h prior to perform-
ing other operations. See Table 10 for further details.

Read Query

The read query mode outputs common flash inter-

face (CFI) data when the device is read (see Table 12).
Two bus cycles are required for this operation. It is pos-
sible to access the query by writing the read query
command code 98h on DQ0DQ7 to the bank contain-
ing address 0h. Control signals CE# and OE# must be
at a logic LOW level (V

), and WE# and RST# must be

at a logic HIGH level (V

) to read data from the query.

The CFI data structure contains information such as
block size, density, command set, and electrical speci-
fications. After reading CFI data, the READ ARRAY
command (FFh) must be issued to the bank containing
address 00h prior to performing other operations.

Read Status Register

The status register is read by entering the command

code 70h on DQ0DQ7. Two bus cycles are required for
this operation: one to enter the command code and
the block address and a second to read the status regis-
ter. In a READ cycle, the address is latched and register
data is updated on the falling edge of OE# or CE#,
whichever occurs last.

.85

01h

Lock Block

Second

If the previous command was PROTECTION CONFIGURATION SETUP, the
CSM will latch the address and lock the block indicated on the address
bus.

2Fh

Lock Down

Second

If the previous command was PROTECTION CONFIGURATION SETUP, the
CSM will latch the address and lock down the block indicated on the
address bus.

D0h

Unlock Block

Second

If the previous command was PROTECTION CONFIGURATION SETUP, the
CSM will latch the address and unlock the block indicated on the address
bus. If the block had been previously set to lock down, this operation
will have no effect.

00h

Invalid/Reserved

Unassigned command that should not be used.

Table 5:

Command Descriptions (Continued)

CODE

DEVICE MODE

BUS CYCLE

DESCRIPTION

2 MEG x 16

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Table 6:

Command State Machine Transition Table

Command input to the present partition (and next state of the present partition)

Present State of Present
Partition

Present State
of the other
Partition

2Fh
Lock
Down
Confirm

01h
Lock
Confirm

C0h
OTP
Setup

60h
Lock/
Unlock/
Lock
Down

98h
Read
Query

90h
Read
Device
ID

50h
Clear
Status
Register

70h
Read
Status

B0h
Program
/Erase
Suspend

D0h BE
Confirm,
P/E
Resume,
ULB
Confirm

20h
Erase
Setup

10h/40h
Program
Setup

30h
FPA
Setup

FFh
Read
Array

SR7

Data
When
Read

State

Mode

Read array

Read

query

Read

Read
array

Read

status

Read array

Array

Read

Setup

Busy

Read array

OTP

setup

Read array

Erase
setup

Program setup

Read
array

Idle

Read array

Erase

Susp

Read array

Prog
Susp

Read array

Read
query

Read

Read
array

Read
status

Read array

CFI

Query

Setup

Busy

Read array

OTP

setup

Read array

Erase
setup

Program setup

Read
array

Idle

Read array

Erase

Susp

Read array

Prog
Susp

Read array

Read

query

Read

Read
array

Read

status

Read array

Device

Setup

Lock/

Unlock/

Lock

down

Busy

Read array

OTP

setup

Read array

Erase
setup

Program setup

Read
array

Idle

Read array

Erase

Susp

Read array

Prog
Susp

Read array

Read

query

Read

Read
array

Read

status

Read array

Status

Setup

Busy

Read array

OTP

setup

Read array

Erase
setup

Program setup

Read
array

Idle

Read array

Erase

Susp

Read array

Prog
Susp

Protection register busy

Status

Setup

Prot reg

Idle

Protection register busy

Status

Busy

Idle

Read array

Lock/

Unlock/

Lock

down

Read

query

Read

Read
array

Read

status

Read array

Status

Done

Setup

Busy

Read array

OTP

setup

Read array

Erase
setup

Program setup

Read
array

Idle

Read array

Erase

Susp

Read array

Prog
Susp

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

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MT28F322P3FJ_F.fm - Rev. F 7/03 EN

LB/ULB

Read Status

LB/ULB

Read status

Status

Setup

Unlock/

lock

down

Any

state

Read array

Lock/

Unlock/

Lock

down

Read

query

Read

Read
array

Read

status

Read array

Status

Error

Setup

Busy

Read array

OTP

setup

Read array

Erase setup

Program setup

Read
array

Idle

Read array

Erase

susp

Read array

Prog

susp

Read array

Read

query

Read

Read
array

Read

status

Read array

Status

Lock/

Unlock

Setup

Busy

Read array

OTP

setup

Read array

Erase setup

Program setup

Read
array

Idle

Read array

Erase

susp

Read array

Prog

susp

Program Busy

Status

Setup

Prog

Any

state

Program Busy

PS read

status

Program busy

Status

Busy

Idle

Read array

Lock/

Unlock/

Lock

down

Read

query

Read

Read
array

Read

status

Read array

Setup

Busy

Read array

OTP

setup

Read array

Erase setup

Program setup

Read
array

Read array

Idle

Read array

Erase

susp

Read array

Prog

susp

Program Read array

Prog

susp

read

query

Prog

susp

read

Prog

susp
read

array

Prog

susp

read

status

Prog

susp

read

array

Program

busy

Program suspend read array

Status

Read

status

Prog

susp

Setup

Idle

Erase

susp

Program suspend read

array

Prog

susp

read

query

Prog

susp

read

Prog

susp
read

array

Prog

susp

read

status

Prog

susp

read

array

Program

busy

Program suspend read array

Array

Read
array

Setup

Idle

Erase

susp

Program suspend read

array

Prog

susp

read

query

Prog

susp

read

Prog

susp
read

array

Prog

susp

read

status

Prog

susp

read

array

Program

busy

Program suspend read array

Read

Setup

Idle

Erase

susp

Program suspend read

array

Prog

susp

read

query

Prog

susp

read

Prog

susp
read

array

Prog

susp

read

status

Prog

susp

read

array

Program

busy

Program suspend read array

CFI

Read

query

Setup

Idle

Erase

susp

Table 6:

Command State Machine Transition Table (Continued)

Command input to the present partition (and next state of the present partition)

Present State of Present
Partition

Present State
of the other
Partition

2Fh
Lock
Down
Confirm

01h
Lock
Confirm

C0h
OTP
Setup

60h
Lock/
Unlock/
Lock
Down

98h
Read
Query

90h
Read
Device
ID

50h
Clear
Status
Register

70h
Read
Status

B0h
Program
/Erase
Suspend

D0h BE
Confirm,
P/E
Resume,
ULB
Confirm

20h
Erase
Setup

10h/40h
Program
Setup

30h
FPA
Setup

FFh
Read
Array

SR7

Data
When
Read

State

Mode

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

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Read array

Erase

busy

Read array

Status

Setup

Erase

Idle

Read array

Lock/

Unlock/

Lock

down

Read

query

Read

Read
array

Read

status

Read array

Status

Error

Setup

Busy

Read array

OTP

setup

Read array

Erase setup

Program setup

Read
array

Idle

Read array

Erase

susp

Read array

Prog

susp

Read array

Read

query

Read

Read
array

Read

status

Read array

Status

Done

Setup

Busy

Read array

OTP

setup

Read array

Erase setup

Program setup

Read
array

Idle

Read array

Erase

susp

Read array

Prog

susp

Block erase busy

ES read

status

Erase busy

Status

Busy

Idle

Erase suspend read array

Lock/

Unlock/

Lock

down

Erase

susp

read

query

Erase

susp

read

Erase

susp
read

array

Erase

susp

read

status

ES read

array

Erase

busy

Erase suspend read array

Status

Read

status

Erase

Susp

Setup

Erase suspend read array

Busy

ES read

array

Erase

busy

read

array

Program setup

read

array

Idle

Erase suspend read array

Prog

susp

Erase suspend read array

Erase

susp

read

query

Erase

susp

read

Erase

susp
read

array

Erase

susp

read

status

ES read

array

Erase

busy

Erase suspend read array

Array

Read
array

Setup

Erase suspend read array

Busy

ES read

array

Erase

busy

read

array

Program setup

read

array

Idle

Erase suspend read array

Prog

susp

Erase suspend read array

Erase

susp

read

query

Erase

susp

read

Erase

susp
read

array

Erase

susp

read

status

ES read

array

Erase

busy

Erase suspend read array

Read

Setup

Erase suspend read array

Busy

ES read

array

Erase

busy

read

array

Program setup

read

array

Idle

Erase suspend read array

Prog

susp

Erase suspend read array

Erase

susp

read

query

Erase

susp

read

Erase

susp
read

array

Erase

susp

read

status

ES read

array

Erase

busy

Erase suspend read array

CFI

Read

query

Setup

Erase suspend read array

Busy

ES read

array

Erase

busy

read

array

Program setup

read

array

Idle

Erase suspend read array

Prog

susp

Table 6:

Command State Machine Transition Table (Continued)

Command input to the present partition (and next state of the present partition)

Present State of Present
Partition

Present State
of the other
Partition

2Fh
Lock
Down
Confirm

01h
Lock
Confirm

C0h
OTP
Setup

60h
Lock/
Unlock/
Lock
Down

98h
Read
Query

90h
Read
Device
ID

50h
Clear
Status
Register

70h
Read
Status

B0h
Program
/Erase
Suspend

D0h BE
Confirm,
P/E
Resume,
ULB
Confirm

20h
Erase
Setup

10h/40h
Program
Setup

30h
FPA
Setup

FFh
Read
Array

SR7

Data
When
Read

State

Mode

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

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Programming Operations

A PROGRAM operation is iniated by a command

sequence to the CSM: PROGRAM SETUP (40h) or
ALTERNATE PROGRAM SETUP (10h), followed by the
correct address and data. Once the program command
sequence has been entered, the CSM automatically
enters into the status read mode. To access the status
of the entered command, a READ of the device at the
address given in the first cycle will provide the relevant
status of the command. See Figure 4 on page 19 for
details.

After the desired command code is entered (10h or

40h command code on DQ0DQ7), the WSM takes
over and correctly sequences the device to complete
the PROGRAM operation. The WRITE operation may
be monitored through the status register (see the Sta-
tus Register section). During this time, the CSM will
only respond to a PROGRAM SUSPEND command
until the PROGRAM operation has been completed,
after which time all commands to the CSM become
valid again. After the PROGRAM operation is com-
plete, the READ ARRAY command (FFh) must be given
to the same partition to clear the CSM.

The PROGRAM operation can be suspended by

issuing a PROGRAM SUSPEND command (B0h). Once
the WSM reaches the suspend state, it allows the CSM
to respond only to READ ARRAY, READ STATUS REG-
ISTER, READ PROTECTION CONFIGURATION, READ
QUERY, or PROGRAM RESUME. During the PROGRAM
SUSPEND operation, array data should be read from
an address other than the one being programmed. To
resume the PROGRAM operation, a PROGRAM
RESUME command (D0h) must be issued to the sus-
pended partition, causing the CSM to clear the sus-
pend state previously set (see Figure 4 for
programming operation and Figure 5 for program sus-
pend and program resume). The RESUME command
(D0h) must not be given to a ready partition when the
other partition is suspended. Doing so could cause the
suspended partition to resume.

Taking RST# to VIL during programming aborts the

PROGRAM operation. During programming, V

must

remain in the appropriate V

voltage range as shown

in the recommended operating conditions table.

Fast Programming Algorithm (FPA)
Mode

The fast programming algorithm (FPA) is intended

for in-factory use. It enables fast data stream program-
ming.

For in-factory programming, the FPA, along with an

optimized set of programming parameters, minimizes
chip programming time when 11.4V < V

12.6V.

Executing the FPA command (30h), followed by FPA

CONFIRM (D0h), enables an entire block to be pro-
grammed. This eliminates the need to continuously
update the address to be programmed.

An initial delay is required after issuing the FPA

command. (See the Erase and Program Cycle Timing
Requirements Table.) The delay enables the device to
detect 12V on V

. If V

< 11.4V, or if the block is

locked, the status register returns an error. When the
FPA command is executed successfully, a data stream
can be programmed beginning at the first address. The
address can be held constant, or it can be incremented
within the address range. The program ends when the
programmer enters an address outside the address
range of the current block.

When the FPA is activated, the data must be pro-

vided in sequential order to the WSM. Immediately
after programming, verification is executed. The
address sequence is again provided to the WSM, which
automatically performs a data consistency check
between the data stored in the memory array, and the
programmed data. The result is stored in the status
register. Issuing an address outside the memory block
boundaries exits the verification cycle. Figure 8 shows
the FPA flowchart.

Erase Operations

An ERASE operation must be used to initialize all

bits in an array block to "1s." After BLOCK ERASE con-
firm is issued, the CSM responds only to an ERASE
SUSPEND command until the WSM completes its task.

Block erasure inside the memory array sets all bits

within the address block to logic 1s. Erase is accom-
plished only by blocks; data at single address locations
within the array cannot be erased individually. The
block to be erased is selected by using any valid
address within that block. Block erasure is initiated by
a command sequence to the CSM: BLOCK ERASE
setup (20h) followed by BLOCK ERASE CONFIRM
(D0h) (see Figure 6). A two-command erase sequence
protects against accidental erasure of memory con-
tents.

Once the BLOCK ERASE CONFIRM command is

entered, the CSM automatically enters into status read
mode. To access the status of the entered commmand,
a READ of the device at the address given in the first
cycle will provide the relevant status of the command.
See Figure 6 on page 21 for details.

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

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MT28F322P3FJ_F.fm - Rev. F 7/03 EN

When the BLOCK ERASE CONFIRM command is

complete, the WSM automatically executes a sequence
of events to complete the block erasure. During this
sequence, the block is programmed with logic 0s, data
is verified, all bits in the block are erased, and finally
verification is performed to ensure that all bits are cor-
rectly erased. The ERASE operation may be monitored
through the status register (see the Status Register sec-
tion). After the ERASE operation is complete, the READ
ARRAY command (FFh) must be given to the same
partition to clear the CSM.

During the execution of an ERASE operation the

ERASE SUSPEND command (B0h) can be entered to
direct the WSM to suspend the ERASE operation. Once
the WSM has reached the suspend state, it allows the
CSM to respond only to the READ ARRAY, READ STA-
TUS REGISTER, READ QUERY, READ CHIP PROTEC-

TION CONFIGURATION, PROGRAM SETUP,
PROGRAM RESUME, ERASE RESUME and LOCK
SETUP (see the Block Locking section). During the
ERASE SUSPEND operation, array data must be read
from a block other than the one being erased. To
resume the ERASE operation, an ERASE RESUME
command (D0h) must be issued to cause the CSM to
clear the suspend state previously set (see Figure 7). It
is also possible to suspend an ERASE in any bank and
initiate a WRITE to another block in the same bank.
After the completion of a WRITE, an ERASE can be
resumed by writing an ERASE RESUME command.
The RESUME command (D0h) must not be given to a
ready partition when the other partition is suspended.
Doing so could cause the suspended partition to
resume.

Table 7:

Bus Operations

MODE

RST#

CE#

OE#

WE#

ADDRESS

DQ0DQ15

Read (array, status registers, device
identification register, or query)

OUT

Standby

High-Z

Output Disable

High-Z

Reset

High-Z

Write

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

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MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Table 8:

Status Register Bit Definition

WSMS

ESS

PSS

BLS

FPAS

STATUS

BIT #

STATUS REGISTER BIT

DESCRIPTION

SR7

WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy

Check write state machine bit first to determine word
program or block erase completion, before checking
program or erase status bits.

SR6

ERASE SUSPEND STATUS (ESS)
1 = BLOCK ERASE Suspended
0 = BLOCK ERASE in Progress/Completed

When ERASE SUSPEND is issued, WSM halts execution
and sets both WSMS and ESS bits to "1." ESS bit
remains set to "1" until an ERASE RESUME command is
issued.

SR5

ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful BLOCK ERASE

When this bit is set to "1," WSM has applied the
maximum number of erase pulses to the block and is
still unable to verify successful block erasure.

SR4

PROGRAM STATUS (PS)
1 = Error in PROGRAM
0 = Successful PROGRAM

When this bit is set to "1," WSM has attempted but
failed to program a word.

SR3

STATUS (V

1 = V

Low Detect, Operation Abort

0 = V

= OK

The V

status bit does not provide continuous

indication of the V

level. The WSM interrogates the

level only after the program or erase command

sequences have been entered and informs the system if
V

< 1.8V. The V

level is also checked before the

PROGRAM/ERASE operation is verified by the WSM.

SR2

PROGRAM SUSPEND STATUS (PSS)
1 = PROGRAM Suspended
0 = PROGRAM in Progress/Completed

When PROGRAM SUSPEND is issued, WSM halts
execution and sets both WSMS and PSS bits to "1." PSS
bit remains set to "1" until a PROGRAM RESUME
command is issued.

SR1

BLOCK LOCK STATUS (BLS)
1 = PROGRAM/ERASE Attempted on a
Locked Block; Operation Aborted
0 = No Operation to Locked Blocks

If a PROGRAM or ERASE operation is attempted to one
of the locked blocks, this is set by the WSM. The
operation specified is aborted and the device is
returned to read status mode.

SR0

FAST PROGRAMMING
ALGORITHM STATUS (FPAS)
1 = FPA PROGRAM/ERASE Busy
0 = FPA Ready

When this bit is set to "1," the FPA algorithm is active.
When the FPA operation is complete, this bit is reset to
"0."

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

09005aef808cfe29

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MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Figure 4: Automated Word

Programming Flowchart

NOTE:

1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program oper-

ation attempts.

YES

Full Status Register

Check (optional)

YES

PROGRAM

SUSPEND?

SR7 = 1?

Issue PROGRAM SETUP

Command and

Word Address

Start

Word Program Passed

Range Error

Word Program Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

Issue Word Address

and Word Data

PROGRAM

SUSPEND Loop

Issue READ ARRAY

Command (FFh)

YES

SR1 = 0?

YES

SR3 = 0?

YES

SR4 = 0?

Word Program

Completed

Read Status Register

Bits

PROGRAM Attempted

on a Locked Block

BUS
OPERATION

COMMAND COMMENTS

WRITE

WRITE
PROGRAM
SETUP

Data = 40h or 10h
Addr = Address of word to

be programmed

WRITE

WRITE
DATA

Data = Word to be

programmed

Addr = Address of word to

be programmed

READ

Status register data
Toggle OE# or CE# to
update status register.

Standby

Check SR7
1 = Read, 0 = Busy

WRITE

READ
ARRAY

Data = FFh
Addr = Bank of word to

be programmed

Repeat for subsequent words.
Write FFh after each word programming operation to
clear the CSM and reset the device to read array mode.

BUS
OPERATION

COMMAND COMMENTS

Standby

Check SR1
1 = Detect locked block

Standby

Check SR3

1 = Detect V

LOW

Standby

Check SR4

1 = Word program error

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

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MT28F322P3FJ_F.fm - Rev. F 7/03 EN

Figure 5: PROGRAM/SUSPEND/

PROGRAM/RESUME Flowchart

NOTE:

1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before

full status is checked.

Issue READ ARRAY

Command

PROGRAM

Complete

Finished
Reading

Issue PROGRAM

RESUME Command

YES

SR2 = 1?

Start

PROGRAM Resumed

Read Status Register

Bits

Issue PROGRAM

SUSPEND Command

YES

SR7 = 1?

BUS
OPERATION

COMMAND COMMENTS

WRITE

PROGRAM
SUSPEND

Data = B0h

READ

Status register data
Toggle OE# or CE# to
update status register

Standby

Check SR7
1 = Ready

Standby

Check SR2
1 = Suspended

WRITE

READ
ARRAY

Data = FFh

READ

Read data from block
other than that being
programmed.

WRITE

PROGRAM
RESUME

Data = D0h

2 MEG x 16

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Figure 6: BLOCK ERASE Flowchart

NOTE:

1. Full status register check can be done after each block or after a sequence of blocks.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before

full status is checked.

YES

Full Status Register

Check (optional)

YES

ERASE

SUSPEND?

SR 7 = 1?

Start

BLOCK ERASE Passed

Range Error

BLOCK ERASE Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

ERASE

SUSPEND Loop

Issue READ ARRAY

Command (FFh)

YES

SR1 = 0?

YES

BLOCK ERASE

Completed

Read Status Register

Bits

ERASE Attempted
on a Locked Block

SR3 = 0?

SR5 = 0?

Issue ERASE SETUP

Command and

Block Address

Issue BLOCK ERASE

CONFIRM Command

and Block Address

BUS
OPERATION

COMMAND COMMENTS

WRITE

WRITE
ERASE
SETUP

Data = 20h
Block Addr = Address
within block to be erased

WRITE

ERASE

Data = D0h
Block Addr = Address
within block to be erased

READ

Status register data
Toggle OE# or CE# to
update status register.

Standby

Check SR7
1 = Read, 0 = Busy

WRITE

READ
ARRAY

Data = FFh
Block Addr = Bank of word
to be programmed

Repeat for subsequent words
Write FFh after each BLOCK ERASE operation to clear the
CSM and reset the device to read array mode.

BUS
OPERATION

COMMAND COMMENTS

Standby

Check SR1
1 = Detect locked block

Standby

Check SR3

1 = Detect V

block

Standby

Check SR5

1 = BLOCK ERASE error

2 MEG x 16

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Figure 7: ERASE SUSPEND/ERASE

RESUME Flowchart

NOTE:

1. See BLOCK ERASE Flowchart for complete erasure procedure.

2. See Word Programming Flowchart for complete programming procedure.

READ

PROGRAM

Issue READ ARRAY

Command

PROGRAM

Loop

ERASE

Complete

READ or

PROGRAM?

YES

Issue ERASE

RESUME Command

READ or

PROGRAM
Complete?

YES

SR6 = 1?

Start

ERASE Continued

Read Status Register

Bits

Issue ERASE

SUSPEND Command

(Note 1)

YES

SR7 = 1?

BUS
OPERATION

COMMAND COMMENTS

WRITE

ERASE
SUSPEND

Data = B0h

READ

Status register data
Toggle OE# or CE# to
update status register

Standby

Check SR7
1 = Ready

Standby

Check SR6
1 = Suspended

WRITE

READ
ARRAY

Data = FFh

READ

Read data from block
other than that being
erased.

WRITE

ERASE
RESUME

Data = D0h

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Figure 8: Fast Programming Algorithm Flowchart

Start

FPA Setup

Exit

Operation

Complete

WRITE 30h

Address = WA

WRITE D0h

Address = WA

FPA Setup Time

Read

Status Register

Check V

and

Lock Errors

(SR3, SR1)

Note: 1. WA: Word address of memory location to be written.

First address may be held constant or incremented within the address range.
2. BA: Address within the block.

= 12V

Unlock Block

SR7 = 0

SR7 = 1

FPA Setup

Done?

WRITE Data

Address = WA

Read

Status Register

WRITE FFFFh

Address

Read

Status Register

SR0 = 0

SR0 = 1

SR0 = 0

SR0 = 1

Yes

SR0 = 0

SR0 = 1

Yes

Data

Stream Ready?

Program

Done?

Last Data?

WRITE Data

Address = WA

Read

Status Register

WRITE FFFFh

Address

Read

Status Register

SR0 = 0

SR0 = 1

Verify

Stream Ready?

Verify

Done?

Last Data?

Full Status

Check Procedure

Read

Status Register

SR7 = 1

SR7 = 0

FPA

Exited?

FPA Program

FPA Verify

FPA Exit

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Read-While-Write/Erase Concurrency

It is possible for the device to read from one bank

while erasing/writing to another bank. Once a bank
enters the WRITE/ERASE operation, the other bank
automatically enters read array mode. For example,
during a READ CONCURRENCY operation, if a PRO-
GRAM/ERASE command is issued in bank a, then
bank a changes to the read status mode and bank b
defaults to the read array mode. The device will read
from bank b if the latched address resides in bank b
(see Figure 9). Similarly, if a PROGRAM/ERASE com-
mand is issued in bank b, then bank b changes to read
status mode and bank a defaults to read array mode.
When returning to bank a, the device will read PRO-
GRAM/ERASE status if the latched address resides in
bank a. A correct bank address must be specified to
read status register after returning from concurrent
read in the other bank.

When reading the CFI or the chip protection regis-

ter, concurrent operation is not allowed on the top
boot device. Concurrent READ of the CFI or the chip
protection register is only allowed when a PROGRAM
or ERASE operation is performed on bank b on the

bottom boot device. For a top boot device, reading of
the CFI table or the chip protection register is only
allowed if bank a is in read array mode.

Figure 9: Read-While-Write

Concurrency

Bank a
1 - Erasing/writing to bank a
2 - Erasing in bank a can be

suspended, and a WRITE to
another block in bank a
can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.

1 - Reading bank a

Bank b

1 - Reading from bank b

1 - Erasing/writing to bank b
2 - Erasing in bank b can be

suspended, and a WRITE to
another block in bank b
can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.

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Block Locking

The MT28F322P3 Flash memory provides a flexible

locking scheme which allows each block to be individ-
ually locked or unlocked with no latency.

The device offers two-level protection for the

blocks. The first level allows software-only control of
block locking (for data which needs to be changed fre-
quently), while the second level requires hardware
interaction before locking can be changed (code which
does not require frequent updates).

Control signals WP#, DQ0, and DQ1 define the state

of a block; for example, state [001] means WP# = 0,
DQ0 = 0 and DQ1 = 1.

Table 9 defines all of the possible locking states.

NOTE: All blocks are software-locked upon

power-up sequence completion.

Locked State

After a power-up sequence completion, or after a

reset sequence, all blocks are locked (states [001] or
[101]). This means full protection from alteration. Any
PROGRAM or ERASE operations attempted on a
locked block will return an error on bit SR1 of the sta-
tus register. The status of a locked block can be
changed to unlocked or lock down using the appropri-
ate software commands. Writing the lock command
sequence, 60h followed by 01h, can lock an unlocked
block.

Unlocked State

Unlocked blocks (states [000], [100], [110]) can be

programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked
down using the appropriate software command
sequence, 60h followed by 01h or 2Fh, respectively.
(see Table 4).

Locked down blocks revert to the locked state when

the device is reset or powered down (see Table 4).

Locked Down State

Blocks that are locked down (state [011]) are pro-

tected from PROGRAM and ERASE operations, but
their protection status cannot be changed using soft-
ware commands alone. A locked or unlocked block can
be locked down by writing the lock down command
sequence, 60h followed by 2Fh. Locked down blocks
revert to the locked state when the device is reset or
powered down.

The LOCK DOWN function is dependent on the

WP# input. When WP# = 0, blocks in lock down [011]
are protected from program, erase, and lock status
changes. When WP# = 1, the lock down function is dis-
abled ([111]), and locked down blocks can be individu-
ally unlocked by a software command to the [110]
state, where they can be erased and programmed.
These blocks can then be relocked [111] and unlocked
[110] as desired while WP# remains HIGH. When WP#
goes LOW, blocks that were previously locked down
return to the locked down state [011] regardless of any
changes made while WP# was HIGH. Device reset or
power-down resets all locks, including those in lock
down, to locked state (see Table 10).

Reading a Block's Lock Status

The lock status of every block can be read in the

read device identification mode. To enter this mode,
write 90h to the bank containing address 00h. Subse-
quent READs at block address +00002 will output the
lock status of that block. The lowest two outputs, DQ0
and DQ1, represent the lock status. DQ0 indicates the
block lock/unlock status and is set by the LOCK com-

Table 9:

Block Locking State Transition

WP#

DQ1

DQ0

NAME

ERASE/PROGRAM

ALLOWED

LOCK

UNLOCK

LOCK DOWN

Unlocked

Yes

To [001]

No Change

To [011]

Locked (Default)

No Change

To [000]

To [011]

Lock Down

No Change

Unlocked

Yes

To [101]

No Change

To [111]

Locked

No Change

To [100]

To [111]

Lock Down

Disabled

Yes

To [111]

No Change

To [111]

Lock Down

Disabled

No Change

To [110]

No Change

2 MEG x 16

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mand and cleared by the UNLOCK command. It is also
automatically set when entering lock down. DQ1 indi-
cates lock down status and is set by the LOCK DOWN
command. It can only be cleared by reset or power-
down, not by software. Table 9 shows the locking state
transition scheme. The read array command, FFh,
must be issued to the bank containing address 00h
prior to performing other operations.

Locking Operations During Erase Suspend

Changes to block lock status can be performed dur-

ing an ERASE SUSPEND by using the standard locking
command sequences to unlock, lock, or lock down.
This is useful in the case when another block needs to
be updated while an ERASE operation is in progress.

To change block locking during an ERASE opera-

tion, first write the ERASE SUSPEND command (B0h),
then check the status register until it indicates that the
ERASE operation has been suspended. Next, write the
desired lock command sequence to block lock, and the
lock status will be changed. After completing any
desired LOCK, READ, or PROGRAM operations,
resume the ERASE operation with the ERASE RESUME
command (D0h).

If a block is locked or locked down during an ERASE

SUSPEND on the same block, the locking status bits
will be changed immediately. When the ERASE is
resumed, the ERASE operation will complete.

A locking operation cannot be performed during a

PROGRAM SUSPEND.

Chip Protection Register

A 128-bit chip protection register can be used to ful-

fill the security considerations in the system (prevent-
ing the device substitution).

The 128-bit security area is divided into two 64-bit

segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit unchangeable
number. The other segment is left blank for customers
to program as desired. (See Figure 10).

Reading the Chip Protection Register
The chip protection register is read in the device iden-
tification mode. To enter this mode, load the 90h com-
mand to the bank containing address 00h. Once in this
mode, READ cycles from addresses shown in Table 10
retrieve the specified information. To return to the
read array mode, write the READ ARRAY command

(FFh). The READ ARRAY command, FFh, must be
issued to the bank containing address 00h prior to per-
forming other operations.

Programming the Chip Protection
Register

The first 64 bits (PR1) of the protection register

(addresses 81h84h) are programmed with a unique
identifier at the factory. DQ0 of the PR lock register
(address 80h) is programmed to a "0" state, locking the
first 64 bits and preventing any further programming.

The second 64 bits (PR2) are a user area (addresses

85h88h), where the user can program any informa-
tion into this area as long as DQ1 of the PR lock register
remains unprogrammed. After DQ1 of the PR lock reg-
ister is programmed, no further programming is
allowed on PR2. The programming sequence is similar
to array programming except that the PROTECTION
REGISTER PROGRAMMING SETUP command (C0h) is
issued instead of an ARRAY PROGRAMMING SETUP
command (40h), followed by the data to be pro-
grammed at addresses 85h88h.

To program the PR lock bit for PR2 (to prevent fur-

ther programming), use the above sequence on
address 80h, with data FFFDh (DQ1 = 0).

Figure 10: Protection Register Memory

Map

4 Words

Factory-Programmed

4 Words

User-Programmed

PR Lock

88h

85h

84h

81h

80h

DQ1

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NOTE:1.Other locations within the configuration address space are reserved by Micron for future use.

2."XX" specifies the block address of lock configuration.

Asynchronous Read Cycle

When accessing addresses in a random order or

when switching between pages, the access time is
given by

AA.

When CE# and OE# are LOW, the data is placed on

the data bus and the processor can read the data.

Page Read Mode

The initial portion of the page mode cycle is the

same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0A2 allows random
access of other words in the page. The page word size
is eight words.

Program and Erase Voltages

The MT28F322P3 Flash memory provides in-system

programming and erase with V

in the 1.8V3.3V

range. The 12V V

mode programming is offered for

compatibility with existing programming equipment,
but does not enhance programming performance
using the standard programming commands.

The device can withstand 100,000 WRITE/ERASE

operations when V

= V

or 100 WRITE/ERASE oper-

ations and 10 cumulative hours when V

= 12V.

In addition to the flexible block locking, the V

pro-

gramming voltage can be held LOW for absolute hard-
ware write protection of all blocks in the Flash device.
When V

is below V

PPLK

, any PROGRAM or ERASE

operation will result in an error, prompting the corre-
sponding status register bit (SR3) to be set.

During WRITE and ERASE operations, the WSM

monitors the V

voltage level. WRITE/ERASE opera-

tions are allowed only when V

is within the ranges

specified in Table 11.

When V

is below V

LKO

, any WRITE/ERASE opera-

tion will be disabled.

Standby Mode

supply current is reduced by applying a logic

HIGH level on CE# and RST# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on CE# and
RST# reduces the current to I

3 (MAX). If the device is

deselected during an ERASE operation or during pro-
gramming, the device continues to draw current until
the operation is complete.

Automatic Power Save (APS) Mode

Substantial power savings are realized during peri-

ods when the array is not being read and the device is
in the active mode. During this time the device
switches to the automatic power save mode. When the
device switches to this mode, I

is reduced to a level

comparable to I

3. Further power savings can be real-

Table 10: Chip Configuration Addressing

ITEM

ADDRESS

DATA

Manufacturer Code (x16)

00000h

002Ch

Device Code

· Top boot configuration
· Bottom boot configuration

00001h

4494h
4495h

Block Lock Configuration

· Block is unlocked
· Block is locked
· Block is locked down

XX002h

Lock
DQ0 = 0
DQ0 = 1
DQ0 = 1

Chip Protection Register Lock

80h

PR Lock

Chip Protection Register 1

81h84h

Factory Data

Chip Protection Register 2

85h88h

User Data

Table 11: V

Range (V)

MIN

MAX

In-System

1.8

3.3

In-Factory

11.4

12.6

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ized by applying a logic HIGH level on CE# to place the
device in standby mode. The low level of power is
maintained until another operation is initiated. In this
mode, the I/Os retain the data from the last memory
address read until a new address is read. This mode is
entered automatically if no address or control signals
toggle.

Device Reset

To correctly reset the MT28F322P3 Flash memory,

the RST# signal must be asserted (RST# = V

) for a

minimum of

RP. After reset, the device can be

accessed for a READ operation with a delayed access
time of

RWH from the rising edge of RST#. The cir-

cuitry used for generating the RST# signal needs to be

common with the rest of the system reset to ensure
that correct system initialization occurs. Please refer to
the timing diagram for further details.

Power-Up Sequence

The following power-up sequence is recommended

to initialize internal chip operations:
· At power-up, RST# should be kept at V

for 2µs after

reaches V

(MIN).

· V

Q should not come up before V

· V

should be kept at V

to maximize data integrity.

When the power-up sequence is completed, RST#

should be brought to V

. To ensure a proper power-

up, the rise time of RST# (10%90%) should be <10µs.

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Absolute Maximum Ratings*

Voltage to Any Ball Except V

and V

with Respect to V

.................................. -0.5V to +4V

Voltage (for BLOCK ERASE and PROGRAM

with Respect to V

..........................-0.5V to +13.5V**

and V

Q Supply Voltage

with Respect to V

.................................. -0.3V to +4V

Output Short Circuit Current ...............................100mA
Operating Temperature Range ................-40

°C to +85°C

Storage Temperature Range ..................-55

°C to +150°C

Operating Temperature Range ................-40

°C to +85°C

Soldering Cycle ........................................... 260

°C for 10s

*Stresses greater than those listed under "Absolute

Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.

**Maximum DC voltage on V

may overshoot to

+13.5V for periods <20ns.

NOTE:

1. V

= V

2 is a maximum of 10 cumulative hours.

Recommended Operating Conditions

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Operating temperature

-40

+85

°C

supply voltage

2.7

3.3

I/O supply voltage

2.2

3.3

voltage

1.8

3.3

in-factory programming voltage

11.4

12.6

Block erase cycling

= V

100,000

Cycles

= V

100

Cycles

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NOTE:

1. All currents are in RMS unless otherwise noted.

2. V

may decrease to -0.4V, and V

may increase to V

Q + 0.3V for durations not to exceed 20ns.

3. APS mode reduces I

to approximately I

3 levels.

4. Test conditions: V

= V

(MAX), CE# = V

, OE# = V

. All other inputs = V

or V

5. I

6 and I

7 values are valid when the device is deselected. Any READ operation performed while in suspend

mode will have an additional current draw of suspend current (I

6 or I

7).

DC Characteristics

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Input Low Voltage

0.4

Input High Voltage

Q - 0.4

Output Low Voltage
I

= 100

-0.10

0.10

Output High Voltage
I

= -100

Q - 0.1

Lockout Voltage

PPLK

During PROGRAM/ERASE

Operations

1.8

3.3

11.4

12.6

Program/Erase Lock Voltage

LKO

Input Leakage Current

Output Leakage Current

0.2

Read Current

Asynchronous Random Read, 70ns cycle
Asynchronous Random Read, 200ns cycle

mA
mA

3,4

Page Mode Read Current at 70ns/30ns

3,4

Standby Current

Program Current

Erase Current

Erase Suspend Current

Program Suspend Current

Read-While-Write Current

Current

(Read, Standby, Erase Suspend, Program
Suspend)
V

= V

200

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Write Cycle Timing Requirements

PARAMETER

SYMBOL

-70/-80

UNITS

MIN

MAX

RST# HIGH recovery to WE# going LOW

150

CE# setup to WE# going LOW

Write pulse width

Data setup to WE# going HIGH

Address setup to WE# HIGH

CE# hold from WE# HIGH

Data hold from WE# HIGH

Address hold from WE# HIGH

Write pulse width HIGH

WPH

WP# setup to WE# going HIGH

RHS

setup to WE# going HIGH

VPS

200

Write recovery before READ

WOS

WP# hold from valid SRD

RHH

hold from valid SRD

VPH

WE# HIGH to data valid

AA + 50

Erase and Program Cycle Timing Requirements

PARAMETER

-70/-80

UNITS

TYP

MAX

4KW parameter block program time

800

32KW main block program time

320

6,400

Word program time

10,000

4KW parameter block erase time

0.3

32KW main block erase time

0.5

Program suspend latency

Erase suspend latency

Chip programming time (FPA)

FPA setup time

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Table 12: CFI

OFFSET

DATA

DESCRIPTION

2Ch

Manufacturer code

94h

Top boot block device code

95h

Bottom boot block device code

02ñ0F

reserved

Reserved

10, 11

0051, 0052 "QR"

0059

"Y"

13, 14

0003, 0000 Primary OEM command set

15, 16

0039, 0000 Address for primary extended table

17, 18

0000, 0000 Alternate OEM command set

19, 1A

0000, 0000 Address for OEM extended table

0027

MIN for Erase/Write; Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

0033

MAX for Erase/Write; Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

00B4

MIN for Erase/Write; Bit 7bit 4 volts in hex; Bit 3bit 0 100mV in BCD

00C6

MAX for Erase/Write; Bit 7bit 4 volts in hex; Bit 3bit 0 100mV in BCD

0003

Typical timeout for single byte/word program, 2

µs, 0000 = not supported

0000

Typical timeout for maximum size multiple byte/word program, 2

µs, 0000 = not supported

0009

Typical timeout for individual block erase, 2

ms, 0000 = not supported

0000

Typical timeout for full chip erase, 2

s, 0000 = not supported

000C

Maximum timeout for single byte/word program, 2

µs, 0000 = not supported

0000

Maximum timeout for maximum size multiple byte/word program, 2

µs, 0000 = not

supported

0003

Maximum timeout for individual block erase, 2

s, 0000 = not supported

0000

Maximum timeout for full chip erase, 2

s, 0000 = not supported

0016

Device size, 2

bytes

0001

Bus interface x16 = 1

0000

Flash device interface description 0000 = async

2A, 2B

0000, 0000 Maximum number of bytes in multi-byte program or page, 2

0003

Number of erase block regions within device (4K words and 32K words)

2D, 2E

002F, 0000

Top boot block device erase block region information 1, 8 blocks ..

0007, 0000 Bottom boot block device erase block region information 1, 8 blocks ...

2F, 30

0000, 0001 Top boot block device......of 8KB

0020, 0000 Bottom boot block device

......of 8KB

31, 32

000E, 0000 Top boot block 15 blocks of ....

000E, 0000 Bottom boot block 15 blocks of ...

33, 34

0000, 0001 ......64KB

35, 36

0007, 0000 Top boot block device.....48 blocks of

002F, 0000

Bottom boot block device.....48 blocks of

37, 38

0020, 0000 Top boot block device......64KB

0000, 0001 Bottom boot block device......64KB

39, 3A

0050, 0052 "PR"

0049

"I"

0030

Major version number, ASCII

2 MEG x 16

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

0031

Minor version number, ASCII

3E
3F
40
41

00E6
0002
0000
0000

Optional Feature and Command Support
Bit 0 Chip erase supported no = 0
Bit 1 Suspend erase supported = yes = 1
Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes =1
Bit 8 Synchronous read supported = no =0
Bit 9 Simultaneous operation supported = yes = 1

0001

Program supported after erase suspend = yes

43, 44

0003, 0000 Bit 0 block lock status active = yes; Bit 1 block lock down active = yes

0030

supply optimum, 00 = not supported, Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

00C0

supply optimum, 00 = not supported, Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

0001

Number of protection register fields in JEDEC ID space

48, 49

0080, 0000 Lock bytes LOW address, lock bytes HIGH address

4A, 4B

0003, 0003 2

factory programmed bytes, 2

user programmable bytes

0003

Background Operation
0000= Not used
0001 = 4% block split
0002 = 12% block split
0003 = 25% block split
0004 = 505 block split

0000

Burst Mode Type
0000 = No burst mode
00x1 = 4 words MAX
00x2 = 8 words MAX
00x3 = 16 words MAX
001x = Linear burst, and/or
002x = interleaved burst, and/or
004x = Continuous burst

0002

Page Mode Type
0000 = No page mode
0001 = 4-word page
0002 = 8-word page
0003 = 16-word page
0004 = 32-word page

0000

Not used

Table 12: CFI

OFFSET

DATA

DESCRIPTION

2 MEG x 16

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Micron Technology, Inc., reserves the right to change products or specifications without notice..

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

48-Ball FBGA

NOTE:

1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.

DATA SHEET DESIGNATION

No Mark: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature

range for production devices. Although considered final, these specifications are subject to change, as further
product development and data characterization sometimes occur.

.850 ±.075

0.10 C

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 37% Pb, 2%Ag
SOLDER BALL PAD: Ø .27mm

BALL A1 ID

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

10.00 ± .10

3.75

1.876 ±.05

.75
TYP

5.00 ±.05

BALL A1 ID

.75 TYP

3.50 ±.05

5.25

7.00 ±.10

1.20 MAX

2.625 ±.05

BALL A1

BALL A8

SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE
PRE-REFLOW DIAMETER
IS Ø 0.33

0.35

48X Ø

2 MEG x 16

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F322P3FJ_F.fm - Rev. F 7/03 EN

REVISION HISTORY

Rev.F .................................................................................................................................................................................7/03

· Clarified column heading on Table 6
· Clarified default condition after PROGRAM command
· Clarified default condition after ERASE command
· Clarified DQ0 value for PR_LOCK register
· Updated value for

Rev. E ................................................................................................................................................................................4/03

· Added Programming Chip Protection Register section
· Updated Automated Word Programming and Block Erase flowcharts
· Updated Read Query, Programming Operations, Erase Operations, Unlocked State, and Read-While-Write/

Erase Concurrency sections

· Added updated version of the Command State Machine Transition State table

Rev. 4...............................................................................................................................................................................10/02

· PRELIMINARY designation was removed

Rev. 3, PRELIMINARY7/02

· Updated Status Register section
· Updated command descriptions
· Updated flowcharts
· Updated Read-While-Write/Erase Concurrency section
· Updated timing diagrams

Rev. 2, PRELIMINARY......................................................................................................................................................4/02

· Changed

AH from 90ns to 0ns

· Updated Read Chip Protection Identification Data text

Rev. 2, PRELIMINARY......................................................................................................................................................3/02

· Updated DC Characteristics table
· Updated Table 10
· Updated Asynchronous Read Cycle Timing Requirements table
· Updated Write Cycle Timing Requirements table
· Updated timing diagrams and parameters

Original document, PRELIMINARY ...............................................................................................................................1/02

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT28F322P3FJ-80BET