128Mb: x8DDR400 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx8DDR400.p65 Rev. A (1/30/02-B)

128Mb: x8

DDR400 SDRAM Addendum

THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.

PREVIEW

KEY TIMING PARAMETERS

SPEED

CLOCK RATE

DATA-OUT

ACCESS DQS-DQ

GRADE

CL = 3

WINDOW

SKEW

-5

200 MHz

2.15ns

±0.50ns

+0.35ns

NOTE:

1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle

Architecture

16 Meg x 8

Configuration

4 Meg x 8 x 4 banks

Refresh Count

Row Addressing

4K (A0A11)

Bank Addressing

4 (BA0, BA1)

Column Addressing

1K (A0A9)

DOUBLE DATA RATE
(DDR) SDRAM

MT46V16M8 4 Meg x 8 x 4 banks

For the latest data sheet revisions, please refer to the Micron
Web site:

www.micron.com/dramds

FEATURES

· 200 MHz Clock, 400 Mb/s/p data rate
· V

= +2.65V ±0.10V

· V

Q = +2.65V ±0.10V

· Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data
capture

· Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

· Differential clock inputs (CK and CK#)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

· DLL to align DQ and DQS transitions with CK
· Four internal banks for concurrent operation
· Data mask (DM) for masking write data
· Programmable burst lengths: 2, 4, or 8
· Concurrent Auto Precharge option supported
· Auto Refresh and Self Refresh Modes
·

RAS lockout (

RAP =

RCD)

OPTIONS

PART NUMBER

· Configuration

16 Meg x 8 (4 Meg x 8 x 4 banks)

16M8

· Plastic Package

66-Pin TSOP

T G

(400mil with 0.65mm pin pitch)

· Timing - Cycle Time

5ns @ CL = 3

(1)

-5

· Self Refresh

Standard

none

NOTE: 1. Supports modules with 3-4-4 timing

CONFIGURATION

GENERAL DESCRIPTION

The DDR400 SDRAM is a high-speed CMOS, dy-

namic random-access memory that operates at a fre-
quency of 200 MHz (

CK=5ns) with a peak data transfer

rate of 400Mb/s. DDR400 continues to use the JEDEC
standard SSTL_2 interface and the 2n-prefetch archi-
tecture.

The standard DDR200/DDR266 data sheets also

pertain to the DDR400 device and should be refer-
enced for a complete description of DDR SDRAM func-
tionality and operating modes. However, to meet the
faster DDR400 operating frequencies, some of the AC
timing parameters, DC levels and operating tempera-
tures are slightly tighter. This addendum data sheet
will concentrate on the key differences required to sup-
port the enhanced speeds.
The Micron 128Mb data sheet provides full specifica-
tions and functionality unless specified herein.

128Mb: x8DDR400 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx8DDR400.p65 Rev. A (1/30/02-B)

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

66-PIN TSOP PACKAGE PIN ASSIGNMENT

66-PIN TSOP PACKAGE DIMENSION

SEE DETAIL A

0.10

0.65 TYP

0.71

10.16 ±0.08

0.15

0.50 ±0.10

PIN #1 ID

DETAIL A

22.22 ± 0.08

0.32 ± .075 TYP

+0.03

-0.02

+0.10

-0.05

1.20 MAX

0.10

0.25

11.76 ±0.10

0.80 TYP

0.10 (2X)

GAGE PLANE

(TOP VIEW)

NOTE:

1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm

per side.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

DQ7

DQ6

DQ5

DQ4

NC
NC
V

DQS

DNU

REF

DM
CK#
CK
CKE
NC
NC

A11
A9
A8
A7
A6
A5
A4

DQ0

DQ1

DQ2

DQ3

NC
NC

DNU

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

128Mb: x8DDR400 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx8DDR400.p65 Rev. A (1/30/02-B)

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

PIN DESCRIPTIONS

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

45, 46

CK, CK#

Input

Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.

CKE

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK#, and CKE) are disabled during
POWER-DOWN. Input buffers (excluding CKE) are disabled
during SELF REFRESH. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after V

is applied.

CS#

Input

Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.

23, 22, 21

RAS#, CAS#,

Input

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE#

command being entered.

Input

Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.

26, 27

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

29-32

A0, A1, A2

Input

Address Inputs: Provide the row address for ACTIVE commands, and

32, 35, 36

A3, A4, A5

the column address and auto precharge bit (A10) for READ/WRITE

36, 38, 39

A6, A7, A8

commands, to select one location out of the memory array in the

40, 29, 41

A9, A10, A11

respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.

2, 5, 8

DQ0-2

I/O

Data Input/Output.

11, 56, 59

DQ3-5

62, 65

DQ6-7

DQS

I/O

Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data.

(continued on next page)

128Mb: x8DDR400 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx8DDR400.p65 Rev. A (1/30/02-B)

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

PIN DESCRIPTIONS (continued)

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

4, 7, 10, 13, 14, 16, 17, 20,

No Connect: These pins should be left unconnected.

20, 25, 42, 43, 53, 54, 57,

60, 63

19, 50

DNU

Do Not Use: Must float to minimize noise on Vref

3, 9, 15, 55,

Supply

DQ Power Supply: +2.65V ±0.10V. Isolated on the die for

improved noise immunity.

6, 12, 52, 58, 64

Supply

DQ Ground. Isolated on the die for improved noise immunity.

1, 18, 33

Supply

Power Supply: +2.65V ±0.10V.

4, 48, 66

Supply

Ground.

REF

Supply

SSTL_2 reference voltage.

128Mb: x8DDR400 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx8DDR400.p65 Rev. A (1/30/02-B)

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

READ LATENCY

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first bit of output data. The latency
should be set to 3 clocks, as shown in the CAS Latency
Diagram and Mode Register Definition Diagram.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

CK#

COMMAND

DQS

CL = 3

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ

T2n

T3n

DON'T CARE

TRANSITIONING DATA

CAS Latency

Diagram

Mode Register Definition

Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

BA0 A11

BA1

* M13 and M12 (BA0 and BA1)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

M10

M11

128Mb: x8DDR400 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx8DDR400.p65 Rev. A (1/30/02-B)

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 15, 16; refer to DDR200/266 data sheet for all notes)
(0°C

+50°C; V

= +2.65V ±0.10V, V

Q = +2.65V ±0.10V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

Supply Voltage

2.55

2.75

36, 41

I/O Supply Voltage

2.55

2.75

36, 41,

I/O Reference Voltage

REF

0.49

x V

Q 0.51

x V

6, 44

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

7, 44

Input High (Logic 1) Voltage

(

)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(

)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT
Any input 0V

, V

REF

pin 0V

1.35V

-2

µA

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT

-5

µA

(DQs are disabled; 0V

OUT

OUTPUT LEVELS: Full drive option - x8
High Current (V

OUT

= V

Q-0.373V, minimum V

REF

, minimum V

)

-16.8

37, 39

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

16.8

AC INPUT OPERATING CONDITIONS

(Notes: 15, 16; refer to DDR200/266 data sheet for all notes)
(0°C

+50°C; V

= +2.65V ±0.10V, V

Q = +2.65V ±0.10V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.310

14, 28, 40

Input Low (Logic 0) Voltage

(

)

REF

- 0.310

14, 28, 40

I/O Reference Voltage

REF

(

)

0.49 x V

0.51 x V

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage Relative to V

....... -1V to +3.6V

Q Supply Voltage Relative to V

.... -1V to +3.6V

REF

and Inputs Voltage Relative to V

.. -1V to +3.6V

I/O Pins Voltage Relative to V

. -0.5V to V

Q +0.5V

Operating Temperature, T

(ambient) .. 0°C to +50°C

Storage Temperature (plastic) .......... -55°C to +150°C
Power Dissipation .................................................. 1W
Short Circuit Output Current ........................... 50mA

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

128Mb: x8DDR400 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx8DDR400.p65 Rev. A (1/30/02-B)

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

CAPACITANCE (TSOP)

(Notes: 1-5, 14-17, 33; refer to DDR200/266 data sheet for all notes)
(0°C

70°C; V

Q = +2.65V ±0.10V, V

= +2.65V ±0.10V)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Delta Input/Output Capacitance:

DQs, DQS, DM

0.50

p F

13, 24

DQ0-DQ7

0.50

p F

13, 24

Delta Input Capacitance: Command and Address

0.50

p F

13, 29

Delta Input Capacitance: CK, CK#

0.25

p F

13, 29

Input/Output Capacitance: DQs, DQS, DM

4.0

5.0

p F

Input Capacitance: Command and Address

2.0

3.0

p F

Input Capacitance: CK, CK#

2.0

3.0

p F

Input Capacitance: CKE

2.0

3.0

p F

128Mb: x8DDR400 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx8DDR400.p65 Rev. A (1/30/02-B)

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

AC CHARACTERISTICS

-5 (TSOP)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.6

+0.6

CK high-level width

0.45

0.55

CK low-level width

0.45

0.55

Clock cycle time

CL = 3

45,52

DQ and DM input hold time relative to DQS

0.45

26,31

DQ and DM input setup time relative to DQS

0.45

26,31

DQ and DM input pulse width (for each input)

DIPW

1.4

Access window of DQS from CK/CK#

DQSCK

-0.50

+0.50

DQS input high pulse width

DQSH

0.4

DQS input low pulse width

DQSL

0.4

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.35

25, 26

Write command to first DQS latching transition

DQSS

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.22

DQS falling edge from CK rising - hold time

DSH

0.22

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.60

18,42

Data-out low-impedance window from CK/CK#

-0.60

18,43

Address and control input hold time (fast slew rate)

0.75

Address and control input setup time (fast slew rate)

0.75

Address and control input hold time (slow slew rate)

Address and control input setup time (slow slew rate)

Address and control input pulse width

IPW

1.8

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

HP -

QHS

25, 26

Data Hold Skew Factor

QHS

0.50

ACTIVE to AUTOPRECHARGE command

RAP

ACTIVE to PRECHARGE command

RAS

70,000

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

DQS read postamble

RPST

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

20, 21

DQS write postamble

WPST

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

QH -

DQSQ

REFRESH to REFRESH command interval

REFC

140.6

µs

Average periodic refresh interval

REFI

15.6

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1-5, 14-17, 33; refer to DDR200/266 data sheet for all notes)
(0°C

50°C; V

Q = +2.65V ±0.10V, V

= +2.65V ±0.10V)

Document Outline

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Document Outline

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