Document Outline

Features
Options
128Mb (x32) DDR SDRAM Part Number
Pin Assignment
Key Timing Parameters
General Description
Table of Contents
Functional Block Diagram
Pin Descriptions
FBGA Ballout
Functional Description
Initialization
Register Definition
- Mode Register
- Burst Length
- Burst Type
- READ Latency
- Operating Mode
- Extended Mode Register
- Output Drive Strength
- DLL Enable/Disable
Figure 1 Mode Register Definition
Table 1 Burst Definition
Figure 2 CAS Latency
Table 2 CAS Latency
Figure 3 Extended Mode Register Definition
Commands
- Deselect
- No Operation (NOP)
- Load Mode Register
- Active
- Read
- Write
- Precharge
- Auto Precharge
- Burst Terminate
- Auto Refresh
- Self Refresh
Truth Table 1 - Commands
Truth Table 1A - DM Operation
Operations
- Bank/Row Activation
- Reads
- WRITEs
- PRECHARGE
- Power-Down (CKE Not Active)
Figure 4 Activating a Specific Row in a Specific Bank
Figure 5 Example
Figure 6 READ Command
Figure 7 READ Burst
Figure 8 Consecutive READ Bursts
Figure 9 Nonconsecutive READ Bursts
Figure 10 Random READ Accesses
Figure 11 Terminating a READ Burst
Figure 12 READ to WRITE
Figure 13 READ to PRECHARGE
Figure 14 WRITE Command
Figure 15 WRITE Burst
Figure 16 Consecutive WRITE to WRITE
Figure 17 Nonconsecutive WRITE to WRITE
Figure 18 Random WRITE Cycles
Figure 19 WRITE to READ - Uninterrupting
Figure 20 WRITE to READ - Interrupting
Figure 21 WRITE to READ - Odd Number of Data, Interrupting
Figure 22 WRITE to PRECHARGE - Uninterrupting
Figure 23 WRITE to PRECHARGE - Interrupting
Figure 24 WRITE to PRECHARGE - Odd Number of Data, Interrupting
Figure 25 PRECHARGE Command
Figure 26 Power-Down
Truth Table 2 - CKE
Truth Table 3 - Current State Bank n, Command to Bank n
Truth Table 4 - Current State Bank n, Command to Bank m
Absolute Maximum Ratings
DC Electrical Characteristics and Operating Conditions
AC Input Operation Conditions
Clock Input Operating Conditions
Figure 27 SSTL_2 Clock Input
DC Electrical Characteristics and Operating Conditions for 1.8V Option
AC Input Operating Conditions for 1.8V Option
Clock Input Operating Conditions for 1.8V Option
Capacitance
IDD Specifications and Conditions
Electrical Characteristics and Recommended AC Operating Conditions
Notes
Figure A Pull-Down Characteristics
Figure B Pull-Up Characteristics
Figure C Pull-Down
Figure D Pull-Up
Impedance Match Output Drive Characteristics
Reduced Output Drive Characteristics
Figure 28a Data Output Timing, TQFP Package
Figure 28b Data Output Timing, FBGA Package
Figure 29 Data Output Timing
Figure 31 Input Voltage Waveform
Initialize and Load Mode Registers
Power-Down Mode
Auto Refresh Mode
Self Refresh Mode
Bank Read - Without Auto Precharge
Bank Read - With Auto Precharge
Bank Write - Without Auto Precharge
Bank Write - With Auto Precharge
Write - DM Operation
100-Pin Plastic TQFP
144-Ball FBGA

128Mb: x32 DDR SDRAM

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.

DOUBLE DATA RATE
(DDR) SDRAM

MT46V4M32 - 1 Meg x 32 x 4 banks

For the latest data sheet revisions, please refer to the Micron
Web site:

www.micron.com/dramds

PIN ASSIGNMENT (TOP VIEW)

FEATURES

· V

= +2.5V ±0.125V, V

Q = +2.5V ±0.125V

· Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data
capture

· Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

· Reduced and matched output drive options
· Differential clock inputs (CK and CK#)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

· DLL to align DQ and DQS transitions with CK
· Four internal banks for concurrent operation
· Data mask (DM) for masking write data
· Programmable burst lengths: 2, 4, 8, or full page
· 32ms, 4,096-cycle auto refresh
· Auto precharge option
· Auto Refresh and Self Refresh Modes
· 2.5V I/O (SSTL_2 compatible)
· DQS per byte on the FBGA package
· 1.8V V

Q option for FBGA package

RAS lockout

OPTIONS MARKING

· Configuration

4 Meg x 32 (1 Meg x 32 x 4 banks)

4M32

· IO Voltage

2.5V V

None

1.8V V

· Plastic Packages

100-pin TQFP (0.65mm lead pitch)

12mm x 12mm FBGA

· Timing - Cycle Time

300 MHz @ CL = 5

-33

250 MHz @ CL = 4

-4

200 MHz @ CL = 3

-5

Note: 1. -4 and -33 speed grades are only available in the FBGA package

DQ2

DQ1

DQ0

DQS

NC \ RFU

DNU

DQ31

DQ30

DQ29

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

31 32 33 34 35 36

38 3940 41 42 43

45 4647 48 49 50

10099 98 97 96 95 94 93 9291 90 89 88 87 86 8584 83 82 81

DQ28
V

DQ27
DQ26
V

DQ25
DQ24
V

DQ15
DQ14
V

DQ13
DQ12
V

DQ11
DQ10
V

DQ9
DQ8
V

REF

DM3
DM1
CK
CK#
CKE
NC/MCL
A8/AP

A10

A11

DQ3

DQ4
DQ5

DQ6
DQ7

DQ16
DQ17

DQ18
DQ19

DQ20
DQ21

DQ22
DQ23

DM0
DM2

WE#

CAS#
RAS#

CS#

BA0
BA1

100-Pin TQFP

4 Meg x 32

Configuration

1 Meg x 32 x 4 banks

Refresh Count

Row Addressing

4K (A0-A11)

Bank Addressing

4 (BA0, BA1)

Column Addressing

256 (A0-A7)

128Mb (x32) DDR SDRAM PART NUMBER

PART NUMBER

ARCHITECTURE

MT46V4M32LG

4 Meg x 32

Part Number Example:

MT46V4M32V1FK-33

KEY TIMING PARAMETERS

SPEED

CLOCK RATE

DATA-OUT ACCESS

DQS-DQ

GRADE

CL = 5

CL = 4

CL = 3

WINDOW

SKEW

-33

300 MHz 250 MHz

0.685ns

±0.6ns +0.40ns

-4

250 MHz 200 MHz 0.950ns

±0.7ns +0.45ns

-5

200 MHz 1.400ns

±0.7ns +0.45ns

1. CL = CAS (Read) Latency
2. Minimum clock rate @ max CL

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

GENERAL DESCRIPTION

The 128Mb (x32) DDR SDRAM is a high-speed

CMOS, dynamic random-access memory containing
134,217,728- bits. It is internally configured as a quad-
bank DRAM.

The 128Mb DDR SDRAM uses a double data rate

architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 128Mb DDR SDRAM
effectively consists of a single 2n-bit wide, one-clock-
cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data
transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted ex-

ternally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.

The 128Mb DDR SDRAM operates from a differen-

tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.

Read and write accesses to the DDR SDRAM are

burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE com-
mand are used to select the bank and the starting col-
umn location for the burst access.

The DDR SDRAM provides for programmable READ

or WRITE burst lengths of 2, 4, 8, or full page locations.
An auto precharge function may be enabled to provide
a self-timed row precharge that is initiated at the end of
the burst access.

As with standard SDR SDRAMs, the pipelined,

multibank architecture of DDR SDRAMs allows for con-
current operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class I compatible.

NOTE: 1. The functionality and the timing specifications

discussed in this data sheet are for the DLL-enabled
mode of operation.

2. Throughout the data sheet, the various figures and

text refer to DQs as "DQ." The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise.

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

TABLE OF CONTENTS

Functional Block Diagram - 4 Meg x 32 .....................

Pin Descriptions ..........................................................

Functional Description ...............................................

Initialization ...........................................................

Mode Register ...................................................

Burst Length .................................................

Burst Type ....................................................

Read Latency ...............................................

Operating Mode ..........................................

Extended Mode Register ................................. 10

DLL Enable/Disable .................................. 10

Commands ................................................................... 11

Truth Table 1 (Commands)

............................................ 11

Truth Table 1A (DM Operation)

...................................... 11

Deselect ................................................................... 12
No Operation (NOP) .............................................. 12
Load Mode Register ............................................... 12
Active ....................................................................... 12
Read ....................................................................... 12
Write ....................................................................... 12
Precharge ................................................................ 12
Auto Precharge ....................................................... 12
Burst Terminate ..................................................... 12
Auto Refresh ........................................................... 13
Self Refresh ............................................................. 13

Operation ..................................................................... 14

Bank/Row Activation ............................................. 14
Reads ....................................................................... 15

Read Burst ......................................................... 16
Consecutive Read Bursts ................................ 17
Nonconsecutive Read Bursts ......................... 18
Random Read Accesses ................................... 19
Terminating a Read Burst ............................... 21
Read to Write ..................................................... 22
Read to Precharge ............................................ 23

Writes ....................................................................... 24

Write Burst ......................................................... 25
Consecutive Write to Write ............................... 26
Nonconsecutive Write to Write ........................ 27
Random Write Cycles ...................................... 28
Write to Read - Uninterrupting ...................... 29
Write to Read - Interrupting ........................... 30
Write to Read - Odd, Interrupting .................. 31

Write to Precharge - Uninterrupting ............. 32
Write to Precharge - Interrupting .................. 33
Write to Precharge - Odd, Interrupting ......... 34

Precharge ................................................................ 35
Power-Down ........................................................... 35

Truth Table 2 (CKE)

...................................................... 36

Truth Table 3 (Current State, Same Bank)

........................ 37

Truth Table 4 (Current State, Different Bank)

.................. 39

Operating Conditions
Absolute Maximum Ratings ....................................... 41
DC Electrical Characteristics and Operating

Conditions ............................................................... 41

AC Input Operating Conditions ................................ 41
Clock Input Operating Conditions ........................... 42
DC Electrical Characteristics and Operating

Conditions, 1.8V Option ....................................... 43

AC Input Operating Conditions, 1.8V Option ......... 43
Clock Input Operating Conditions, 1.8V Option .... 43
Capacitance .................................................................. 44
I

Specifications and Conditions ................................ 44

Electrical Characteristics and Recommended

AC Operating Conditions ..................................... 45

Notes ............................................................................. 46
Derating Data Valid Window ..................................... 47

Voltage and Timing Waveforms

Impedance Match Output .................................... 50
Reduced Output Drive Characteristics .............. 51
Output Timing -

DQSQ and

QH ......................... 52

Output Timing -

and

DQSCK ....................... 54

Input Timing .......................................................... 54
Input Voltage .......................................................... 55
Initialize and Load Mode Registers ..................... 56
Power-Down Mode ................................................ 57
Auto Refresh Mode ................................................ 58
Self Refresh Mode .................................................. 59
Reads

Bank Read - Without Auto Precharge ............ 60
Bank Read - With Auto Precharge .................. 61

Writes

Bank Write - Without Auto Precharge ........... 62
Bank Write - With Auto Precharge ................. 63
Write - DM Operation ...................................... 64

100-pin TQFP dimensions .......................................... 65
FBGA Package .............................................................. 66

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

PIN DESCRIPTIONS

TQFP PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

55, 54

CK, CK#

Input

Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and DQS) is
referenced to the crossings of CK and CK#.

CKE

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operations
(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank).
CKE is synchronous for POWER-DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for
disabling the outputs. CKE must be maintained HIGH throughout
read and write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWER-DOWN. Input buffers (excluding CKE) are
disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect
an LVCMOS LOW level after V

is applied.

CS#

Input

Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.

27, 26, 25

RAS#, CAS#, Input

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE#

command being entered.

23, 56, 24, 57

DM0-DM3

Input

Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.

29, 30

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

31-34, 47-51, 45, 36, 37

A0-A11

Input

Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A8) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A8 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A8 LOW,
bank selected by BA0, BA1) or all banks (A8 HIGH). The address
inputs also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode register
or extended mode register) is loaded during the LOAD MODE
REGISTER command.

97, 98, 100, 1, 3, 4, 6, 7

DQ0-7

I/O

Data Input/Output:

60, 61, 63, 64, 68, 69, 71, 72

DQ8-15

I/O

Data Input/Output:

9, 10, 12, 13, 17, 18, 20, 21 DQ16-23

I/O

Data Input/Output:

74, 75, 77, 78, 80, 81, 83, 84

DQ24-31

I/O

Data Input/Output:

DQS

I/O

Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data.

(continued on next page)

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

38, 39, 40, 41, 42, 43, 44

No Connect: These pins should be left unconnected.

87, 88, 90

DNU

Do Not Use: Must float to minimize noise.

NC/RFU

Reserved for Future Use

NC (MCL)

No Connect: Not internally connected. Must Connect LOW (for
compatibility with SGRAM devices).

2, 8, 14, 22, 59, 67, 73,

Supply

DQ Power Supply: +2.5V ±0.125V. Isolated on the die for

79, 86, 95

improved noise immunity. 1.8V option

5, 11, 19, 62, 70, 76,

Supply

DQ Ground. Isolated on the die for improved noise immunity.

82, 92, 99

15, 35, 65, 96

Supply

Power Supply: +2.5V ±0.125V.

16, 46, 66, 85

Supply

Ground.

REF

Supply

SSTL_2 reference voltage.

PIN DESCRIPTIONS (continued)

TQFP PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins

deemed to be of importance.

FBGA BALLOUT

DQS0

DM0

VSSQ

DQ21

DQ10

DQ15

DQ16

DQ26

DQ4

DQ3

DM2

DM1

DQS2

DQS1

DQ22

DQ8

DQ1

DQ6

DQ2

DQ0

CS#

DQ31

Q DQ30

DQ29

DSF/MCL

DQ24

DQ7

DQ28

VSSQ

DM3

DQS3

DQ27

DQ5

DQ25

A11

CK#

CKE

RFU

CAS#

DQ17

DQ14

RAS#

DQ19

DQ18 V

DQ20

DQ23

WE#

BA0

BA1

DQ13

DQ12

Q DQ11

DQ9

REF

A8/AP

RFU

A10

NOTE: 1. This package uses 4 DQS lines

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

FUNCTIONAL DESCRIPTION

The 128Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing
134,217,728 bits. The 128Mb DDR SDRAM is internally
configured as a quad-bank DRAM.

The 128Mb DDR SDRAM uses a double data rate

architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture, with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 128Mb DDR SDRAM
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two correspond-
ing n-bit wide, one-half-clock-cycle data transfers at
the I/O pins.

Read and write accesses to the DDR SDRAM are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.

Prior to normal operation, the DDR SDRAM must be

initialized. The following sections provide detailed in-
formation covering device initialization, register defi-
nition, command descriptions and device operation.

Initialization

DDR SDRAMs must be powered up and initialized

in a predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Power must first be applied to V

and V

Q simul-

taneously, and then to V

REF

(and to the system V

). V

must be applied after V

Q to avoid device latch-up,

which may cause permanent damage to the device.
V

REF

can be applied any time after V

Q but is expected

to be nominally coincident with V

. Except for CKE,

inputs are not recognized as valid until after V

REF

applied. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after V

is applied. Maintaining

an LVCMOS LOW level on CKE during power-up is re-
quired to ensure that the DQ and DQS outputs will be
in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.

Once the 200µs delay has been satisfied, a DESE-

LECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP com-
mand, a PRECHARGE ALL command should be ap-
plied. Next a LOAD MODE REGISTER command should
be issued for the extended mode register (BA1 LOW
and BA0 HIGH) to enable the DLL, followed by another
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL and to pro-
gram the operating parameters. Two-hundred clock
cycles are required between the DLL reset and any
READ command. A PRECHARGE ALL command should
then be applied, placing the device in the all banks idle
state.

Once in the idle state, two AUTO REFRESH cycles

must be performed (

RFC must be satisfied.) Addition-

ally, a LOAD MODE REGISTER command for the mode
register with the reset DLL bit deactivated (i.e., to pro-
gram operating parameters without resetting the DLL)
is recommended by JEDEC specification but is not re-
quired by the Micron device. Following these require-
ments, the DDR SDRAM is ready for normal operation
once a value has been written in to the DRAM and it has
been refreshed correctly. Read accesses to the DRAM
prior to it being written in to the DRAM must be assumed
to be unknown and unrepeatable.

MODE REGISTER

The mode register is used to define the specific mode

of operation of the DDR SDRAM. This definition in-
cludes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in Fig-
ure 1. The mode register is programmed via the MODE
REGISTER SET command (with BA0 = 0 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either
of these requirements will result in unspecified opera-
tion.

Mode register bits A0-A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-
leaved), A4-A6 specify the CAS latency, and A7-A11
specify the operating mode.

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

Figure 1

Mode Register Definition

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being programmable,
as shown in Figure 1. The burst length determines the
maximum number of column locations that can be ac-
cessed for a given READ or WRITE command. Burst
lengths of 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types. Full page burst
is supported in sequential mode only.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst Length

CAS Latency BT

0* 0*

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

Operating Mode

A10

A11

BA1

BA0

* M13 and M12 (BA0 and BA1)

must be 0, 0 to select the

base mode register (vs. the

extended mode register).

M10

M11

Order of Accesses Within a Burst

Burst

Starting Column

Length

Address

Type = Sequential Type = Interleaved

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

n = A0 - A7,

Cn, Cn+1, Cn+2

Page

A0 = 0

Cn+3, Cn+4...

Not supported

(256)

...Cn-1,

Cn...

n = A0 - A7,

Cn, Cn-1, Cn-2

A0 = 1

Cn-3, Cn-4...

Not supported

...Cn+1,

Cn...

Table 1

Burst Definition

NOTE:

1. For a burst length of two, A1-A7 select the block

of two burst; A0 selects the starting column
within the block.

2. For a burst length of four, A2-A7 select the block

of four burst; A0-A1 select the starting column
within the block.

3. For a burst length of eight, A3-A7 select the

block of eight burst; A0-A2 select the starting
column within the block.

4. For a full-page burst, the full row is selected and

A0-A7 select the starting column. A0 also selects
the direction of the burst (incrementing if A0 = 0,
decrementing if A0 = 1).

5. Whenever a boundary of the block is reached

within a given sequence above, the following
access wraps within the block.

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

lected by A1-Ai when the burst length is set to two, by
A2-Ai when the burst length is set to four and by A3-Ai
when the burst length is set to eight (where Ai is the
most significant column address bit for a given con-
figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.

Figure 2

CAS Latency

Read Latency

The READ latency is the delay, in clock cycles, be-

tween the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, 3, 4 or 5 clocks, as shown in Figure 2.

If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available nominally
coincident with clock edge n + m. Table 2 indicates the
operating frequencies at which each CAS latency setting
can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7-A11 each
set to zero, and bits A0-A6 set to the desired values. A
DLL reset is initiated by issuing a MODE REGISTER

CK#

COMMAND

DQS

CL = 2

READ

NOP

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ

CK#

COMMAND

DQS

CL = 3

T2n

T3n

DON'T CARE

TRANSITIONING DATA

Table 2

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

SPEED

CL = 5

CL = 4

CL = 3

-33

300

250

-4

250

200

-5

200

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128Mb: x32

DDR SDRAM

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Figure 3

Extended Mode Register Definition

SET command with bits A7 and A9-A11 each set to zero,
bit A8 set to one, and bits A0-A6 set to the desired
values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD MODE
REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGIS-
TER command to select normal operating mode.

All other combinations of values for A7-A11 are re-

served for future use and/or test modes. Test modes
and reserved states should not be used because un-
known operation or incompatibility with future ver-
sions may result.

EXTENDED MODE REGISTER

The extended mode register controls functions be-

yond those controlled by the mode register; these ad-
ditional functions are DLL enable/disable. These func-
tions are controlled via the bits shown in Figure 3. The
extended mode register is programmed via the LOAD
MODE REGISTER command to the mode register (with
BA0 = 1 and BA1 = 0) and will retain the stored informa-
tion until it is programmed again or the device loses
power. Although not required by the Micron device,
the enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiat-
ing any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Although not required by Micron, JEDEC recommends
a LOAD MODE REGISTER command be issued to the
mode register (BA0/BA1 both LOW) to reset the DLL.

Output Drive Strength

The reduced drive strength for all outputs are specified

to be SSTL2, Class I. The x32 supports both reduced and
matched impedance drive strengths. This option is in-
tended for the support of the lighter load and/or point-to-
point environments. The selection of the reduced drive
strength will alter the DQs and DQSs from SSTL2, Class
I drive strength to a reduced drive strength, which is
approximately 54 percent of the SSTL2, Class II drive
strength.

DLL

Enable

Disable

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Drive Strength

Reserved

Half

Reserved

Matched

A10

A11

BA0 BA1

NOTE: 1. E13 and E12 (BA0 and BA1) must be 1, 0 to select the
Extended Mode Register (vs. the base Mode Register).

2. Reserved for future use. Set values to 0.

RFU

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued. The DLL must be reset any time the
clock frequency is changed followed by 200 clock cycles.

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128Mb: x32

DDR SDRAM

ADVANCE

appear following the Operation section; these tables
provide current state/next state information.

Commands

Truth Table 1 provides a quick reference of avail-

able commands. This is followed by a verbal descrip-
tion of each command. Two additional Truth Tables

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;

BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the op-
code to be written to the selected mode register.

3. BA0-BA1 provide bank address and A0-A11provide row address.
4. BA0-BA1 provide bank address; A0-A7provide column address; A8 HIGH enables the auto precharge feature (nonpersis-

tent), and A8 LOW disables the auto precharge feature.

5. A8 LOW: BA0-BA1 determine which bank is precharged.

A8 HIGH: all banks are precharged and BA0-BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

TRUTH TABLE 1 COMMANDS

(Note: 1)

NAME (FUNCTION)

CS# RAS# CAS# WE#

ADDR

NOTES

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

Bank/Col

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH

6, 7

(Enter self refresh mode)

LOAD MODE REGISTER

Op-Code

TRUTH TABLE 1A DM OPERATION

NAME (FUNCTION)

D M

DQs

NOTES

Write Enable

Valid

Write Inhibit

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DDR SDRAM

ADVANCE

DESELECT

The DESELECT function (CS# HIGH) prevents new

commands from being executed by the DDR SDRAM.
The DDR SDRAM is effectively deselected. Operations
already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

instruct the selected DDR SDRAM to perform a NOP
(CS# LOW). This prevents unwanted commands from
being registered during idle or wait states. Operations
already in progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via inputs A0-A11.

See mode register descriptions in the Register Defini-
tion section. The LOAD MODE REGISTER command
can only be issued when all banks are idle, and a sub-
sequent executable command cannot be issued until

MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before open-
ing a different row in the same bank.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A7 selects the starting column location. The
value on input A8 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses.

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A7 selects the starting column location. The
value on input A8 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
WRITE burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Input data
appearing on the DQs is written to the memory array

subject to the DM input logic level appearing coinci-
dent with the data. If a given DM signal is registered
LOW, the corresponding data will be written to memory;
if the DM signal is registered HIGH, the corresponding
data inputs will be ignored, and a WRITE will not be
executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate

the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (

RP) after the PRECHARGE

command is issued. Input A8 determines whether one
or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1
select the bank. Otherwise BA0, BA1 are treated as
"Don't Care." Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. A
PRECHARGE command will be treated as a NOP if there
is no open row in that bank (idle state), or if the previ-
ously open row is already in the process of precharging.

AUTO PRECHARGE

Auto precharge is a feature which performs the same

individual-bank precharge function described above,
but without requiring an explicit command. This is ac-
complished by using A8 to enable auto precharge in
conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst. Auto
precharge is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE com-
mand.

Auto precharge ensures that the precharge is initi-

ated at the earliest valid stage within a burst. This "ear-
liest valid stage" is determined as if an explicit
PRECHARGE command was issued at the earliest pos-
sible time, without violating

RAS

min

, as described for

each burst type in the Operation section of this data
sheet. The user must not issue another command to
the same bank until the precharge time (

RP) is com-

pleted.

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate READ bursts (with auto precharge disabled). The
most recently registered READ command prior to the
BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet.

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DDR SDRAM

ADVANCE

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the DDR SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) REFRESH in FPM/EDO DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required.

The addressing is generated by the internal refresh

controller. This makes the address bits a "Don't Care"
during an AUTO REFRESH command. The 128 Mb x32
DDR SDRAM requires AUTO REFRESH cycles at an
average interval of 7.8µs (maximum).

To allow for improved efficiency in scheduling and

switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any given
DDR SDRAM, meaning that the maximum absolute
interval between any AUTO REFRESH command and
the next AUTO REFRESH command is 18 × 7.8µs
(140.4µs). This maximum absolute interval is to allow
future support for DLL updates internal to the DDR
SDRAM to be restricted to AUTO REFRESH cycles,
without allowing excessive drift in

AC between updates.

This is a JEDEC requirement that is NOT required for
Micron's 128Mb x32 DDR device.

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). The
DLL is automatically disabled upon entering SELF RE-
FRESH and is automatically enabled upon exiting SELF
REFRESH (200 clock cycles must then occur before a
READ command can be issued). Input signals except
CKE are "Don't Care" during SELF REFRESH.

The procedure for exiting self refresh requires a se-

quence of commands. First, CK must be stable prior to
CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for

XSNR

because time is required for the completion of any in-
ternal refresh in progress. A simple algorithm for meet-
ing both refresh and DLL requirements is to apply
NOPs for 200 clock cycles before applying any other
command.

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128Mb: x32

DDR SDRAM

ADVANCE

Operations

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be is-

sued to a bank within the DDR SDRAM, a row in that
bank must be "opened." This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 4.

After a row is opened with an ACTIVE command, a

READ or WRITE command may be issued to that row,
subject to the

RCD specification.

RCD (MIN) should

be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a

RCD specifi-

cation of 15ns with a 166 MHz clock (6ns period) results
in 2.5 clocks rounded to 3. This is reflected in Figure 5,
which covers any case where 2 <

RCD (MIN)/

(Figure 5 also shows the same case for

RCD; the same

procedure is used to convert other specification limits
from time units to clock cycles).

A subsequent ACTIVE command to a different row

in the same bank can only be issued after the previous
active row has been "closed" (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by

RC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by

RRD.

Figure 5

Example: Meeting

RCD (

RRD) MIN When 2 <

RCD (

RRD) MIN/

Figure 4

Activating a Specific Row in

a Specific Bank

CS#

WE#

CAS#

RAS#

CKE

A0-A11

RA = Row Address
BA = Bank Address

HIGH

BA0,1

CK#

COMMAND

BA0, BA1

ACT

NOP

tRRD

tRCD

CK#

Bank x

Bank y

A0-A11

Row

NOP

RD/WR

NOP

Bank y

Col

NOP

DON T CARE

NOP

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128Mb: x32

DDR SDRAM

ADVANCE

READs

READ bursts are initiated with a READ command,

as shown in Figure 6.

The starting column and bank addresses are pro-

vided with the READ command and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid nominally
at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#). Figure 7 shows general
timing for each possible CAS latency setting. DQS is
driven by the DDR SDRAM along with output data.
The initial LOW state on DQS is known as the read
preamble; the LOW state coincident with the last data-
out element is known as the read postamble.

Upon completion of a burst, assuming no other com-

mands have been initiated, the DQs will go
High-Z. A detailed explanation of

DQSQ (valid data-

out skew),

QH (data-out window hold), the valid data

window are depicted in Figure 27. A detailed explana-
tion of

DQSCK (DQS transition skew to CK) and

(data-out transition skew to CK) is depicted in Figure
28.

Data from any READ burst may be concatenated

with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data can
be maintained. The first data element from the new
burst follows either the last element of a completed
burst or the last desired data element of a longer burst
which is being truncated. The new READ command
should be issued x cycles after the first READ com-
mand, where x equals the number of desired data ele-
ment pairs (pairs are required by the 2n-prefetch ar-
chitecture). This is shown in Figure 8. A READ com-
mand can be initiated on any clock cycle following a
previous READ command. Nonconsecutive read data
is shown for illustration in Figure 9. Full-speed random
read accesses within a page (or pages) can be performed
as shown in Figure 10.

Figure 6

READ Command

CS#

WE#

CAS#

RAS#

CKE

A0-A7

BA0,1

HIGH

EN AP

DIS AP

A9, A10, A11

CK#

CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge

DON T CARE

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128Mb: x32

DDR SDRAM

ADVANCE

Data from any READ burst may be truncated with a

BURST TERMINATE command, as shown in Figure 11.
The BURST TERMINATE latency is equal to the READ
(CAS) latency, i.e., the BURST TERMINATE command
should be issued x cycles after the READ command,
where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architec-
ture).

Data from any READ burst must be completed or

truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TER-
MINATE command must be used, as shown in Figure
12. The

DQSS (MIN) case is shown; the

DQSS (MAX)

case has a longer bus idle time. (

DQSS [MIN] and

DQSS [MAX] are defined in the section on WRITEs.)

A READ burst may be followed by, or truncated with,

a PRECHARGE command to the same bank provided
that auto precharge was not activated. The
PRECHARGE command should be issued x cycles after
the READ command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture). This is shown in Figure 13.
Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until

is met. Note that part of the row precharge time is hid-
den during the access of the last data elements.

READs (continued)

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ADVANCE

WRITEs

WRITE bursts are initiated with a WRITE command,

as shown in Figure 14.

The starting column and bank addresses are pro-

vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.

During WRITE bursts, the first valid data-in ele-

ment will be registered on the first rising edge of DQS
following the WRITE command, and subsequent data
elements will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command
and the first rising edge is known as the write preamble;
the LOW state on DQS following the last data-in ele-
ment is known as the write postamble.

The time between the WRITE command and the

first corresponding rising edge of DQS (

DQSS) is speci-

fied with a relatively wide range (from 75 percent to 125
percent of one clock cycle). All of the WRITE diagrams
show the nominal case, and where the two extreme
cases (i.e.,

DQSS [MIN] and

DQSS

[MAX]) might not be

intuitive, they have also been included. Figure 15 shows
the nominal case and the extremes of

DQSS for a burst

of 4. Upon completion of a burst, assuming no other
commands have been initiated, the DQs will remain
High-Z and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with

or truncated with a subsequent WRITE command. In
either case, a continuous flow of input data can be main-
tained. The new WRITE command can be issued on any
positive edge of clock following the previous WRITE com-
mand. The first data element from the new burst is ap-
plied after either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated. The new WRITE command should
be issued x cycles after the first WRITE command, where
x equals the number of desired data element pairs (pairs
are required by the 2n-prefetch architecture).

Figure 16 shows concatenated bursts of 4. An ex-

ample of nonconsecutive WRITEs is shown in Figure
17. Full-speed random write accesses within a page or
pages can be performed as shown in Figure 18.

Data for any WRITE burst may be followed by a

subsequent READ command. To follow a WRITE with-
out truncating the WRITE burst,

WTR should be met

as shown in Figure 19.

Data for any WRITE burst may be truncated by a

subsequent READ command, as shown in Figure 20.
Note that only the data-in pairs that are registered
prior to the

WTR period are written to the internal ar-

ray, and any subsequent data-in should be masked
with DM as shown in Figure 21.

Figure 14

WRITE Command

Data for any WRITE burst may be followed by a

subsequent PRECHARGE command. To follow a WRITE
without truncating the WRITE burst,

WR should be

met as shown in Figure 22.

Data for any WRITE burst may be truncated by a

subsequent PRECHARGE command, as shown in Fig-
ures 23 and 24. Note that only the data-in pairs that are
registered prior to the

WR period are written to the

internal array, and any subsequent data-in should be
masked with DM as shown in Figures 23 and 24. After
the PRECHARGE command, a subsequent command
to the same bank cannot be issued until

RP is met.

CS#

WE#

CAS#

RAS#

CKE

BA0,1

HIGH

EN AP

DIS AP

CK#

CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge

DON T CARE

A0-A7

A9, A10, A11

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128Mb: x32

DDR SDRAM

ADVANCE

Figure 23

WRITE to Precharge Interrupting

DQSS

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

PRE

NOP

ADDRESS

Bank a,

Col b

Bank,

(a or all)

NOP

T2n

NOTE: 1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 4 is shown; two data elements are written.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
7. DQS is required at T2 and T2n (nominal case) to register DM.
8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE

command would mask the last two data elements.

9. PRE = PRECHARGE command.

T1n

DQS

DQSS

DQSS (MIN)

DQS

DQSS

DQSS (MAX)

DQS

DON T CARE

TRANSITIONING DATA

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DDR SDRAM

ADVANCE

Figure 24

WRITE to PRECHARGE Odd Number of Data, Interrupting

DQSS

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

PRE

NOP

ADDRESS

Bank a,

Col b

Bank,

(a or all)

NOP

T2n

NOTE: 1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 4 is shown; one data elements are written.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
7. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE

command would mask the last two data elements.

9. PRE = PRECHARGE command.

T1n

DQS

DQSS

DQSS (MIN)

DQS

DQSS

DQSS (MAX)

DQS

DON T CARE

TRANSITIONING DATA

128Mb: x32 DDR SDRAM

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

Figure 25

PRECHARGE Command

PRECHARGE

The PRECHARGE command (Figure 25) is used to

deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (

RP) af-

ter the PRECHARGE command is issued. Input A8 de-
termines whether one or all banks are to be precharged,

CS#

WE#

CAS#

RAS#

CKE

BA0,1

HIGH

ALL BANKS

ONE BANK

A0-A7, A9-A11

CK#

BA = Bank Address (if A8 is LOW;
otherwise Don t Care )

No READ/WRITE
access in progress

Exit power-down mode

Enter power-down mode

CKE

CK#

COMMAND

NOP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

NOP

VALID

Ta0

Ta1

Ta2

VALID

DON'T CARE

and in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as "Don't
Care." Once a bank has been precharged, it is in the
idle state and must be activated prior to any READ or
WRITE commands being issued to that bank.

POWER-DOWN (CKE NOT ACTIVE)

Unlike SDR SDRAMs, DDR SDRAMs require CKE to

be active at all times an access is in progress: from the
issuing of a READ or WRITE command until comple-
tion of the burst. For READs, a burst completion is de-
fined when the Read Postamble is satisfied; For
WRITEs, a burst completion is defined when the Write
Postamble is satisfied.

Power-down (Figure 26) is entered when CKE is reg-

istered LOW. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in any
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and out-
put buffers, excluding CK, CK# and CKE. For maximum
power savings, the user has the option of disabling the
DLL prior to entering power-down. In that case, the
DLL must be enabled after exiting power-down, and
200 clock cycles (approximately 2µs) must occur before
a READ command can be issued. However, power-
down duration is limited by the refresh requirements
of the device, so in most applications, the self-refresh
mode is preferred over the DLL-disabled power-down
mode.

While in power-down, CKE LOW and a stable clock

signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are "Don't Care."

The power-down state is synchronously exited

when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable com-
mand may be applied one clock cycle later.

Figure 26

Power-Down

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

TRUTH TABLE 2 CKE

(Notes: 1-4)

CKE

n-1

CKE

CURRENT STATE

COMMAND

ACTION

NOTES

Power-Down

Maintain Power-Down

Self Refresh

Maintain Self Refresh

Power-Down

DESELECT or NOP

Exit Power-Down

Self Refresh

DESELECT or NOP

Exit Self Refresh

All Banks Idle

DESELECT or NOP

Precharge Power-Down Entry

Bank(s) Active

DESELECT or NOP

Active Power-Down Entry

All Banks Idle

AUTO REFRESH

Self Refresh Entry

See Truth Table 3

NOTE: 1. CKE

is the logic state of CKE at clock edge n; CKE

n-1

was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND

is the command registered at clock edge n, and ACTION

is a result of COMMAND

4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the

XSR period. A minimum of 200

clock cycles is needed before applying a READ command for the DLL to lock.

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

TRUTH TABLE 3 CURRENT STATE BANK n COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE#

COMMAND/ACTION

NOTES

Any

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

ACTIVE (select and activate row)

Idle

AUTO REFRESH

LOAD MODE REGISTER

READ (select column and start READ burst)

Row Active

WRITE (select column and start WRITE burst)

PRECHARGE (deactivate row in bank or banks)

Read

READ (select column and start new READ burst)

(Auto-

WRITE (select column and start WRITE burst)

10, 12

Precharge

PRECHARGE (truncate READ burst, start PRECHARGE)

Disabled)

BURST TERMINATE

Write

READ (select column and start READ burst)

10, 11

(Auto-

WRITE (select column and start new WRITE burst)

Precharge

PRECHARGE (truncate WRITE burst, start PRECHARGE)

8, 11

Disabled)

NOTE:

1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Truth Table 2) and after

XSNR has been met (if the previous

state was self refresh).

2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those

allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses

and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands,

or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when

RP is met. Once

RP is

met, the bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when

RCD is met.

Once

RCD is met, the bank will be in the "row active" state.

Read w/Auto-

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends

when

RP has been met. Once

RP is met, the bank will be in the idle state.

Write w/Auto-

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends

when

RP has been met. Once

RP is met, the bank will be in the idle state.

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

NOTE (continued):

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be

applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

RC is met.

Once

RC is met, the DDR SDRAM will be in the all banks idle state.

Accessing Mode

MRD

has been met. Once

MRD is met, the DDR SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when

RP is met.

Once

RP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.

10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or

WRITEs with auto precharge disabled.

11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to

end the READ burst prior to asserting a WRITE command.

128Mb: x32 DDR SDRAM

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

TRUTH TABLE 4 CURRENT STATE BANK n COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE#

COMMAND/ACTION

NOTES

Any

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

Idle

Any Command Otherwise Allowed to Bank m

Row

ACTIVE (select and activate row)

Activating,

READ (select column and start READ burst)

Active, or

WRITE (select column and start WRITE burst)

Precharging

PRECHARGE

Read

ACTIVE (select and activate row)

(Auto-

READ (select column and start new READ burst)

Precharge

WRITE (select column and start WRITE burst)

7, 9

Disabled)

PRECHARGE

Write

ACTIVE (select and activate row)

(Auto-

READ (select column and start READ burst)

7, 8

Precharge

WRITE (select column and start new WRITE burst)

Disabled)

PRECHARGE

Read

ACTIVE (select and activate row)

(With Auto-

READ (select column and start new READ burst)

Precharge)

WRITE (select column and start WRITE burst)

7, 9

PRECHARGE

Write

ACTIVE (select and activate row)

(With Auto-

READ (select column and start READ burst)

Precharge)

WRITE (select column and start new WRITE burst)

PRECHARGE

NOTE:

1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Truth Table 2) and after

XSNR has been

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and

the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state
that the given command is allowable). Exceptions are covered in the notes below.

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

NOTE (continued):

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses

and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Read with Auto

Precharge Enabled: See following text

Write with Auto

Precharge Enabled: See following text

3a. The read with auto precharge enabled or WRITE with auto precharge enabled states can each be broken

into two parts: the access period and the precharge period. For read with auto precharge, the precharge
period is defined as if the same burst was executed with auto precharge disabled and then followed with
the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with
auto precharge, the precharge period begins when tWR ends,with tWR measured as if auto precharge
was disabled. The access period starts with registration of the command and ends where the precharge
period (or tRP) begins.

This device supports concurrent auto precharge such that when a read with auto precharge is enabled

or a write with auto precharge is enabled any command to other banks is allowed, as long as that
command does not interrupt the read or write data transfer already in process. In either case, all other
related limitations apply (e.g., contention between read data and write data must be avoided).

3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a com-

mand to a different bank is summarized below.

From Command

To Command

Minimum delay (with concurrent auto precharge)

WRITE w/AP

READ or READ w/AP

[1 + (BL/2)]

CK +

WTR

WRITE or WRITE w/AP

(BL/2) tCK

PRECHARGE

ACTIVE

READ w/AP

READ or READ w/AP

(BL/2) *

WRITE or WRITE w/AP

[CL

+ (BL/2)]

PRECHARGE

ACTIVE

= CAS Latency (CL) rounded up to the next integer

BL = Bust Length

4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by

the current state only.

6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge

enabled and READs or WRITEs with auto precharge disabled.

8. Requires appropriate DM masking.

9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMI-

NATE must be used to end the READ burst prior to asserting a WRITE command.

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

Supply

Relative to V

............................................ -1V to +3.6V

Voltage on V

Q Supply

Relative to V

............................................ -1V to +3.6V

Voltage on V

REF

and Inputs

Relative to V

............................................ -1V to +3.6V

Voltage on I/O Pins

Relative to V

............................... -0.5V to V

Q +0.5V

Operating Temperature, T

(ambient) ... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ........................................................ 2W
Short Circuit Output Current ................................. 50mA

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

AC INPUT OPERATING CONDITIONS

(Notes: 1-5, 14, 16, 40; notes appear on pages 46-49) (0°C

+70°C; V

= +2.5V ±0.125V, V

Q = +2.5V ±0.125V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage; DQ

(

)

REF

+ 0.310

14, 28, 39

Input Low (Logic 0) Voltage; DQ

(

)

REF

- 0.310

14, 28, 39

Clock Input Differential Voltage; CK and CK#

(

)

0.7

Q + 0.6

Clock Input Crossing Point Voltage; CK and CK#

(

)

0.5xV

Q-0.2

0.5xV

Q+0.2

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1-5, 16, 40; notes appear on pages 46-49) (0°C

+70°C; V

= +2.5V ±0.125V, V

Q = +2.5V ±0.125V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

Supply Voltage

2.375

2.625

I/O Supply Voltage

2.375

2.625

I/O Reference Voltage

REF

0.49

x V

0.51

x V

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

Input High (Logic 1) Voltage

(

)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(

)

-0.3

REF

- 0.15

Clock Input Voltage Level; CK and CK#

-0.3

Q + 0.3

Clock Input Differential Voltage; CK and CK#

0.36

Q + 0.6

Clock Input Crossing Point Voltage; CK and CK#

1.15

1.35

INPUT LEAKAGE CURRENT
Any input 0V

-2

µA

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT

-5

µA

(DQs are disabled; 0V

OUT

OUTPUT LEVELS: Impedance Match
High Current (V

OUT

= V

Q-0.373V, minimum V

REF

, minimum V

)

-4

37, 39

Low Current (V

OUT

= 0.373V, maximum V

REF

,maximum V

)

OUTPUT LEVELS: Reduced drive option -
High Current (V

OUT

= V

Q-0.763V, minimum V

REF

, minimum V

)

OHR

-9

38, 39

Low Current (V

OUT

= 0.763V, maximum V

REF

,maximum V

)

OLR

128Mb: x32 DDR SDRAM

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

CK#

2.80V

Maximum Clock Level

Minimum Clock Level

- 0.30V

1.25V

1.45V

1.05V

(AC)

(DC)

(AC)

NOTE: 1. This provides a minimum of 1.15V to a maximum of 1.35V, and is always half of V

2. CK and CK# must cross in this region.
3. CK and CK# must meet at least V

(DC) min when static and is centered around V

(DC)

4. CK and CK# must have a minimum 700mv peak to peak swing.
5. CK or CK# may not be more positive than V

Q + 0.3V or more negative than Vss - 0.3V.

6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values.

CLOCK INPUT OPERATING CONDITIONS

(Notes: 15, 15, 16, 30; notes appear on pages 4649) (0°C

+ 70°C; V

= +2.5V ±0.125V, V

Q = +2.5V ±0.125V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Clock Input Mid-Point Voltage; CK and CK#

(

)

1.15

1.35

6, 9

Clock Input Voltage Level; CK and CK#

(

)

-0.3

Q + 0.3

Clock Input Differential Voltage; CK and CK#

(

)

0.36

Q + 0.6

6, 8

Clock Input Differential Voltage; CK and CK#

(

)

0.7

Q + 0.6

Clock Input Crossing Point Voltage; CK and CK#

(

)

0.5 x V

Q - 0.2

0.5 x V

Q + 0.2

Figure 27

SSTL_2 Clock Input

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

AC INPUT OPERATING CONDITIONS FOR 1.8V OPTION

(Notes: 1-5, 14, 16, 40; notes appear on pages 46-49) (0°C

+70°C; V

= +2.5V ±0.125V, V

Q = +1.8V ±0.125V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage; DQ

(

)

REF

+ 0.310

14, 28, 39

Input Low (Logic 0) Voltage; DQ

(

)

REF

- 0.310

14, 28, 39

Clock Input Differential Voltage; CK and CK#

(

)

0.7

Q + 0.6

Clock Input Crossing Point Voltage; CK and CK#

(

)

0.5xV

Q-0.2

0.5xV

Q+0.2

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS FOR 1.8V OPTION

(Notes: 1-5, 16, 40; notes appear on pages 46-49) (0°C

+70°C; V

= +2.5V ±0.125V, V

Q = +1.8V ±0.125V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

Supply Voltage

2.375

2.625

I/O Supply Voltage

1.67

1.925

I/O Reference Voltage

REF

0.49

x V

0.51

x V

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

Input High (Logic 1) Voltage

(

)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(

)

-0.3

REF

- 0.15

Clock Input Voltage Level; CK and CK#

-0.3

Q + 0.3

Clock Input Differential Voltage; CK and CK#

0.36

Q + 0.6

Clock Input Crossing Point Voltage; CK and CK#

0.8

1.0

INPUT LEAKAGE CURRENT
Any input 0V

-2

µA

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT

-5

µA

(DQs are disabled; 0V

OUT

OUTPUT LEVELS: Impedance Match
High Current (V

OUT

= V

Q-0.373V, minimum V

REF

, minimum V

)

-4

37, 39

Low Current (V

OUT

= 0.373V, maximum V

REF

,maximum V

)

OUTPUT LEVELS: Reduced drive option -
High Current (V

OUT

= V

Q-0.763V, minimum V

REF

, minimum V

)

OHR

-9

38, 39

Low Current (V

OUT

= 0.763V, maximum V

REF

,maximum V

)

OLR

CLOCK INPUT OPERATING CONDITIONS FOR 1.8V OPTION

(Notes: 15, 15, 16, 30; notes appear on pages 4649) (0°C

+ 70°C; V

= +2.5V ±0.125V, V

Q = +1.8V ±0.125V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Clock Input Mid-Point Voltage; CK and CK#

(

)

0.8

1.0

6, 9

Clock Input Voltage Level; CK and CK#

(

)

-0.3

Q + 0.3

Clock Input Differential Voltage; CK and CK#

(

)

0.36

Q + 0.6

6, 8

Clock Input Differential Voltage; CK and CK#

(

)

0.7

Q + 0.6

Clock Input Crossing Point Voltage; CK and CK#

(

)

0.5 x V

Q - 0.2

0.5 x V

Q + 0.2

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

SPECIFICATIONS AND CONDITIONS

(Notes: 1-5, 10, 12, 14, 40; notes on pages 46-49) (0°C

+70°C; V

Q = +2.5V ±0.125V, V

= +2.5V ±0.125V)

PARAMETER/CONDITION

SYMBOL

-33

- 4

- 5

UNITS NOTES

OPERATING CURRENT: One bank; Active-Precharge;

RC =

RC (MIN);

TBD

CK =

CK (MIN); DQ, DM, and DQS inputs changing twice

per clock cyle; Address and control inputs changing once
per clock cycle;

OPERATING CURRENT: One bank; Active-Read-Precharge;

TBD

Burst = 2;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA;

Address and control inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;

TBD

Power-down mode;

CK =

CK MIN; CKE = LOW;

IDLE STANDBY CURRENT: CS# = HIGH; All banks idle;

TBD

CK =

CK (MIN); CKE = HIGH; Address and other control inputs

changing once per clock cycle

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;

TBD

Power-down mode;

CK =

CK (MIN); CKE = LOW

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;

TBD

One bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN);

DQ, DM and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;

TBD

One bank active; Address and control inputs changing once per
clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;

TBD

One bank active; Address and control inputs changing once per
clock cycle;

CK =

CK(MIN); DQ, DM and DQS inputs

changing twice per clock cycle

AUTO REFRESH CURRENT

RFC =

RFC (MIN)

TBD

RFC =

7.8µs

TBD

SELF REFRESH CURRENT: CKE

0.2V

Standard

TBD

MAX

CAPACITANCE

(Note: 13)

TQFP Package

FBGA Package

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Delta Input/Output Capacitance: DQs, DQS, DM

0.50

p F

Delta Input Capacitance: Command and Address

0.50

p F

Delta Input Capacitance: CK, CK#

0.25

0.50

p F

Input/Output Capacitance: DQs, DQS, DM

4.0

5.0

3.0

5.0

p F

Input Capacitance: Command and Address

2.0

3.0

2.0

3.0

p F

Input Capacitance: CK, CK#

2.0

3.0

2.0

3.0

p F

Input Capacitance: CKE

2.0

3.0

2.0

3.0

p F

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1-5,14-17,33,40; notes on pages 46-49) (0°C

+70°C; V

Q = +2.5V ±0.125V, V

= +2.5V ±0.125V)

AC CHARACTERISTICS

-33

-4

-5

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.6

+0.6

-0.7

+0.7

-0.7

+0.7

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL = 5

CK(5)

3.3

CL = 4

CK(4)

CL = 3

CK(3)

CL = 2

CK(2)

Auto precharge write recovery plus precharge time

DAL

DQ and DM input hold time relative to DQS

0.45

26, 31

DQ and DM input setup time relative to DQS

0.45

26, 31

DQ and DM input pulse width (for each input)

DIPW

1.25

Access window of DQS from CK/CK#

DQSCK

-0.6

+0.6

-0.7

+0.7

-0.7

+0.7

DQS input high pulse width

DQSH

0.4

DQS input low pulse width

DQSL

0.4

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.4

0.45

25, 26

Write command to first DQS latching transition

DQSS

0.8

1.2

0.8

1.2

0.8

1.2

DQS falling edge to CK rising - setup time

DSS

0.25

DQS falling edge from CK rising - hold time

DSH

0.25

Half clock period

CH,

Data-out high-impedance window from CK/CK#

-0.5

Data-out low-impedance window from CK/CK#

-0.5

Address and control input hold time

0.9

Address and control input setup time

0.9

Address and control input pulse width

IPW

LOAD MODE REGISTER command cycle time

MRD

Power-Down Recovery Time

PDIX

25, 26

DQ-DQS hold, DQS to first DQ to go non-valid, per access

25, 26

-0.4ns

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

REFRESH to REFRESH command interval`

REFC

µs

Average periodic refresh interval

REFI

7.8

µs

ACTIVE to READ delay

RCDR

ACTIVE to WRITE delay

RCDW

PRECHARGE command period

DQS Read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS Read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

Terminating voltage delay to V

VTD

DQS Write preamble

WPRE

0.25

DQS Write preamble setup time

WPRES

20, 21

DQS Write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Data valid output window

QH-

DQSQ

QH-

DQSQ

QH-

DQSQ

128Mb: x32 DDR SDRAM

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

AC timing and I

tests may use a V

-to-V

swing

of up to 1.5V in the test environment, but input
timing is still referenced to V

REF

(or to the crossing

point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew
rate for the input signals used to test the device is
1V/ns in the range between V

(

) and V

(

The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in
that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

REF

is expected to equal V

Q/2 of the transmit-

ting device and to track variations in the DC level
of the same. Peak-to-peak noise on V

REF

may not

exceed ±2 percent of the DC value. Thus, from
V

Q/2, V

REF

is allowed ±25mV for DC error and an

additional ±25mV for AC noise.

is not applied directly to the device. V

is a

system supply for signal termination resistors, is
expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

is the magnitude of the difference between

the input level on CK and the input level on CK#.

The value of V

is expected to equal V

Q/2 of

the transmitting device and must track variations
in the DC level of the same.

10. I

is dependent on output loading and cycle

rates. Specified values are obtained with
minimum cycle time at CL = 5 for -33, CL = 4 for -
4, and CL = 3 for -5. Outputs are open during IDD
measurments.

11. Enables on-chip refresh and address counters.
12. I

specifications are tested after the device is

properly initialized.

NOTES

All voltages referenced to V

Tests for AC timing, I

, and electrical AC and DC

characteristics may be conducted at nominal
reference/supply voltage levels, but the related
specifications and device operation are guaran-
teed for the full voltage range specified.

Outputs measured with equivalent load:

13. This parameter is sampled. V

= +2.5V ±0.125V,

Q = +2.5V ±0.125V, V

REF

= V

, f = 100 MHz,

= 25°C, V

OUT

(

) = V

Q/2, V

OUT

(peak to peak) =

0.2V. DM input is grouped with I/O pins,
reflecting the fact that they are matched in
loading.

14. Command/Address input slew rate = 1V/ns. If

the slew rate is less than 0.3V/ns, timing is no
longer referenced to the mid-point but to the
V

(

) maximum and V

(

) minimum points.If

the slew rate exceeds 3V/ns, functionality is
uncertain.

15. The CK/CK# input reference level (for timing

referenced to CK/CK#) is the point at which CK
and CK# cross; the input reference level for
signals other than CK/CK# is V

REF

16. Inputs are not recognized as valid until V

REF

stabilizes. Exception: during the period before
V

REF

stabilizes, CKE

0.3 x V

Q is recognized as

LOW.

17. The output timing reference level, as measured

at the timing reference point indicated in Note 3,
is V

18.

HZ and

LZ transitions occur in the same access

time windows as valid data transitions. These
parameters are not referenced to a specific
voltage level, but specify when the device output
is no longer driving (HZ) or begins driving (LZ).

19. The maximum limit for this parameter is not a

device limit. The device will operate with a
greater value for this parameter, but system
performance (bus turnaround) will degrade
accordingly.

20. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic LOW)
applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on

DQSS.

22. MIN (

RC or

RFC) for I

measurements is the

smallest multiple of

CK that meets the minimum

absolute value for the respective parameter.

RAS

MAX for I

measurements is the largest multiple

CK that meets the maximum absolute value

for

RAS.

23. The refresh period 32ms. This equates to an

average refresh rate of 7.8µs.

Output
(V

OUT

)

Reduced
Drive)

Reference

Point

20pF

Output
(V

OUT

)

Impedance
Match

Reference

Point

10pF

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

24. The I/O capacitance per DQS and DQ byte/group

will not differ by more than this maximum
amount for any given device.

25. The valid data window is derived by achieving

other specifications -

HP (

CK/2),

DQSQ,

and

QH [

HP - 0.4ns (-3),

HP - 0.4ns (-4) or

HP -

0.5ns (-4)]. The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle
variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data
valid window derating curves are provided below
for duty cycles ranging between 50/50 and 45/55.

26. Referenced to each output group: DQS with DQ0-

DQ31

27. This limit is actually a nominal value and does

not result in a fail value. CKE is HIGH during
REFRESH command period (

RFC [MIN]) else

CKE is LOW (i.e., during standby).

28. The DC values define where the input slew rate

requirements are imposed, and the input signal
must not violate these levels in order to maintain

NOTES (continued)

a valid level. The inputs require the AC value to
be achieved during signal transition edge and
the driver should achieve the same slew rate
through the AC values.

29. The Input capacitance per pin group will not

differ by more than this maximum amount for
any given device..

30. CK and CK# input slew rate must be

1V/ns.

31. DQ and DM input slew rates must not deviate

from DQS by more than 10%. If the DQ/DM/DQS
slew rate is less than 0.5V/ns, timing is no longer
referenced to the mid-point but to the V

(

)

maximum and V

(

) minimum points.

32. Vdd must not vary more than 4% if CKE is not

active while any bank is active.

33. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same
amount.

34.

HP (MIN) is the lesser of

CL minimum and

minimum actually applied to the device CK and CK/
inputs, collectively during bank active.

DERATING DATA VALID WINDOW

(

QH -

DQSQ)

0.850

0.834

0.817

0.801

0.784

0.768

0.751

0.735

0.718

0.702

0.685

1.150

1.130

1.110

1.090

1.070

1.050

1.030

1.010

0.990

0.970

0.950

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

50/50

49.5/50.5 49/51

48.5/52.5

48/52

47.5/53.5

47/53

46.5/54.5

46/54

45.5/55.5

45/55

Clock Duty Cycle

-33 @ tCK = 3.3ns

-4 @ tCK = 4ns

-5 @ tCK = 5ns

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

NOTES (continued)

35. READs and WRITEs with autoprecharge are not

allowed to be issued until

RAS (MIN) can be

satisfied prior to the internal precharge com-
mand being issued.

36. Impedance Matched Drive Curves:

a) The full variation in driver pull-down current

from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figures A

b)The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figures A .

c) The full variation in driver pull-up current from

minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figures B.

d)The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figures B.

e) The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
will not exceed 1.7, for device drain-to-source
voltages from 0 to V

Q/2.

f) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±30%, for device drain-to-source voltages from
0 to V

Q/2.

37. Reduced Output Drive Curves:

a) The full variation in driver pull-down current

from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figures C
and D.

b)The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figures C and D.

c) The full variation in driver pull-up current from

minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figures C and D.

Figure B

Pull-Up Characteristics

Figure A

Pull-Down Characteristics

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Vout (V)

Iout(mA)

Max

Min

Nominal Low

Nominal High

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Vout (V)

Iout(mA)

-45

-40

-35

-30

-25

-20

-15

-10

-5

Max

Min

Nominal Low

Nominal High

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

NOTES (continued)

d)The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
FiguresC and C.

e) The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
will not exceed 1.7, for device drain-to-source
voltages from 0 to V

Q/2.

f) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±30%, for device drain-to-source voltages from
0 to V

Q/2.

38. The voltage levels used are derived from the

refernced test load. In practice, the voltage levels
obtained from a properly terminated bus will
provide significantly different voltage values.

39. V

overshoot: VIH (MAX) = V

Q+1.5V for a pulse

width

3ns and the pulse width can not be

greater than 1/3 of the cycle rate. V

undershoot:

(MIN) = -1.5V for a pulse width

3ns and the

pulse width can not be greater than 1/3 of the
cycle rate.

40. All speed grades support CL 2, 3, 4, and 5 but only

the speed grades listed in the AC timing tables are
tested.

41. The DLL must be reset when changing the

frequency.

42. V

and V

Q must track each other.

Figure D

Pull-Up

Figure C

Pull-Down

Vout (V)

Iout(mA)

0.0

0.5

1.0

1.5

2.0

2.5

Nominal Low

Nominal High

MIN

MAX

Vout (V)

Iout(mA)

-120

-100

-80

-60

-40

-20

0.0

0.5

1.0

1.5

2.0

2.5

Nominal Low

Nominal High

MIN

MAX

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

REDUCED OUTPUT DRIVE CHARACTERISTICS

PULL-DOWN CURRENT (mA)

PULL-UP CURRENT (mA)

VOLTAGE

NOMINAL NOMINAL

(V)

LOW

HIGH

MINIMUM MAXIMUM

LOW

HIGH

MINIMUM MAXIMUM

0.1

3.3

3.7

2.5

4.8

-3.3

-4.1

-2.5

-4.9

0.2

6.6

7.3

5.0

9.4

-6.6

-7.8

-5.0

-9.7

0.3

9.8

10.9

7.4

14.0

-9.8

-11.4

-7.4

-14.5

0.4

13.0

14.4

10.0

18.3

-12.9

-14.9

-10.0

-19.2

0.5

16.1

17.8

12.4

22.6

-16.1

-18.4

-12.4

-23.9

0.6

18.7

21.1

14.9

26.7

-18.5

-21.9

-14.9

-28.4

0.7

21.3

23.9

17.4

30.7

-20.5

-25.3

-17.4

-32.9

0.8

23.6

26.9

19.9

34.1

-22.2

-28.7

-19.5

-37.3

0.9

25.6

29.8

21.4

37.7

-23.6

-32.1

-20.6

-41.7

1.0

27.7

32.6

23.0

41.2

-24.8

-35.4

-20.9

-46.0

1.1

29.2

35.2

24.2

44.5

-25.8

-38.6

-21.1

-50.2

1.2

30.3

37.7

25.0

47.7

-26.6

-41.9

-21.2

-54.3

1.3

31.3

40.1

25.4

50.7

-27.0

-45.2

-21.3

-58.4

1.4

32.0

42.4

25.6

53.5

-27.2

-48.4

-21.4

-62.4

1.5

32.5

44.4

25.8

56.0

-27.4

-51.6

-21.5

-66.4

1.6

32.7

46.4

25.9

58.6

-27.5

-54.7

-21.6

-70.4

1.7

32.9

48.1

26.2

60.6

-27.6

-57.8

-21.7

-73.8

1.8

33.2

49.8

26.4

62.6

-27.7

-60.7

-21.8

-77.8

1.9

33.5

51.5

26.5

64.6

-27.8

-64.1

-21.8

-81.3

2.0

33.8

52.5

26.7

66.6

-27.9

-67.0

-21.9

-84.7

2.1

33.9

53.5

26.8

68.3

-28.0

-69.8

-21.9

-88.1

2.2

34.2

54.5

26.9

69.9

-28.1

-72.7

-22.0

-91.6

2.3

34.5

55.0

27.0

71.5

-28.2

-75.6

-22.0

-95.0

2.4

34.6

55.5

27.0

72.9

-28.2

-78.4

-22.1

-97.9

2.5

34.9

56.0

27.1

74.1

-28.3

-81.3

-22.2

-101.3

NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

Figure 28a

Data Output Timing

DQSQ,

QH and Data Valid Window for TQFP Package

DQ (Last data valid)

DQS

DQ (Last data valid)

DQ (First data no longer valid)

All DQs and DQS, collectively

NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an "early DQS,"
at T3 is a "nominal DQS," and at T3n is a "late DQS."
2. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and
ends with the last valid transition of DQs .
3. tQH is derived from tHP: tQH = tHP
4. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
5. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.
6. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, DQ11, DQ13, DQ14, DQ15, DQ16, DQ17, DQ18, DQ19

DQ20, DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27, DQ28, DQ29, DQ30, or DQ31.

Earliest signal transition

Latest signal transition

T2n

T3n

CK#

T2n

T3n

tQH

tHP

tQH

tHP

tQH

tDQSQ

Data

Valid

window

Data

Valid

window

Data

Valid

window

Data

Valid

window

128Mb: x32 DDR SDRAM

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4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

DQ (Last data valid)

DQS0

DQ (Last data valid)

DQ (First data no longer valid)

DQ0 - DQ7 and DQS0, collectively

NOTE: 1. DQs transitioning after DQS transition define tDQSQ
window. LDQS defines the lower byte and
UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not
cumulative over time and begins with DQS transition
and ends with the last valid transition of DQs .

T2n

T3n

CK#

T2n

T3n

tQH

tDQSQ

Data Valid

window

Data Valid

window

DQ (Last data valid)

DQS1

DQ (Last data valid)

DQ (First data no longer valid)

DQ8 - DQ15 and DQS1, collectively

T2n

T3n

tQH

tDQSQ

tHP

tQH

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition
collectively when a bank is active.
6. The data valid window is derived for each
DQS transition and is tQH minus tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
8. DQ16, DQ17, DQ18, D19, DQ20, DQ21, DQ22, or DQ23.
9. DQ24, DQ25, DQ26, D26, DQ28, DQ29, DQ30, or DQ31.

DQS1 (DQ8 - DQ15)

DQS0 (DQ0 - DQ7)

Data Valid

window

DQ (Last data valid)

DQS2

DQ (Last data valid)

DQ (First data no longer valid)

DQ16 - DQ23 and DQS2, collectively

T2n

T3n

CK#

T2n

T3n

tQH

tDQSQ

Data Valid

window

Data Valid

window

DQ (Last data valid)

UDQS

DQ (Last data valid)

DQ (First data no longer valid)

DQ24 - DQ31 and DQS3, collectively

T2n

T3n

tQH

tDQSQ

tHP

tQH

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

DQS3 (DQ24 - DQ31)

DQS2 (DQ16 - DQ23)

Data Valid

window

Figure 28b

Data Output Timing

DQSQ,

QH and Data Valid Window for FBGA Package

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

Figure 29

Data Output Timing

AC and

DQSCK

Figure 30

Data Input Timing

CK#

DQS, or LDQS/UDQS

T2n

T3n

T4n

T5n

NOTE: 1. tDQSCK is the DQS output window relative to CK and is the long term component of DQS skew.
2. DQs transitioning after DQS transition define tDQSQ window.
3. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.
4. tAC is the DQ output window relative to CK, and is the long term component of DQ skew.
5. tLZ

(MIN)

and tAC

(MIN)

are the first valid signal transition.

6. tHZ

(MAX

,and tAC

(MAX)

are the latest valid signal transition.

7. READ command with CL = 2 issued at T0.

tRPST

tLZ

(MIN)

tDQSCK

(MAX)

tDQSCK

(MIN)

tDQSCK

(MAX)

tDQSCK

(MIN)

tHZ

(MAX)

tRPRE

DQ (Last data valid)

DQ (First data valid)

All DQs collectively

tAC

(MIN)

tAC

(MAX)

tLZ

(MIN)

tHZ

(MAX)

T2n

T3n

T4n

T5n

T2n

T3n

T4n

T5n

DQS

tDQSS

tDQSH

tWPRE

tWPRES

tWPST

tDH

tDS

tDQSL

tDSS2 tDSH1

tDSH1

tDSS2

CK#

T1n

T2n

NOTE: 1. tDSH

(MIN)

generally occurs during tDQSS

(MIN)

2. tDSS

(MIN)

generally occurs during tDQSS

(MAX)

DON T CARE

TRANSITIONING DATA

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

TIMING PARAMETERS

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (5)

CK (4)

CK (3)

INITIALIZE AND LOAD MODE REGISTERS

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.9

MRD

RFC

VTD

CKE

LVCMOS
LOW LEVEL

BA0, BA1

200 cycles of CK

Load Extended

Mode Register

Load Mode

MRD

RFC

Power-up:
V

and

CK stable

T = 200 s

High-Z

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DQS

High-Z

A0-A7, A9-A11

ALL BANKS

CK#

TT1

tVTD

REF

COMMAND

LMR

NOP

PRE

LMR

ACT5

BA0 = H,

BA1 = L

tIS

tIH

BA0 = L,

BA1 = L

tIS

tIH

(

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(

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(

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(

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(

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(

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CODE CODE

tIS

tIH

CODE CODE

(

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(

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(

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(

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PRE

ALL BANKS

tIS

tIH

NOTE:

1. V

is not applied directly to the device; however, tVTD must be greater than or equal to zero to avoid device latch-up.

2. Although not required by the Micron device, JEDEC specifies resetting the DLL with A8 = H.
3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.
4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied after the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address,
BA = Bank Address

(

)

(

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(

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(

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Ta0

Tb0

Tc0

Td0

Te0

Tf0

(

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DON T CARE

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(

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128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

POWER-DOWN MODE

CK#

COMMAND

VALID1

NOP

ADDR

CKE

NOTE: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down

mode shown is precharge power-down. If this command is an ACTIVE (or if at least one row is

already active), then the power-down mode shown is active power-down.
2. No column accesses are allowed to be in progress at the time power-down is entered.

DQS

NOP

VALID

Enter 2

Power-Down

Mode

Exit

Power-Down

Mode

(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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Ta0

Ta1

Ta2

NOP

DON T CARE

(

)

(

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(

)

(

)

VALID

PDIX

TIMING PARAMETERS

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (5)

3.3

CK (4)

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

CK (3)

0.9

PDIX

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

AUTO REFRESH MODE

CK#

COMMAND

NOP

VALID

NOP

PRE

CKE

A0-A7, A9-A11

BA0, BA1

Bank(s)

NOTE:

1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
3. Don t Care if A8 is HIGH at this point; A8 must be HIGH if more than one bank is active (i.e., must precharge all active banks).
4. DM, DQ and DQS signals are all Don t Care /High-Z for operations shown.
5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.

NOP

NOP2

ACT

NOP2

ONE BANK

ALL BANKS

(

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DQS

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tRFC

tRP

tRFC

Ta0

Tb0

Ta1

Tb1

Tb2

DON T CARE

TIMING PARAMETERS

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (5)

3.3

CK (4)

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

CK (3)

0.9

RFC

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

SELF REFRESH MODE

CK#

COMMAND

NOP

ADDR

CKE

VALID

DQS

VALID

NOP

NOTE: 1. Clock must be stable before exiting self refresh mode.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3.

XSNR is required before any non-READ command can be applied, and

XSRD (200 cycles of CK)

is required before a READ command can be applied.

4. AR = AUTO REFRESH command.

tCK

tXSNR/
tXSRD

tIS

tIH

tIS

Enter Self Refresh Mode

Exit Self Refresh Mode

(

)

(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

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(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Ta0

Tb0

Ta1

(

)

(

)

(

)

(

)

(

)

(

)

DON T CARE

(

)

(

)

(

)

(

)

TIMING PARAMETERS

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (5)

3.3

CK (4)

CK (3)

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.9

XSNR

XSRD

200

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

BANK READ WITHOUT AUTO PRECHARGE

CK#

CKE

BA0, BA1

RCD

RAS

CL = 2

T5n

T6n

DQS

Case 1:

(MIN)

and

DQSCK

(MIN)

Case 2:

(MAX)

and

DQSCK

(MAX)

DQS

RPRE

RPST

DQSCK

(MIN)

DQSCK

(MAX)

(MIN)

(MAX)

(MIN)

(MAX)

NOP6

COMMAND

ACT

Col n

PRE7

Bank x

Bank x4

ACT

Bank x

NOP6

(MIN)

NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. "Don't Care" if A8is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. The PRECHARGE command can only be applied at T5 if

RAS minimum is met.

ONE BANK

ALL BANKS

DON'T CARE

TRANSITIONING DATA

A0-A7

A9-A11

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

BANK READ WITH AUTO PRECHARGE

CK#

CKE

BA0, BA1

RCD

CL = 2

T5n

T6n

DQS

Case 1:

(MIN)

and

DQSCK

(MIN)

Case 2:

(MAX)

and

DQSCK

(MAX)

DQS

RPRE

RPST

DQSCK

(MIN)

DQSCK

(MAX)

(MIN)

(MAX)

(MIN)

(MAX)

NOP5

COMMAND

ACT

Col n

NOP5

Bank x

ACT

Bank x

NOP5

(MIN)

NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The READ command can only be applied at T3 if

RAS minimum is met by T5.

DON'T CARE

TRANSITIONING DATA

A0-A7

A9-A11

RAS6

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

BANK WRITE WITHOUT AUTO PRECHARGE

TIMING PARAMETERS

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (5)

3.3

CK (4)

CK (3)

0.45

DQSH

0.4

DQSL

0.4

DQSS

0.8

1.2

0.8

1.2

0.8

1.2

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

DSS

0.25

DSH

0.25

0.9

RAS

120,000

RCDW

WPRE

0.25

WPRES

WPST

0.4

0.6

0.4

0.6

0.4

0.6

CK#

CKE

BA0, BA1

RCD

RAS

DSH

T5n

T4n

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. "Don't Care" if A8 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

7. tDSH is applicable during tDQSS (MIN)

and is referenced from CK T4 or T5.

8. tDSS is applicable during tDQSS (MAX)

and is referenced from CK T5 or T6.

NOP6

COMMAND

ACT

Col n

WRITE2

NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6

DQSL

DQSH

WPST

DSS

DSH

DSS

Bank x4

DQS

tDS

tDH

DON'T CARE

TRANSITIONING DATA

DQSS (NOM)

A0-A7

A9-A11

WPRE

WPRES

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

BANK WRITE WITH AUTO PRECHARGE

TIMING PARAMETERS

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (5)

3.3

CK (4)

CK (3)

0.45

DQSH

0.4

DQSL

0.4

DQSS

0.8

1.2

0.8

1.2

0.8

1.2

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

DSS

0.25

DSH

0.25

0.9

RAS

120,000

RCDW

WPRE

0.25

WPRES

WPST

0.4

0.6

0.4

0.6

0.4

0.6

CK#

CKE

BA0, BA1

tCL

RCD

RAS

DSH

T5n

T4n

A0-A7

A9-A11

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.

6. tDSH is applicable during tDQSS(MIN)

and is referenced from CK T4 or T5.

7. tDSS is applicable during tDQSS (MAX)

and is referenced from CK T5 or T6.

NOP5

COMMAND

ACT

Col n

WRITE2

NOP5

Bank x

NOP5

Bank x

NOP5

DQSL

DQSH

WPST

DSS

DSH

DSS

DQS

DQSS (NOM)

DON'T CARE

TRANSITIONING DATA

WPRES

WPRE

128Mb: x32 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4M32DDR_B.p65 Rev. B, Pub. 7/02

128Mb: x32

DDR SDRAM

ADVANCE

WRITE DM OPERATION

TIMING PARAMETERS

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (5)

3.3

CK (4)

CK (3)

0.45

DQSH

0.4

DQSL

0.4

DQSS

0.8

1.2

0.8

1.2

0.8

1.2

-33

-4

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

DSS

0.25

DSH

0.25

0.9

RAS

120,000

RCDW

WPRE

0.25

WPRES

WPST

0.4

0.6

0.4

0.6

0.4

0.6

CK#

CKE

BA0, BA1

RCD

RAS

DSH

tRP

tWR

T5n

T4n

7. tDSH is applicable during tDQSS (MIN)

and is referenced from CK T4 or T5.

8. tDSS is applicable during tDQSS (MAX)

and is referenced from CK T5 or T6.

9. tDS and tDH are referanced from DQS

NOP6

COMMAND

ACT

Col n

WRITE2

NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6

DQSL

DQSH

WPST

DSS

DSH

DSS

Bank x4

DQS

DON'T CARE

TRANSITIONING DATA

DQSS (NOM)

A0-A7

A9-A11

WPRES

WPRE

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Document Outline

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