Document Outline

Features
Options
Pin Assignment (Top View)
Key Timing Parameters
256Mb DDR SDRAM Part Numbers
General Description
Table of Contents
Functional Block Diagrams
- 128 Meg x 4
- 64 Meg x 8
- 32 Meg x 16
Pin Descriptions
Reserved NC Pins
Functional Description
Initialization
Register Definition
- Mode Register
- Burst Length
- Burst Type
- Extended Mode Register
- Output Drive Strength
- DLL Enable/Disable
Figure 1 Mode Register Definition
Table 1 Burst Definition
Read Latency
Figure 2 CAS Latency
Table 2 CAS Latency (CL)
Figure 3 Extended Mode Register Definition
Commands
- Deselect
- No Operation (NOP)
- Load Mode Register
- Active
- Read
- Write
- Precharge
- Auto Precharge
- Burst Terminate
- Auto Refresh
- Self Refresh
Truth Table 1 - Commands
Truth Table 1A - DM Operation
Operations
- Reads
- WRITEs
- PRECHARGE
- Power-Down (CKE not active)
Figure 4 Activating a Specific Row in a Specific Bank
Figure 5 Example
Figure 6 READ Command
Figure 7 READ Burst
Figure 8 Consecutive READ Bursts
Figure 9 Nonconsecutive READ Bursts
Figure 10 Random READ Accesses
Figure 11 Terminating a READ Burst
Figure 12 READ to WRITE
Figure 13 READ to PRECHARGE
Figure 14 WRITE Command
Figure 15 WRITE Burst
Figure 16 Consecutive WRITE to WRITE
Figure 17 Nonconsecutive WRITE to WRITE
Figure 18 Random WRITE Cycles
Figure 19 WRITE to READ - Uninterrupting
Figure 20 WRITE to READ - Interrupting
Figure 21 WRITE to READ - Odd Number of Data, Interrupting
Figure 22 WRITE to PRECHARGE - Uninterrupting
Figure 23 WRITE to Precharge - Interrupting
Figure 24 WRITE to PRECHARGE Odd Number of Data, Interrupting
Figure 25 PRECHARGE Command
Figure 26 Power-Down
Truth Table 2 - CKE
Truth Table 3 - Current State Bank n - Command to Bank n
Truth Table 4 - Current State Bank n - Command to Bank m
Absolute Maximum Ratings
DC Electrical Characteristics andOperating Conditions
AC Input Operating Conditions
Figure 27 Input Voltage Waveform
Clock Input Operating Conditions
Figure 28 - SSTL_2 Clock Input
Capacitance (x4, x8)
IDD Specifications and Conditions (x4, x8)
Capacitance (x16)
IDD Specifications and Conditions
Electrical Characteristics and Recommended AC Operating Conditions
Slew Rate Derating Values
Slew Rate Derating Values
Notes
Normal Output Drive Characteristics
Reduced Output Drive Characteristics
Figure 29 x4, x8 Data Output Timing
Figure 29 A x16 Data Output Timing
Figure 30 Data Output Timing
Figure 31 Data Input Timing
Initialize and Load Mode Registers
Power-Down Mode
Auto Refresh Mode
Self Refresh Mode
Bank Read - Without Auto Precharge
Bank Read - With Auto Precharge
Bank Write - Without Auto Precharge
Bank Write - With Auto Precharge
WRITE - DM Operation
(TG) Option 66-Pin Plastic TSOP (400 mil)

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE

SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S

PRODUCTION DATA SHEET SPECIFICATIONS.

DOUBLE DATA RATE
(DDR) SDRAM

MT46V128M4 32 Meg x 4 x 4 banks
MT46V64M8 16 Meg x 8 x 4 banks
MT46V32M16 8 Meg x 16 x 4 banks

For the latest data sheet revisions, please refer to the Micron
Web site:

www.micron.com/datasheets

PIN ASSIGNMENT (TOP VIEW)

66-Pin TSOP

FEATURES

· V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V

· Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data
capture (x16 has two one per byte)

· Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

· Differential clock inputs (CK and CK#)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

· DLL to align DQ and DQS transitions with CK
· Four internal banks for concurrent operation
· Data mask (DM) for masking write data (x16 has

two one per byte)

· Programmable burst lengths: 2, 4, or 8
· x16 has programmable IOL/IOV.
· Concurrent auto precharge option is supported
· Auto Refresh and Self Refresh Modes
· Longer lead TSOP for improved reliability (OCPL)
· 2.5V I/O (SSTL_2 compatible)

OPTIONS

MARKING

· Configuration

128 Meg x 4

(32 Meg x 4 x 4 banks)

128M4

64 Meg x 8

(16 Meg x 8 x 4 banks)

64M8

32 Meg x 16

(8 Meg x 16 x 4 banks)

32M16

· Plastic Package OCPL

66-pin TSOP (standard 22.3mm length)

(400 mil width, 0.65mm pin pitch)

· Timing Cycle Time

7.5ns @ CL = 2 (DDR266B)

-75Z

7.5ns @ CL = 2.5 (DDR266B)

-75

10ns @ CL = 2 (DDR200)

-8

· Self Refresh

Standard

none

Low Power

NOTE: 1. Supports PC2100 modules with 2-3-3 timing

2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing

128 Meg x 4

64 Meg x 8

32 Meg x 16

Configuration

32 Meg x 4 x 4 banks

16 Meg x 8 x 4 banks

8 Meg x 16 x 4 banks

Refresh Count

Row Addressing

8K (A0A12)

Bank Addressing

4 (BA0, BA1)

Column Addressing

4K (A0A9, A11, A12)

2K (A0A9, A11)

1K (A0A9)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

DQ15

DQ14
DQ13

DQ12
DQ11

DQ10
DQ9

DQ8

NC
V

UDQS

DNU

REF

UDM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

x16

DQ0

DQ1

DQ2

VssQ

DQ3

DQ4

DQ5
DQ6

VssQ

DQ7

LDQS

DNU

LDM

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

x16

DQ7

DQ6

DQ5

DQ4

NC
NC
V

DQS

DNU

REF

DM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

NC
V

DQ3

NC
NC
V

DQ2

NC
NC
V

DQS

DNU

REF

DM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

DQ0

DQ1

DQ2

DQ3

NC
NC

DNU

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

DQ0

NC
NC

DQ1

NC
NC

DNU

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

KEY TIMING PARAMETERS

SPEED

CLOCK RATE

DATA-OUT

ACCESS

DQS-DQ

GRADE

CL = 2**

CL = 2.5**

WINDOW* WINDOW

SKEW

-75

133 MHz

2.5ns

±0.75ns

+0.5ns

-75

100 MHz

133 MHz

2.5ns

±0.75ns

+0.5ns

-8

100 MHz

125 MHz

3.4ns

±0.8ns

+0.6ns

*Minimum clock rate @ CL = 2 (-8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

GENERAL DESCRIPTION

The 512Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing
536,870,912 bits. It is internally configured as a quad-
bank DRAM.

The 512Mb DDR SDRAM uses a double data rate

architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 512Mb DDR SDRAM
effectively consists of a single 2n-bit wide, one-clock-
cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data
transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted ex-

ternally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower byte
and one for the upper byte.

The 512Mb DDR SDRAM operates from a differen-

tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.

Read and write accesses to the DDR SDRAM are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-

tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE com-
mand are used to select the bank and the starting col-
umn location for the burst access.

The DDR SDRAM provides for programmable READ

or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.

As with standard SDR SDRAMs, the pipelined,

multibank architecture of DDR SDRAMs allows for con-
current operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All full
drive strength outputs are SSTL_2, Class II compat-
ible.

NOTE: 1. The functionality and the timing specifications

discussed in this data sheet are for the DLL-enabled
mode of operation.

2. Throughout the data sheet, the various figures and

text refer to DQs as "DQ." The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, the x16 is
divided in to two bytes--the lower byte and upper
byte. For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS; and for the
upper byte (DQ8 through DQ15) DM refers to UDM
and DQS refers to UDQS.

(Note: xx= -75, -75Z, or -8)

512Mb DDR SDRAM PART NUMBERS

PART NUMBER

CONFIGURATION

I/O DRIVE LEVEL

REFRESH OPTION

MT46V128M4TG-xx

128 Meg x 4

Full Drive

Standard

MT46V128M4TG-xxL

128 Meg x 4

Full Drive

Low Power

MT46V64M8TG-xx

64 Meg x 8

Full Drive

Standard

MT46V64M8TG-xxL

64 Meg x 8

Full Drive

Low Power

MT46V32M16TG-xx

32 Meg x 16

Programmable Drive

Standard

MT46V32M16TG-xxL

32 Meg x 16

Programmable Drive

Low Power

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

TABLE OF CONTENTS

Functional Block Diagram 128 Meg x 4 .............

Functional Block Diagram 64 Meg x 8 ...............

Functional Block Diagram 32 Meg x 16 .............

Pin Descriptions ......................................................

Functional Description .........................................

Initialization ......................................................

Mode Register ...............................................

Burst Length ............................................

Burst Type ................................................ 10
Read Latency ........................................... 11
Operating Mode ...................................... 11

Extended Mode Register ............................... 12

DLL Enable/Disable ................................. 12

Commands ............................................................ 13

Truth Table 1 (Commands)

....................................... 13

Truth Table 1A (DM Operation)

................................. 13

Deselect .............................................................. 14
No Operation (NOP) .......................................... 14
Load Mode Register ........................................... 14
Active ................................................................ 14
Read

................................................................ 14

Write ................................................................ 14
Precharge ........................................................... 14
Auto Precharge .................................................. 14
Burst Terminate ................................................. 14
Auto Refresh ...................................................... 15
Self Refresh ......................................................... 15

Operation .............................................................. 16

Bank/Row Activation ....................................... 16
Reads ................................................................ 17

Read Burst .................................................... 18
Consecutive Read Bursts .............................. 19
Nonconsecutive Read Bursts ....................... 20
Random Read Accesses ................................ 21
Terminating a Read Burst ............................ 23
Read to Write ............................................... 24
Read to Precharge ......................................... 25

Writes ................................................................ 26

Write Burst .................................................... 27
Consecutive Write to Write ......................... 28
Nonconsecutive Write to Write .................. 29

Random Writes ............................................ 30
Write to Read Uninterrupting .................. 31
Write to Read Interrupting ....................... 32
Write to Read Odd, Interrupting ............. 33
Write to Precharge Uninterrupting .......... 34
Write to Precharge Interrupting ............... 35
Write to Precharge Odd, Interrupting ...... 36

Precharge ........................................................... 37
Power-Down ..................................................... 37

Truth Table 2 (CKE)

................................................. 38

Truth Table 3 (Current State, Same Bank)

..................... 39

Truth Table 4 (Current State, Different Bank)

................. 41

Operating Conditions
Absolute Maximum Ratings .................................... 43
DC Electrical and Operating Conditions ..................... 43
AC Input Operating Conditions ........................... 43
Clock Input Operating Conditions ....................... 44
Capacitance x4, x8 .............................................. 45
I

Specifications and Conditions x4, x8 ........... 45

Capacitance x16 .................................................. 46
I

Specifications and Conditions x16 ............... 46

AC Electrical Characteristics (Timing Table) .......... 47
Slew Rate Derating Table ....................................... 48
Data Valid Window Derating ............................... 52

Voltage and Timing Waveforms

Nominal Output Drive Curves ......................... 53
Reduced Output Drive Curves (x16 only) ........ 54
Output Timing

DQSQ and

QH - x4, x8 ...... 55

Output Timing

DQSQ and

QH - x16 .......... 56

Output Timing

and

DQSCK ................. 57

Input Timing ..................................................... 57
Input Voltage .................................................... 58
Initialize and Load Mode Registers .................. 59
Power-Down Mode .......................................... 60
Auto Refresh Mode ........................................... 61
Self Refresh Mode ............................................. 62
Reads

Bank Read - Without Auto Precharge ........ 63
Bank Read - With Auto Precharge .............. 64

Writes

Bank Write Without Auto Precharge ....... 65
Bank Write With Auto Precharge ............. 66
Write DM Operation ................................ 67

66-pin TSOP (TG) dimensions ............................... 68

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

PIN DESCRIPTIONS

TSOP PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

45, 46

CK, CK#

Input

Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.

CKE

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after V

is applied.

CS#

Input

Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.

23, 22, 21

RAS#, CAS#,

Input

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE#

command being entered.

Input

Input Data Mask: DM is an input mask signal for write data. Input

20, 47

LDM, UDM

data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins. For the x16 , LDM is DM for DQ0-
DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC on x4 and x8

26, 27

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

29-32, 35-40,

A0A12

Input

Address Inputs: Provide the row address for ACTIVE commands, and

28, 41, 42

the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address
inputs also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode register
or extended mode register) is loaded during the LOAD MODE
REGISTER command.

2, 4, 5, 7, 8, 10, 11, 13,

DQ015

I/O

Data Input/Output: Data bus for x16 (4, 7, 10, 13, 54, 57, 60, and 63

54, 56, 57, 59, 60, 62,

are NC for x8), (2, 4, 7, 8,10, 13, 54, 57, 59, 60, 63, and 65 for x4).

63, 65

(continued on next page)

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

PIN DESCRIPTIONS (continued)

TSOP PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

RESERVED NC PINS

TSOP PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

A13

Address input for 1Gb devices.

NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins
deemed to be of importance.

2, 5, 8, 11, 56, 59, 62, 65

DQ0-7

I/O

Data Input/Output: Data bus for x8 (2, 8, 59 and 65 are NC for x4).

5, 11, 56, 62

DQ0-3

I/O

Data Input/Output: Data bus for x4.

DQS

I/O

Data Strobe: Output with read data, input with write data. DQS is

16, 51

LDQS, UDQS

edge-aligned with read data, centered in write data. It is used to
capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS is
DQS for DQ8-DQ15. Pin 16 is NC on x4 and x8.

DNU

Do Not Use: Must float to minimize noise.

3, 9, 15, 55, 61

Supply

DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved
noise immunity.

6, 12, 52, 58, 64

Supply

DQ Ground. Isolated on the die for improved noise immunity.

1, 18, 33

Supply

Power Supply: +2.5V ±0.2V.

34, 48, 66

Supply

Ground.

REF

Supply

SSTL_2 reference voltage.

14, 17, 19, 25, 43, 53

No Connect: These pins should be left unconnected.

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

FUNCTIONAL DESCRIPTION

The 512Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing
536,870,912 bits. The 512Mb DDR SDRAM is internally
configured as a quad-bank DRAM.

The 512Mb DDR SDRAM uses a double data rate

architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture, with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 512Mb DDR SDRAM
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two correspond-
ing n-bit wide, one-half-clock-cycle data transfers at
the I/O pins.

Read and write accesses to the DDR SDRAM are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A12 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.

Prior to normal operation, the DDR SDRAM must be

initialized. The following sections provide detailed in-
formation covering device initialization, register defi-
nition, command descriptions and device operation.

Initialization

DDR SDRAMs must be powered up and initialized

in a predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Power must first be applied to V

and V

Q simul-

taneously, and then to V

REF

(and to the system V

). V

must be applied after V

Q to avoid device latch-up,

which may cause permanent damage to the device.
V

REF

can be applied any time after V

Q but is expected

to be nominally coincident with V

. Except for CKE,

inputs are not recognized as valid until after V

REF

applied. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after V

is applied. Maintaining

an LVCMOS LOW level on CKE during power-up is re-
quired to ensure that the DQ and DQS outputs will be
in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.

Once the 200µs delay has been satisfied, a DESE-

LECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP command,
a PRECHARGE ALL command should be applied. Next
a LOAD MODE REGISTER command should be issued
for the extended mode register (BA1 LOW and BA0
HIGH) to enable the DLL, followed by another LOAD
MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL and to program the
operating parameters. Two-hundred clock cycles are
required between the DLL reset and any READ com-
mand. A PRECHARGE ALL command should then be
applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed (

RFC must be satisfied.) Addition-

ally, a LOAD MODE REGISTER command for the mode
register with the reset DLL bit deactivated (i.e., to pro-
gram operating parameters without resetting the DLL)
is required. Following these requirements, the DDR
SDRAM is ready for normal operation.

MODE REGISTER

The mode register is used to define the specific

mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in Fig-
ure 1. The mode register is programmed via the MODE
REGISTER SET command (with BA0 = 0 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either
of these requirements will result in unspecified opera-
tion.

Mode register bits A0-A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-
leaved), A4-A6 specify the CAS latency, and A7-A12
specify the operating mode.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-
mable, as shown in Figure 1. The burst length deter-
mines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for both

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 1

Mode Register Definition

the sequential and the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1-Ai when the burst length is set to two, by
A2-Ai when the burst length is set to four and by A3-Ai
when the burst length is set to eight (where Ai is the
most significant column address bit for a given con-

Table 1

Burst Definition

Burst

Starting Column

Order of Accesses Within a Burst

Length

Address

Type = Sequential

Type = Interleaved

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1 A0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

NOTE: 1. For a burst length of two, A1-Ai select the two-

data-element block; A0 selects the first access
within the block.

2. For a burst length of four, A2-Ai select the four-

data-element block; A0-A1 select the first access
within the block.

3. For a burst length of eight, A3-Ai select the eight-

data-element block; A0-A2 select the first access
within the block.

4. Whenever a boundary of the block is reached

within a given sequence above, the following
access wraps within the block.

figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA0 and BA1)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

M10

M12 M11

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DDR SDRAM

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Table 2

CAS Latency (CL)

Read Latency

The READ latency is the delay, in clock cycles, be-

tween the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, or 2.5 clocks, as shown in Figure 2.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 2
indicates the operating frequencies at which each CAS
latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Figure 2

CAS Latency

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7-A12 each
set to zero, and bits A0-A6 set to the desired values. A
DLL reset is initiated by issuing a MODE REGISTER
SET command with bits A7 and A9-A12 each set to zero,
bit A8 set to one, and bits A0-A6 set to the desired
values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD MODE
REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGIS-
TER command to select normal operating mode.

All other combinations of values for A7-A12 are re-

served for future use and/or test modes. Test modes
and reserved states should not be used because un-
known operation or incompatibility with future ver-
sions may result.

CK#

COMMAND

DQS

CL = 2

READ

NOP

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ

CK#

COMMAND

DQS

CL = 2.5

T2n

T3n

T2n

T3n

DON'T CARE

TRANSITIONING DATA

ALLOWABLE OPERATING

FREQUENCY (MHz)

SPEED

CL = 2

CL = 2.5

-75Z

133

-75

100

133

-8

100

125

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DDR SDRAM

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Figure 3

Extended Mode Register Definition

EXTENDED MODE REGISTER

The extended mode register controls functions be-

yond those controlled by the mode register; these ad-
ditional functions are DLL enable/disable and
output drive strength. These functions are controlled
via the bits shown in Figure 3. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power. The en-
abling of the DLL should always be followed by a LOAD
MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiat-
ing any subsequent operation. Violating either of these
requirements could result in unspecified operation.

Output Drive Strength

The normal drive strength for all outputs are speci-

fied to be SSTL2, Class II. The x16 supports an option
for reduced drive. This option is intended for the sup-
port of the lighter load and/or point-to-point environ-
ments. The selection of the reduced drive strength will
alter the DQs and DQSs from SSTL2, Class II drive
strength to a reduced drive strength, which is approxi-
mately 54% of the SSTL2, Class II drive strength.

The Micron (32Meg x16) device supports a

programmable drive strength option.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.

Operating Mode

Reserved

Valid

DLL

Enable

Disable

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Drive Strength

Normal

Reduced

E12

QFC# Function

Disabled

Reserved

E1,

Operating Mode

A10

A11

A12

BA1 BA0

NOTE: 1. E14 and E13 (BA0 and BA1) must be "1, 0" to select the
Extended Mode Register (vs. the base Mode Register).
2. The reduced drive strength option is not supported on the x4
and x8 versions, and is only available on the x16 version.
3. The QFC# option is not supported.

E2,

E6 E5

E10

E11

E12

QFC#

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DDR SDRAM

ADVANCE

appear following the Operation section; these tables
provide current state/next state information.

COMMANDS

Truth Table 1 provides a quick reference of avail-

able commands. This is followed by a verbal descrip-
tion of each command. Two additional Truth Tables

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;

BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the op-
code to be written to the selected mode register.

3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0-BA1 provide bank address; A0-Ai provide column address (where i = 9 for x16, 9,11 for x8, and 9, 11, 12 for x4);

A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

5. A10 LOW: BA0-BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0-BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

TRUTH TABLE 1 COMMANDS

(Note: 1)

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDR

NOTES

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

Bank/Col

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH

6, 7

(Enter self refresh mode)

LOAD MODE REGISTER

Op-Code

TRUTH TABLE 1A DM OPERATION

(Note: 10)

NAME (FUNCTION)

DQs

NOTES

Write Enable

Valid

Write Inhibit

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DDR SDRAM

ADVANCE

DESELECT

The DESELECT function (CS# HIGH) prevents new

commands from being executed by the DDR SDRAM.
The DDR SDRAM is effectively deselected. Operations
already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

instruct the selected DDR SDRAM to perform a NOP
(CS# LOW). This prevents unwanted commands from
being registered during idle or wait states. Operations
already in progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via inputs A0A12.

See mode register descriptions in the Register Defini-
tion section. The LOAD MODE REGISTER command
can only be issued when all banks are idle, and a subse-
quent executable command cannot be issued until

MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0A12 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank.
A PRECHARGE command must be issued before open-
ing a different row in the same bank.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0Ai (where i = 9 for x16; 9, 11 for x8; or 9, 11, and
12 for x4) selects the starting column location. The value
on input A10 determines whether or not auto precharge
is used. If auto precharge is selected, the row being
accessed will be precharged at the end of the READ
burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs
A0Ai (where i = 9 for x16; 9 and 11 for x8; or 9, 11, and 12
for x4) selects the starting column location. The value on
input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being ac-
cessed will be precharged at the end of the WRITE burst;
if auto precharge is not selected, the row will remain
open for subsequent accesses. Input data

appearing on the DQs is written to the memory array
subject to the DM input logic level appearing coincident
with the data. If a given DM signal is registered LOW, the
corresponding data will be written to memory; if the DM
signal is registered HIGH, the corresponding data in-
puts will be ignored, and a WRITE will not be executed to
that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate

the open row in a particular bank or the open row in
all banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the precharge
command is issued. Except in the case of concurrent
auto precharge, where a READ or WRITE command to
a different bank is allowed as long as it does not
interrupt the data transfer in the current bank and does
not violate any other timing parameters. Input A10
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Other-
wise BA0, BA1 are treated as "Don't Care." Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command
will be treated as a NOP if there is no open row in that
bank (idle state), or if the previously open row is
already in the process of precharging.

AUTO PRECHARGE

Auto precharge is a feature which performs the

same individual-bank precharge function described
above, but without requiring an explicit command.
This is accomplished by using A10 to enable auto
precharge in conjunction with a specific READ or
WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or
WRITE burst. Auto precharge is nonpersistent in that it
is either enabled or disabled for each individual Read or
Write command. This device supports concurrent
auto precharge if the command to the other bank does
not interrupt the data transfer to the current bank.

Auto precharge ensures that the precharge is initi-

ated at the earliest valid stage within a burst. This
"earliest valid stage" is determined as if an explicit
PRECHARGE command was issued at the earliest pos-
sible time, without violating tRAS (MIN), as described
for each burst type in the Operation section of this data
sheet. The user must not issue another command to the
same bank until the precharge time (tRP) is completed.

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate READ bursts (with auto precharge disabled). The
most recently registered READ command prior to the
BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet. The
open page which the READ burst was terminated from
remains open.

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the DDR SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) REFRESH in FPM/EDO DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required.

The addressing is generated by the internal refresh

controller. This makes the address bits a "Don't Care"
during an AUTO REFRESH command. The 512Mb DDR
SDRAM requires AUTO REFRESH cycles at an average
interval of 7.8125µs (maximum).

To allow for improved efficiency in scheduling and

switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH command can be posted to any given
DDR SDRAM, meaning that the maximum absolute
interval between any AUTO REFRESH command and
the next AUTO REFRESH command is 9 × 7.8125µs
(70.3µs). This maximum absolute interval is to allow

future support for DLL updates internal to the DDR
SDRAM to be restricted to AUTO REFRESH cycles, with-
out allowing excessive drift in

AC between updates.

Although not a JEDEC requirement, to provide for

future functionality features, CKE must be active
(High) during the AUTO REFRESH period. The AUTO
REFRESH period begins when the AUTO REFRESH
command is registered and ends

RFC later.

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). The
DLL is automatically disabled upon entering SELF RE-
FRESH and is automatically enabled upon exiting SELF
REFRESH (200 clock cycles must then occur before a
READ command can be issued). Input signals except
CKE are "Don't Care" during SELF REFRESH.

The procedure for exiting self refresh requires a se-

quence of commands. First, CK must be stable prior to
CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for

XSNR

because time is required for the completion of any in-
ternal refresh in progress. A simple algorithm for meet-
ing both refresh and DLL requirements is to apply NOPs
for 200 clock cycles before applying any other com-
mand.

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Operations

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be is-

sued to a bank within the DDR SDRAM, a row in that
bank must be "opened." This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 4.

After a row is opened with an ACTIVE command, a

READ or WRITE command may be issued to that row,
subject to the

RCD specification.

RCD (MIN) should

be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a

RCD specifi-

cation of 20ns with a 133 MHz clock (7.5ns period) re-
sults in 2.7 clocks rounded to 3. This is reflected in
Figure 5, which covers any case where 2 <

RCD (MIN)/

3. (Figure 5 also shows the same case for

RCD; the

same procedure is used to convert other specification
limits from time units to clock cycles).

A subsequent ACTIVE command to a different row

in the same bank can only be issued after the previous
active row has been "closed" (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by

RC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by

RRD.

Figure 5

Example: Meeting

RCD (

RRD) MIN When 2 <

RCD (

RRD) MIN/

Figure 4

Activating a Specific Row in

a Specific Bank

CS#

WE#

CAS#

RAS#

CKE

A0-A12

RA = Row Address
BA = Bank Address

HIGH

BA0,1

CK#

COMMAND

BA0, BA1

ACT

NOP

RRD

tRCD

CK#

Bank x

Bank y

A0-A12

Row

NOP

RD/WR

NOP

Bank y

Col

NOP

DON'T CARE

NOP

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ADVANCE

READs

READ bursts are initiated with a READ command,

as shown in Figure 6.

The starting column and bank addresses are pro-

vided with the READ command and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid nominally
at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#). Figure 7 shows general
timing for each possible CAS latency setting. DQS is
driven by the DDR SDRAM along with output data.
The initial LOW state on DQS is known as the read
preamble; the LOW state coincident with the last data-
out element is known as the read postamble.

Upon completion of a burst, assuming no other com-

mands have been initiated, the DQs will go
High-Z. A detailed explanation of

DQSQ (valid data-

out skew),

QH (data-out window hold), the valid data

window are depicted in Figure 27. A detailed explana-
tion of

DQSCK (DQS transition skew to CK) and

(data-out transition skew to CK) is depicted in Figure
28.

Data from any READ burst may be concatenated

with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data can
be maintained. The first data element from the new
burst follows either the last element of a completed
burst or the last desired data element of a longer burst
which is being truncated. The new READ command
should be issued x cycles after the first READ com-
mand, where x equals the number of desired data ele-
ment pairs (pairs are required by the 2n-prefetch ar-
chitecture). This is shown in Figure 8. A READ com-
mand can be initiated on any clock cycle following a
previous READ command. Nonconsecutive read data
is shown for illustration in Figure 9. Full-speed random
read accesses within a page (or pages) can be performed
as shown in Figure 10.

Figure 6

READ Command

CS#

WE#

CAS#

RAS#

CKE

x4: A0-A9, A11, A12

x8: A0-A9, A11

x16: A0-A9

A10

BA0,1

HIGH

EN AP

DIS AP

x8: A12

x16: A11, A12

CK#

CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge

DON'T CARE

512Mb: x4, x8, x16 DDR SDRAM

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Figure 8

Consecutive READ Bursts

CK#

COMMAND

READ

NOP

READ

NOP

ADDRESS

Bank,

Col n

Bank,

Col b

COMMAND

READ

NOP

READ

NOP

ADDRESS

Bank,

Col n

Bank,

Col b

CL = 2

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T2n

T3n

T4n

T5n

T2n

T3n

T4n

T5n

NOTE: 1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal

AC,

DQSCK, and

DQSQ.

6. Example applies only when READ commands are issued to same device.

DON'T CARE

TRANSITIONING DATA

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ADVANCE

Figure 9

Nonconsecutive READ Bursts

CK#

COMMAND

READ

NOP

ADDRESS

Bank,

Col n

READ

Bank,

Col b

COMMAND

ADDRESS

CL = 2

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T2n

T3n

T5n

AC,

DQSCK, and

DQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecutive READs.

READ

NOP

Bank,

Col n

READ

Bank,

Col b

T2n

T3n

T5n

DON'T CARE

TRANSITIONING DATA

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ADVANCE

Figure 10

Random READ Accesses

CK#

COMMAND

READ

NOP

ADDRESS

Bank,

Col n

Bank,

Col x

Bank,

Col b

Bank,

Col x

Bank,

Col b

READ

Bank,

Col g

COMMAND

ADDRESS

CL = 2

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T2n

T3n

T4n

T5n

NOTE: 1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. Burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous).
3. n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively.
4. READs are to an active row in any bank.
5. Shown with nominal

AC,

DQSCK, and

DQSQ.

READ

NOP

Bank,

Col n

READ

Bank,

Col g

T2n

T3n

T4n

T5n

DON'T CARE

TRANSITIONING DATA

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Data from any READ burst may be truncated with a

BURST TERMINATE command, as shown in Figure 11.
The BURST TERMINATE latency is equal to the READ
(CAS) latency, i.e., the BURST TERMINATE command
should be issued x cycles after the READ command,
where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architec-
ture).

Data from any READ burst must be completed or

truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TER-
MINATE command must be used, as shown in Figure
12. The

DQSS (MIN) case is shown; the

DQSS (MAX)

case has a longer bus idle time. (

DQSS [MIN] and

DQSS

[MAX] are defined in the section on WRITEs.)

A READ burst may be followed by, or truncated with,

a PRECHARGE command to the same bank provided
that auto precharge was not activated. The
PRECHARGE command should be issued x cycles after
the READ command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture). This is shown in Figure 13.
Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until

is met. Note that part of the row precharge time is hid-
den during the access of the last data elements.

READs (continued)

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 12

READ to WRITE

CK#

COMMAND

READ

BST

NOP

ADDRESS

Bank,

Col n

WRITE

Bank,

Col b

T2n

T4n

T5n

NOTE: 1. DO n = data-out from column n.
2. DI b = data-in from column b.
3. Burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2,
the BST command shown can be NOP).
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal

AC,

DQSCK, and

DQSQ.

7. BST = BURST TERMINATE command, page remains open.

CL = 2

DQS

t
(MIN)

DQSS

CK#

COMMAND

READ

BST

NOP

WRITE

NOP

ADDRESS

Bank a,

Col n

NOP

T2n

T5n

CL = 2.5

DQS

t
(MIN)

DQSS

DON'T CARE

TRANSITIONING DATA

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 13

READ to PRECHARGE

CK#

COMMAND

READ

NOP

PRE

NOP

ACT

ADDRESS

Bank a,

Col n

Bank a,

(a or all)

Bank a,

Row

READ

NOP

PRE

NOP

ACT

Bank a,

Col n

CL = 2

tRP

NOTE: 1. DO n = data-out from column n.
2. Burst length = 4, or an interrupted burst of 8.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
5. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out.
6. A READ command with AUTO-PRECHARGE enabled would cause a precharge to be performed

at x number of clock cycles after the READ command, where x = BL / 2.

7. PRE = PRECHARGE command; ACT = ACTIVE command.

CK#

COMMAND

ADDRESS

DQS

CL = 2.5

DQS

T2n

T3n

T2n

T3n

Bank a,

(a or all)

Bank a,

Row

DON'T CARE

TRANSITIONING DATA

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

WRITEs

WRITE bursts are initiated with a WRITE command,

as shown in Figure 14.

The starting column and bank addresses are pro-

vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.

During WRITE bursts, the first valid data-in ele-

ment will be registered on the first rising edge of DQS
following the WRITE command, and subsequent data
elements will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command
and the first rising edge is known as the write preamble;
the LOW state on DQS following the last data-in ele-
ment is known as the write postamble.

The time between the WRITE command and the

first corresponding rising edge of DQS (

DQSS) is speci-

fied with a relatively wide range (from 75 percent to 125
percent of one clock cycle). All of the WRITE diagrams
show the nominal case, and where the two extreme
cases (i.e.,

DQSS [MIN] and

DQSS

[MAX]) might not

be intuitive, they have also been included. Figure 15
shows the nominal case and the extremes of

DQSS for

a burst of 4. Upon completion of a burst, assuming no
other commands have been initiated, the DQs will re-
main High-Z and any additional input data will be ig-
nored.

Data for any WRITE burst may be concatenated

with or truncated with a subsequent WRITE command.
In either case, a continuous flow of input data can be
maintained. The new WRITE command can be issued
on any positive edge of clock following the previous
WRITE command. The first data element from the new
burst is applied after either the last element of a com-
pleted burst or the last desired data element of a longer
burst which is being truncated. The new WRITE com-
mand should be issued x cycles after the first WRITE
command, where x equals the number of desired data
element pairs (pairs are required by the 2n-prefetch
architecture).

Figure 16 shows concatenated bursts of 4. An ex-

ample of nonconsecutive WRITEs is shown in Figure
17. Full-speed random write accesses within a page or
pages can be performed as shown in Figure 18.

Data for any WRITE burst may be followed by a

subsequent READ command. To follow a WRITE with-
out truncating the WRITE burst,

WTR should be met

as shown in Figure 19.

Data for any WRITE burst may be truncated by a

subsequent READ command, as shown in Figure 20.
Note that only the data-in pairs that are registered

Figure 14

WRITE Command

prior to the

WTR period are written to the internal ar-

ray, and any subsequent data-in should be masked
with DM as shown in Figure 21.

Data for any WRITE burst may be followed by a

subsequent PRECHARGE command. To follow a
WRITE without truncating the WRITE burst,

WR should

be met as shown in Figure 22.

Data for any WRITE burst may be truncated by a

subsequent PRECHARGE command, as shown in Fig-
ures 23 and 24. Note that only the data-in pairs that are
registered prior to the

WR period are written to the

internal array, and any subsequent data-in should be
masked with DM as shown in Figures 23 and 24. After
the PRECHARGE command, a subsequent command
to the same bank cannot be issued until

RP is met.

CS#

WE#

CAS#

RAS#

CKE

A10

BA0,1

HIGH

EN AP

DIS AP

CK#

CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge

DON'T CARE

x4: A0A9, A11, A12

x8: A0-A9, A11

x16: A0A9

x8: A12

x16:A11, A12

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 19

WRITE to READ Uninterrupting

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

READ

NOP

ADDRESS

Bank a,

Col b

Bank a,

Col n

NOP

T2n

NOTE: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to same device. However, the READ and WRITE commands may be

to different devices, in which case tWTR is not required and the READ command could be applied earlier.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

T1n

T6n

WTR

CL = 2

DQS

DQSS

DQSS (MIN)

CL = 2

DQS

DQSS

DQSS (MAX)

CL = 2

DQS

DQSS

DON'T CARE

TRANSITIONING DATA

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 20

WRITE to READ Interrupting

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

ADDRESS

Bank a,

Col b

Bank a,

Col n

READ

T2n

T5n

NOTE: 1. DI b = data-in for column b.
2. An interrupted burst of 4 or 8 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would
mask the last two data elements.

T1n

T6n

WTR

CL = 2

DQS

DQSS (MIN)

CL = 2

DQS

DQSS (MAX)

CL = 2

DQS

DON'T CARE

TRANSITIONING DATA

DQSS

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 21

WRITE to READ Odd Number of Data, Interrupting

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

ADDRESS

Bank a,

Col b

Bank a,

Col n

READ

T2n

NOTE: 1. DI b = data-in for column b.
2. An interrupted burst of 4 is shown; one data element is written.
3. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last

four data elements.

T1n

T6n

T5n

WTR

CL = 2

DQS

DQSS (MIN)

CL = 2

DQS

DQSS (MAX)

CL = 2

DQS

DON'T CARE

TRANSITIONING DATA

DQSS

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 22

WRITE to PRECHARGE Uninterrupting

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

PRE

NOP

ADDRESS

Bank a,

Col b

Bank,

(a or all)

NOP

T2n

NOTE: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE

commands may be to different devices, in which case tWR is not required and the PRECHARGE command could be
applied earlier.

6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.

T1n

DQS

DQSS (MIN)

DQS

DQSS (MAX)

DQS

DON'T CARE

TRANSITIONING DATA

DQSS

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512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 23

WRITE to Precharge Interrupting

DQSS

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

PRE

NOP

ADDRESS

Bank a,

Col b

Bank,

(a or all)

NOP

T2n

NOTE: 1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 4 is shown; two data elements are written.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. DQS is required at T2 and T2n (nominal case) to register DM.
8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE

command would mask the last two data elements.

9. PRE = PRECHARGE command.

T1n

DQS

DQSS

DQSS (MIN)

DQS

DQSS

DQSS (MAX)

DQS

DON'T CARE

TRANSITIONING DATA

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 24

WRITE to PRECHARGE

Odd Number of Data, Interrupting

DQSS

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

PRE

NOP

ADDRESS

Bank a,

Col b

Bank,

(a or all)

NOP

T2n

NOTE: 1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 4 is shown; one data element is written.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. DQS is required at T1n, T2 and T2n (nominal case) to register DM.
8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE

command would mask the last two data elements.

9. PRE = PRECHARGE command.

T1n

DQS

DQSS

DQSS (MIN)

DQS

DQSS

DQSS (MAX)

DQS

DON'T CARE

TRANSITIONING DATA

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 25

PRECHARGE Command

PRECHARGE

The PRECHARGE command (Figure 25) is used to

deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (

RP) af-

ter the PRECHARGE command is issued. Input A10

No READ/WRITE
access in progress

Exit power-down mode

Enter power-down mode

CKE

CK#

COMMAND

NOP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

NOP

VALID

Ta0

Ta1

Ta2

VALID

DON'T CARE

determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. When
all banks are to be precharged, inputs BA0, BA1 are
treated as "Don't Care." Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.

POWER-DOWN (CKE NOT ACTIVE)

Unlike SDR SDRAMs, DDR SDRAMs require CKE to

be active at all times an access is in progress: from the
issuing of a READ or WRITE command until comple-
tion of the burst. Thus a clock suspend is not supported.
For READs, a burst completion is defined when the
Read Postamble is satisfied; For WRITEs, a burst
completion is defined when the Write Postamble is
satisfied.

Power-down (Figure 26) is entered when CKE is reg-

istered LOW. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in any
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers, excluding CK, CK#, and CKE. For maximum
power savings, the DLL is frozen during precharge
power-down. Exiting power-down requires the device to
be at the same voltage and frequency as when it entered
power-down. However, power-down duration is limited
by the refresh requirements of the device (

REFC).

While in power-down, CKE LOW and a stable clock

signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are "Don't Care."

The power-down state is synchronously exited when

CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.

Figure 26

Power-Down

CS#

WE#

CAS#

RAS#

CKE

A10

BA0,1

HIGH

ALL BANKS

ONE BANK

A0A9, A11, A12

CK#

BA = Bank Address (if A10 is LOW;
otherwise "Don't Care")

DON'T CARE

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

TRUTH TABLE 2 CKE

(Notes: 1-4)

CKE

n-1

CKE

CURRENT STATE

COMMAND

ACTION

NOTES

Power-Down

Maintain Power-Down

Self Refresh

Maintain Self Refresh

Power-Down

DESELECT or NOP

Exit Power-Down

Self Refresh

DESELECT or NOP

Exit Self Refresh

All Banks Idle

DESELECT or NOP

Precharge Power-Down Entry

Bank(s) Active

DESELECT or NOP

Active Power-Down Entry

All Banks Idle

AUTO REFRESH

Self Refresh Entry

See Truth Table 3

NOTE: 1. CKE

is the logic state of CKE at clock edge n; CKE

n-1

was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND

is the command registered at clock edge n, and ACTION

is a result of COMMAND

4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the

XSR period. A minimum of 200

clock cycles is needed before applying a READ command for the DLL to lock.

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

TRUTH TABLE 3 CURRENT STATE BANK n - COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE#

COMMAND/ACTION

NOTES

Any

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

ACTIVE (select and activate row)

Idle

AUTO REFRESH

LOAD MODE REGISTER

READ (select column and start READ burst)

Row Active

WRITE (select column and start WRITE burst)

PRECHARGE (deactivate row in bank or banks)

Read

READ (select column and start new READ burst)

(Auto-

WRITE (select column and start WRITE burst)

10, 12

Precharge

PRECHARGE (truncate READ burst, start PRECHARGE)

Disabled)

BURST TERMINATE

Write

READ (select column and start READ burst)

10, 11

(Auto-

WRITE (select column and start new WRITE burst)

Precharge

PRECHARGE (truncate WRITE burst, start PRECHARGE)

8, 11

Disabled)

NOTE:

1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Truth Table 2) and after

XSNR has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the com-

mands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in
the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses

and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT

or NOP commands, or allowable commands to the other bank should be issued on any clock edge occur-
ring during these states. Allowable commands to the other bank are determined by its current state and
Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when

RP is met. Once

RP is met, the bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when

RCD is met.

Once

RCD is met, the bank will be in the "row active" state.

Read w/Auto-

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends

when

RP has been met. Once

RP is met, the bank will be in the idle state.

Write w/Auto-

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends

when

RP has been met. Once

RP is met, the bank will be in the idle state.

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTE (continued):

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP

commands must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

RC is met.

Once

RC is met, the DDR SDRAM will be in the all banks idle state.

Accessing Mode

MRD

has been met. Once

MRD is met, the DDR SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when

RP is met.

Once

RP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for

precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.

10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge

enabled and READs or WRITEs with auto precharge disabled.

11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMI-

NATE must be used to end the READ burst prior to asserting a WRITE command.

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

TRUTH TABLE 4 CURRENT STATE BANK n - COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE

CS# RAS# CAS# WE#

COMMAND/ACTION

NOTES

Any

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

Idle

Any Command Otherwise Allowed to Bank m

Row

ACTIVE (select and activate row)

Activating,

READ (select column and start READ burst)

Active, or

WRITE (select column and start WRITE burst)

Precharging

PRECHARGE

Read

ACTIVE (select and activate row)

(Auto-

READ (select column and start new READ burst)

Precharge

WRITE (select column and start WRITE burst)

7, 9

Disabled)

PRECHARGE

Write

ACTIVE (select and activate row)

(Auto-

READ (select column and start READ burst)

7, 8

Precharge

WRITE (select column and start new WRITE burst)

Disabled)

PRECHARGE

Read

ACTIVE (select and activate row)

(With Auto-

READ (select column and start new READ burst)

7, 3a

Precharge)

WRITE (select column and start WRITE burst)

7, 9, 3a

PRECHARGE

Write

ACTIVE (select and activate row)

(With Auto-

READ (select column and start READ burst)

7, 3a

Precharge)

WRITE (select column and start new WRITE burst)

7, 3a

PRECHARGE

NOTE:

1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Truth Table 2) and after

XSNR has been

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and

the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the
given command is allowable). Exceptions are covered in the notes below.

(Notes continued on next page)

512Mb: x4, x8, x16 DDR SDRAM

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512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

From Command

To Command

Minimum delay (with concurrent auto precharge)

WRITE w/AP

READ or READ w/AP

[1 + (BL/2)]

CK +

WTR

WRITE or WRITE w/AP

(BL/2) tCK

PRECHARGE

ACTIVE

READ w/AP

READ or READ w/AP

(BL/2) *

WRITE or WRITE w/AP

[CL

+ (BL/2)]

PRECHARGE

ACTIVE

NOTE (continued):

3.Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses

and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Read with Auto

Precharge Enabled: See following text 3a

Write with Auto

Precharge Enabled: See following text 3a

3a.

The read with auto precharge enabled or WRITE with auto precharge enabled states can
each be broken into two parts: the access period and the precharge period. For read with
auto precharge, the precharge period is defined as if the same burst was executed with
auto precharge disabled and then followed with the earliest possible PRECHARGE com-
mand that still accesses all of the data in the burst. For write with auto precharge, the
precharge period begins when tWR ends,with tWR measured as if auto precharge was
disabled. The access period starts with registration of the command and ends where the
precharge period (or tRP) begins.

This device supports concurrent auto precharge such that when a read with auto precharge is
enabled or a write with auto precharge is enabled any command to other banks is allowed, as
long as that command does not interrupt the read or write data transfer already in process. In
either case, all other related limitations apply (e.g., contention between read data and write
data must be avoided).

3b.

The minimum delay from a READ or WRITE command with auto precharge enabled, to a
command to a different bank is summarized below.

= CAS Latency (CL) rounded up to the next integer

BL = Bust Length

4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the

current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled

and READs or WRITEs with auto precharge disabled.

8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMI-

NATE must be used to end the READ burst prior to asserting a WRITE command.

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage Relative to V

............. -1V to +3.6V

Q Supply Voltage Relative to V

.......... -1V to +3.6V

REF

and Inputs Voltage Relative to V

........ -1V to +3.6V

I/O Pins Voltage Relative to V

........ -0.5V to V

Q +0.5V

Operating Temperature, T

(ambient) .... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ........................................................ 1W
Short Circuit Output Current ................................. 50mA

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 15, 16; notes appear on pages 5053) (0°C

+70°C; V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

Supply Voltage

2.3

2.7

36, 41

I/O Supply Voltage

2.3

2.7

36, 41,

I/O Reference Voltage

REF

0.49

x V

0.51

x V

6, 44

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

7, 44

Input High (Logic 1) Voltage

(

)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(

)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT
Any input 0V

, V

REF

pin 0V

1.35V

-2

µA

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT

-5

µA

(DQs are disabled; 0V

OUT

OUTPUT LEVELS: Full drive option - x4, x8, x16
High Current (V

OUT

= V

Q-0.373V, minimum V

REF

, minimum V

)

-16.8

37, 39

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

16.8

OUTPUT LEVELS: Reduced drive option - x16 only
High Current (V

OUT

= V

Q-0.763V, minimum V

REF

, minimum V

)

OHR

-9

38, 39

Low Current (V

OUT

= 0.763V, maximum V

REF

, maximum V

)

OLR

AC INPUT OPERATING CONDITIONS

(Notes: 15, 14, 16; notes appear on pages 5053) (0°C

+70°C; V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.310

14, 28, 40

Input Low (Logic 0) Voltage

(

)

REF

- 0.310

14, 28, 40

I/O Reference Voltage

REF

(

)

0.49 x V

0.51 x V

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

CLOCK INPUT OPERATING CONDITIONS

(Notes: 15, 15, 16, 30; notes appear on pages 5053) (0°C

+ 70°C; V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Clock Input Mid-Point Voltage; CK and CK#

(

)

1.15

1.35

6, 9

Clock Input Voltage Level; CK and CK#

(

)

-0.3

Q + 0.3

Clock Input Differential Voltage; CK and CK#

(

)

0.36

Q + 0.6

6, 8

Clock Input Differential Voltage; CK and CK#

(

)

0.7

Q + 0.6

Clock Input Crossing Point Voltage; CK and CK#

(

)

0.5 x V

Q - 0.2

0.5 x V

Q + 0.2

FIGURE 28 SSTL_2 CLOCK INPUT

CK#

2.80v

Maximum Clock Level

Minimum Clock Level

- 0.30v

1.25v

1.45v

1.05v

(AC)

(DC)

(AC)

NOTE:

1. This provides a minimum of 1.15v to a maximum of 1.35v, and is always half of V

2. CK and CK# must cross in this region.

3. CK and CK# must meet at least V

(DC) min when static and is centered around V

(DC)

4. CK and CK# must have a minimum 700mv peak to peak swing.

5. CK or CK# may not be more positive than V

Q + 0.3v or more negative than Vss - 0.3v.

6. For AC operation, all DC clock requirements must also be satisfied.

7. Numbers in diagram reflect nominal values.

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

CAPACITANCE (x4, x8)

(Note: 13; notes appear on pages 5053)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Delta Input/Output Capacitance: DQs, DQS, DM

0.50

Delta Input Capacitance: Command and Address

0.50

Delta Input Capacitance: CK, CK#

0.25

Input/Output Capacitance: DQs, DQS, DM

4.0

5.0

Input Capacitance: Command and Address

2.0

3.0

Input Capacitance: CK, CK#

2.0

3.0

Input Capacitance: CKE

2.0

3.0

p F

SPECIFICATIONS AND CONDITIONS (x4, x8)

(Notes: 15, 10, 12, 14; notes appear on pages 5053) (0°C

+70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V)

PARAMETER/CONDITION

SYMBOL

-75/-75Z

-8

UNITS NOTES

OPERATING CURRENT: One bank; Active-Precharge;

RC =

RC(MIN);

TBD

22, 48

CK =

CK(MIN); DQ, DM, and DQS inputs changing once per clock cyle;

Address and control inputs changing once every two clock cycles

OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;

TBD

22, 48

RC =

RC(MIN);

CK =

CK(MIN); I

OUT

= 0mA; Address and control inputs

changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;

23, 32

Power-down mode;

CK =

CK(MIN); CKE = LOW;

IDLE STANDBY CURRENT: CS# = HIGH; All banks idle;

CK =

CK(MIN);

CKE = HIGH; Address and other control inputs changing once per clock
cycle. V

= V

REF

for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;

23, 32

Power-down mode;

CK =

CK(MIN); CKE = LOW

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;One bank;

Active-Precharge;

RC =

RAS(MAX);

CK =

CK(MIN); DQ, DM, and DQS

inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank

TBD

22, 48

active; Address and control inputs changing once per clock cycle;

CK =

CK(MIN); I

OUT

= 0mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank

TBD

active; Address and control inputs changing once per clock cycle;

CK =

CK(MIN); DQ, DM, and DQS inputs changing twice per clock cycle

AUTO REFRESH CURRENT

RC =

7.8125µs

27,50

RC =

RC(MIN)

TBD

22,50

SELF REFRESH CURRENT: CKE

0.2V

Standard

TBD

Low power (L)

TBD

OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto

TBD

22, 49

precharge,

RC =

RC(MIN);

CK =

RC(MIN); Address and control inputs change

only during Active READ, or WRITE commands.

MAX

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

CAPACITANCE (x16)

(Note: 13; notes appear on pages 5053)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM

IOL

0.50

Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM

IOU

0.50

Delta Input Capacitance: Command and Address

0.50

Delta Input Capacitance: CK, CK#

0.25

Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM

4.0

5.0

Input Capacitance: Command and Address

2.0

3.0

Input Capacitance: CK, CK#

2.0

3.0

Input Capacitance: CKE

2.0

3.0

SPECIFICATIONS AND CONDITIONS (x16)

(Notes: 15, 10, 12, 14; notes appear on pages 5053) (0°C

+70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V)

PARAMETER/CONDITION

SYMBOL

-75/-75Z

-8

UNITS NOTES

OPERATING CURRENT: One bank; Active-Precharge;

RC =

RC(MIN);

TBD

22, 48

CK =

CK(MIN); DQ, DM, and DQS inputs changing once per clock cyle;

Address and control inputs changing once every two clock cycles;

OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;

TBD

22, 48

RC =

RC(MIN);

CK =

CK(MIN); I

OUT

= 0mA; Address and control inputs

changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;

23, 32

Power-down mode;

CK =

CK(MIN); CKE = LOW;

IDLE STANDBY CURRENT: CS# = HIGH; All banks idle;

CK =

CK(MIN);

CKE = HIGH; Address and other control inputs changing once per clock cycle.
V

= V

REF

for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;

23, 32

Power-down mode;

CK =

CK(MIN); CKE = LOW

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;

Active-Precharge;

RC =

RAS(MAX);

CK =

CK(MIN); DQ, DM, and DQS

inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank

TBD

22, 48

active; Address and control inputs changing once per clock cycle;

CK =

CK(MIN); I

OUT

= 0mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank

TBD

active; Address and control inputs changing once per clock cycle;

CK =

CK(MIN); DQ, DM, and DQS inputs changing twice per clock cycle

AUTO REFRESH CURRENT

RC =

7.8125µs

27,50

RC =

7.8125µs

27,50

SELF REFRESH CURRENT: CKE

0.2V

Standard

TBD

Low power (L)

TBD

OPERATING CURRENT: Four bank interleaving READs (BL=4) with

TBD

22, 49

auto precharge with ,

RC =

RC(MIN);

CK =

RC(MIN); Address and

control inputs change only during Active READ, or WRITE commands.

MAX

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 15, 1417, 33; notes appear on pages 5053) (0°C

+70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V)

AC CHARACTERISTICS

-75Z

-75

-8

PARAMETER

SYMBOL MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL = 2.5

CK (2.5)

7.5

45, 52

CL = 2

CK (2)

7.5

45, 52

DQ and DM input hold time relative to DQS

0.5

0.6

26, 31

DQ and DM input setup time relative to DQS

0.5

0.6

26, 31

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.75

+0.75

-0.8

+0.75

-0.8

+0.8

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.5

0.6

25, 26

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.75

+0.8

18,42

Data-out low-impedance window from CK/CK#

-0.75

-0.8

18,43

Address and control input hold time (fast slew rate)

.90

1.1

Address and control input setup time (fast slew rate)

.90

1.1

Address and control input hold time (slow slew rate)

1.1

Address and control input setup time (slow slew rate)

1.1

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

25, 26

QHS

Data Hold Skew Factor

QHS

0.75

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

20, 21

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window (DVW)

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval

REFC

70.3

µs

Average periodic refresh interval

REFI

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

SLEW RATE DERATING VALUES

(Note: 14; notes appear on pages 5053) (0°C

+70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V)

ADDRESS / COMMAND

SPEED

SLEW RATE

UNITS

-75Z, -75

0.500V / ns

-75Z, -75

0.400V / ns

1.05

-75Z, -75

0.300V / ns

1.10

-75Z, -75

0.200V / ns

1.15

-8

0.500V / ns

1.1

-8

0.400V / ns

1.15

1.1

-8

0.300V / ns

1.20

1.1

-8

0.200V / ns

1.25

1.1

SLEW RATE DERATING VALUES

(Note: 31; notes appear on pages 5053) (0°C

+70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V)

DQ, DM, DQS

SPEED

SLEW RATE

UNITS

-75Z, -75

0.500V / ns

0.50

-75Z, -75

0.400V / ns

0.55

-75Z, -75

0.300V / ns

0.60

-75Z, -75

0.200V / ns

0.65

-8

0.500V / ns

0.60

-8

0.400V / ns

0.65

-8

0.300V / ns

0.70

-8

0.200V / ns

0.75

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

AC timing and I

tests may use a V

-to-V

swing

of up to 1.5V in the test environment, but input
timing is still referenced to V

REF

(or to the crossing

point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew
rate for the input signals used to test the device is
1V/ns in the range between V

(

) and V

(

The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in
that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

REF

is expected to equal V

Q/2 of the transmit-

ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V

REF

may not exceed ±2 percent of the

DC value. Thus, from V

Q/2, V

REF

is allowed

±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V

REF

by-pass capacitor.

is not applied directly to the device. V

is a

system supply for signal termination resistors, is
expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

is the magnitude of the difference between the

input level on CK and the input level on CK#.

The value of V

is expected to equal V

Q/2 of

the transmitting device and must track variations
in the DC level of the same.

10. I

is dependent on output loading and cycle

rates. Specified values are obtained with
minimum cycle time at CL = 2 for -75Z and -8,
CL = 2.5 for -75 with the outputs open.

11. Enables on-chip refresh and address counters.

NOTES

All voltages referenced to V

Tests for AC timing, I

, and electrical AC and DC

characteristics may be conducted at nominal
reference/supply voltage levels, but the related
specifications and device operation are guaran-
teed for the full voltage range specified.

Outputs measured with equivalent load:

12. I

specifications are tested after the device is

properly initialized, and is averaged at the
defined cycle rate.

13. This parameter is sampled. V

= +2.5V ±0.2V,

Q = +2.5V ±0.2V, V

REF

= V

, f = 100 MHz,

= 25°C, V

OUT

(

) = V

Q/2, V

OUT

(peak to peak)

= 0.2V. DM input is grouped with I/O pins,
reflecting the fact that they are matched in
loading.

14. Command/Address input slew rate = 0.5V/ns.

For -75 with slew rates 1V/ns and faster,

IS and

IH are reduced to 900ps. If the slew rate is less

than 0.5V/ns, timing must be derated:

IS has an

additional 50ps per each 100mV/ns reduction in
slew rate from the 500mV/ns.

IH has 0ps added,

that is, it remains constant. If the slew rate
exceeds 4.5V/ns, functionality is uncertain.

15. The CK/CK# input reference level (for timing

referenced to CK/CK#) is the point at which CK
and CK# cross; the input reference level for
signals other than CK/CK# is V

REF

16. Inputs are not recognized as valid until V

REF

stabilizes. Exception: during the period before
V

REF

stabilizes, CKE

0.3 x V

Q is recognized as

LOW.

17. The output timing reference level, as measured at the

timing reference point indicated in Note 3, is V

18.

HZ and

LZ transitions occur in the same access

time windows as valid data transitions. These
parameters are not referenced to a specific
voltage level, but specify when the device output
is no longer driving (HZ) or begins driving (LZ).

19. The maximum limit for this parameter is not a

device limit. The device will operate with a
greater value for this parameter, but system
performance (bus turnaround) will degrade
accordingly.

20. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic LOW)
applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on

DQSS.

22. MIN (

RC or

RFC) for I

measurements is the

smallest multiple of

CK that meets the minimum

absolute value for the respective parameter.

RAS(

MAX

) for I

measurements is the largest

multiple of

CK that meets the maximum

absolute value for

RAS.

23. The refresh period 64ms. This equates to an

Output
(V

OUT

)

Reference

Point

30pF

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

average refresh rate of 7.8125µs. However, an
AUTO REFRESH command must be asserted at
least once every 70.3µs; burst refreshing or
posting by the DRAM controller greater than
eight refresh cycles is not allowed.

24. The I/O capacitance per DQS and DQ byte/group

will not differ by more than this maximum
amount for any given device.

25. The valid data window is derived by achieving

other specifications -

HP (

CK/2),

DQSQ, and

QH (

HP -

QHS). The data valid window derates

directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle
variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data
valid window derating curves are provided below
for duty cycles ranging between 50/50 and 45/55.

26. Referenced to each output group: x4 = DQS with

DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS
with DQ0-DQ7; and UDQS with DQ8-DQ15.

27. This limit is actually a nominal value and does

not result in a fail value. CKE is HIGH during
REFRESH command period (

RFC [MIN]) else

NOTES (continued)

CKE is LOW (i.e., during standby).

28. To maintain a valid level, the transitioning edge

of the input must:
a) Sustain a constant slew rate from the current

AC level through to the target AC level, V

(

)

or V

(

b) Reach at least the target AC level.
c) After the AC target level is reached, continue
to maintain at least the target DC level, V

(

)

or V

(

29. The Input capacitance per pin group will not

differ by more than this maximum amount for
any given device.

30. JEDEC specifies CK and CK# input slew rate must

1V/ns (2V/ns if measured differentially).

31. DQ and DM input slew rates must not deviate

from DQS by more than 10%. If the DQ/DM/DQS
slew rate is less than 0.5V/ns, timing must be
derated: 50ps must be added to

DS and

DH for

each 100mv/ns reduction in slew rate. If slew rate
exceeds 4V/ns, functionality is uncertain.

32. V

must not vary more than 4% if CKE is not

active while any bank is active.

DERATING DATA VALID WINDOW

(

QH -

DQSQ)

3.750

3.700

3.650

3.600

3.550

3.500

3.450

3.400

3.350

3.300

3.250

3.400

3.350

3.300

3.250

3.200

3.150

3.100

3.050

3.000

2.950

2.900

2.500

2.463

2.425

2.388

2.350

2.313

2.275

2.238

2.200

2.163

2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50

49.5/50.5 49/51

48.5/52.5

48/52

47.5/53.5

47/53

46.5/54.5

46/54

45.5/55.5

45/55

Clock Duty Cycle

---- -75 @

CK = 10ns

---- -8 @

CK = 10ns

---- -75 @

CK = 7.5ns

---- -8 @

CK = 8ns

n
l

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTES (continued)

33. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same
amount.

34.

HPmin is the lesser of

CL minimum and

minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.

35. READs and WRITEs with autoprecharge are not

allowed to be issued until

RAS(

MIN

) can be

satisfied prior to the internal precharge com-
mand being issued.

36. Any positive glitch must be less than

of the

clock cycle and not more than +400mV or 2.9
volts, whichever is less. Any negative glitch must
be less than

of the clock cycle and not exceed

either -300mV or 2.2 volts, whichever is more
positive.

37. Normal Output Drive Curves:

a) The full variation in driver pull-down current

from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figure A.

b )The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure A.

c) The full variation in driver pull-up current

from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figure B.

d )The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figure B.

e) The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between .71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0 Volt,
and at the same voltage and temperature.

f) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages from
0.1V to 1.0 volt.

38.Reduced Output Drive Curves:

a) The full variation in driver pull-down current

from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figure C.

b ) The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure C.

c) The full variation in driver pull-up current

from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figure D.

d ) The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figure D.

e) The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between .71 and 1.4 for device
drain-to-source voltages from 0.1V to 1.0 Volt,
and at the same voltage and temperature.

f) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages from
0.1V to 1.0 Volt.

Figure A

Pull-Down Characteristics

100

120

140

160

0.0

0.5

1.0

1.5

2.0

2.5

OUT

(V)

Figure B

Pull-Up Characteristics

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0.0

0.5

1.0

1.5

2.0

2.5

Q - V

OUT

(V)

OUT

)

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTES (continued)

39. The voltage levels used are derived from a

minimum V

level and the refernced test load.

In practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.

40. V

overshoot: V

(MAX) = V

Q+1.5V for a pulse

width

3ns and the pulse width can not be

greater than 1/3 of the cycle rate.
VIL undershoot: VIL(MIN) = -1.5V for a pulse
width

3ns and the pulse width can not be

greater than 1/3 of the cycle rate.

41. V

and V

DDQ

must track each other.

42. This maximum value is derived from the

referenced test load. In practice, the values
obtained in a typical terminated design may
reflect up to 310ps less for

HZmax and the last

DVW.

HZ(MAX) will prevail over

DQSCK(MAX) +

RPST(MAX) condition.

43. For slew rates greater than 1V/ns the (LZ)

transition will start about 310ps earlier.

LZ(MIN)

will prevail over a

DQSCK(MIN) +

RPRE(MAX)

condition.

44. During initialization, V

DDQ

, V

, and V

REF

must be

equal to or less than V

+ 0.3V. Alternatively, V

may be 1.35V maximum during power up, even if
V

DDQ

are 0 volts, provided a minimum of 42

ohms of series resistance is used between the V

supply and the input pin.

Figure C

Pull-Down Characteristics

0.0

0.5

1.0

1.5

2.0

2.5

OUT

(V)

OUT

(mA)

Figure D

Pull-Up Characteristics

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0.0

0.2

0.4

0.6

0.8

1.0

Q - V

OUT

(V)

OUT

)

45. The current Micron part operates below the

slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.

46. Reserved for future use.
47. Reserved for future use.
48. Random addressing changing 50% of data

changing at every transfer.

49. Random addressing changing 100% of data

changing at every transfer.

50. CKE must be active (high) during the entire time

a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge,
until

REF later.

51. IDD2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is "worst case."

52. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset,
and followed by 200 clock cycles.

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.

NORMAL OUTPUT DRIVE CHARACTERISTICS

PULL-DOWN CURRENT (mA)

PULL-UP CURRENT (mA)

VOLTAGE

NOMINAL

(V)

LOW

HIGH

MINIMUM MAXIMUM

LOW

HIGH

MINIMUM MAXIMUM

0.1

6.0

6.8

4.6

9.6

-6.1

-7.6

-4.6

-10.0

0.2

12.2

13.5

9.2

18.2

-12.2

-14.5

-9.2

-20.0

0.3

18.1

20.1

13.8

26.0

-18.1

-21.2

-13.8

-29.8

0.4

24.1

26.6

18.4

33.9

-24.0

-27.7

-18.4

-38.8

0.5

29.8

33.0

23.0

41.8

-29.8

-34.1

-23.0

-46.8

0.6

34.6

39.1

27.7

49.4

-34.3

-40.5

-27.7

-54.4

0.7

39.4

44.2

32.2

56.8

-38.1

-46.9

-32.2

-61.8

0.8

43.7

49.8

36.8

63.2

-41.1

-53.1

-36.0

-69.5

0.9

47.5

55.2

39.6

69.9

-43.8

-59.4

-38.2

-77.3

1.0

51.3

60.3

42.6

76.3

-46.0

-65.5

-38.7

-85.2

1.1

54.1

65.2

44.8

82.5

-47.8

-71.6

-39.0

-93.0

1.2

56.2

69.9

46.2

88.3

-49.2

-77.6

-39.2

-100.6

1.3

57.9

74.2

47.1

93.8

-50.0

-83.6

-39.4

-108.1

1.4

59.3

78.4

47.4

99.1

-50.5

-89.7

-39.6

-115.5

1.5

60.1

82.3

47.7

103.8

-50.7

-95.5

-39.9

-123.0

1.6

60.5

85.9

48.0

108.4

-51.0

-101.3

-40.1

-130.4

1.7

61.0

89.1

48.4

112.1

-51.1

-107.1

-40.2

-136.7

1.8

61.5

92.2

48.9

115.9

-51.3

-112.4

-40.3

-144.2

1.9

62.0

95.3

49.1

119.6

-51.5

-118.7

-40.4

-150.5

2.0

62.5

97.2

49.4

123.3

-51.6

-124.0

-40.5

-156.9

2.1

62.8

99.1

49.6

126.5

-51.8

-129.3

-40.6

-163.2

2.2

63.3

100.9

49.8

129.5

-52.0

-134.6

-40.7

-169.6

2.3

63.8

101.9

49.9

132.4

-52.2

-139.9

-40.8

-176.0

2.4

64.1

102.8

50.0

135.0

-52.3

-145.2

-40.9

-181.3

2.5

64.6

103.8

50.2

137.3

-52.5

-150.5

-41.0

-187.6

2.6

64.8

104.6

50.4

139.2

-52.7

-155.3

-41.1

-192.9

2.7

65.0

105.4

50.5

140.8

-52.8

-160.1

-41.2

-198.2

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.

REDUCED OUTPUT DRIVE CHARACTERISTICS

PULL-DOWN CURRENT (mA)

PULL-UP CURRENT (mA)

VOLTAGE NOMINAL NOMINAL

NOMINAL NOMINAL

(V)

LOW

HIGH

MINIMUM MAXIMUM

LOW

HIGH

MINIMUM MAXIMUM

0.1

3.4

3.8

2.6

5.0

-3.5

-4.3

-2.6

-5.0

0.2

6.9

7.6

5.2

9.9

-6.9

-7.8

-5.2

-9.9

0.3

10.3

11.4

7.8

14.6

-10.3

-12.0

-7.8

-14.6

0.4

13.6

15.1

10.4

19.2

-13.6

-15.7

-10.4

-19.2

0.5

16.9

18.7

13.0

23.6

-16.9

-19.3

-13.0

-23.6

0.6

19.9

22.1

15.7

28.0

-19.4

-22.9

-15.7

-28.0

0.7

22.3

25.0

18.2

32.2

-21.5

-26.5

-18.2

-32.2

0.8

24.7

28.2

20.8

35.8

-23.3

-30.1

-20.4

-35.8

0.9

26.9

31.3

22.4

39.5

-24.8

-33.6

-21.6

-39.5

1.0

29.0

34.1

24.1

43.2

-26.0

-37.1

-21.9

-43.2

1.1

30.6

36.9

25.4

46.7

-27.1

-40.3

-22.1

-46.7

1.2

31.8

39.5

26.2

50.0

-27.8

-43.1

-22.2

-50.0

1.3

32.8

42.0

26.6

53.1

-28.3

-45.8

-22.3

-53.1

1.4

33.5

44.4

26.8

56.1

-28.6

-48.4

-22.4

-56.1

1.5

34.0

46.6

27.0

58.7

-28.7

-50.7

-22.6

-58.7

1.6

34.3

48.6

27.2

61.4

-28.9

-52.9

-22.7

-61.4

1.7

34.5

50.5

27.4

63.5

-28.9

-55.0

-22.7

-63.5

1.8

34.8

52.2

27.7

65.6

-29.0

-56.8

-22.8

-65.6

1.9

35.1

53.9

27.8

67.7

-29.2

-58.7

-22.9

-67.7

2.0

35.4

55.0

28.0

69.8

-29.2

-60.0

-22.9

-69.8

2.1

35.6

56.1

28.1

71.6

-29.3

-61.2

-23.0

-71.6

2.2

35.8

57.1

28.2

73.3

-29.5

-62.4

-23.0

-73.3

2.3

36.1

57.7

28.3

74.9

-29.5

-63.1

-23.1

-74.9

2.4

36.3

58.2

28.3

76.4

-29.6

-63.8

-23.2

-76.4

2.5

36.5

58.7

28.4

77.7

-29.7

-64.4

-23.2

-77.7

2.6

36.7

59.2

28.5

78.8

-29.8

-65.1

-23.3

-78.8

2.7

36.8

59.6

28.6

79.7

-29.9

-65.8

-23.3

-79.7

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 29

x4, x8 Data Output Timing

DQSQ,

QH and Data Valid Window

DQ (Last data valid)

DQS

DQ (Last data valid)

DQ (First data no longer valid)

All DQs and DQS, collectively

NOTE:

1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an "early DQS,"

at T3 is a "nominal DQS," and at T3n is a "late DQS"
2. For a x4, only two DQs apply.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and
ends with the last valid transition of DQs .
4. tQH is derived from tHP : tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.

Earliest signal transition

Latest signal transition

T2n

T3n

CK#

T2n

T3n

tQH

tHP

tQH

tHP

tQH

tDQSQ

Data

Valid

window

Data

Valid

window

Data

Valid

window

Data

Valid

window

QFC#

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 29 A

x16 Data Output Timing

DQSQ,

QH and Data Valid Window

DQ (Last data valid)

LDQS

DQ (Last data valid)

DQ (First data no longer valid)

DQ0 - DQ7 and LDQS, collectively

NOTE: 1. DQs transitioning after DQS transition define tDQSQ
window. LDQS defines the lower byte and
UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not
cumulative over time and begins with DQS transition
and ends with the last valid transition of DQs .

T2n

T3n

CK#

T2n

T3n

tQH

tDQSQ

Data Valid

window

Data Valid

window

DQ (Last data valid)

UDQS

DQ (Last data valid)

DQ (First data no longer valid)

DQ8 - DQ15 and UDQS, collectively

T2n

T3n

tQH

tDQSQ

tHP

tQH

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition
collectively when a bank is active.
6. The data valid window is derived for each
DQS transition and is tQH minus tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

Upper Byte

Lower Byte

Data Valid

window

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 31

Data Input Timing

Figure 30

Data Output Timing -

AC and

DQSCK

CK#

DQS, or LDQS/UDQS

T2n

T3n

T4n

T5n

NOTE: 1. tDQSCK is the DQS output window relative to CK and is the"long term" component of DQS skew.
2. DQs transitioning after DQS transition define tDQSQ window.
3. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.
4. tAC is the DQ output window relative to CK, and is the"long term" component of DQ skew.
5. tLZ

(

MIN)

and tAC

(

MIN)

are the first valid signal transition.

6. tHZ

(

MAX

,and tAC

(

MAX)

are the latest valid signal transition.

7. READ command with CL = 2 issued at T0.

tRPST

tLZ

(MIN)

tDQSCK

(MAX)

tDQSCK

(MIN)

tDQSCK

(MAX)

tDQSCK

(MIN)

tHZ

(MAX)

tRPRE

DQ (Last data valid)

DQ (First data valid)

All DQs collectively

tAC

(MIN)

tAC

(MAX)

tLZ

(MIN)

tHZ

(MAX)

T2n

T3n

T4n

T5n

T2n

T3n

T4n

T5n

DQS

tDQSS

tDQSH tWPST

tDH

tDS

tDQSL

tDSS2 tDSH1

tDSH1

tDSS2

CK#

T1n

T2n

NOTE: 1. tDSH

(MIN)

generally occurs during tDQSS

(MIN)

2. tDSS

(MIN)

generally occurs during tDQSS

(MAX)

3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.

DON'T CARE

TRANSITIONING DATA

tWPRE

tWPRES

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

INITIALIZE AND LOAD MODE REGISTERS

VTD

CKE

LVCMOS
LOW LEVEL

BA0, BA1

200 cycles of CK

Load Extended

Mode Register

Load Mode

tMRD

tRP

tRFC

Power-up:
V

and

CK stable

T = 200µs

High-Z

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

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DQS

High-Z

A0-A9, A11, A12

A10

ALL BANKS

CK#

TT1

REF

COMMAND

LMR

NOP

PRE

LMR

(

)

(

)

(

)

(

)

ACT5

tIS

tIH

BA0 = H,

BA1 = L

tIS

tIH

BA0 = L,

BA1 = L

tIS

tIH

(

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(

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(

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CODE CODE

tIS

tIH

CODE CODE

(

)

(

)

(

)

(

)

PRE

ALL BANKS

tIS

tIH

NOTE:

1. V

is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. V

Q, V

and V

REF

must be equal to or less than V

+ 0.3V. Alternatively, V

may be 1.35V maximum during power up, even if

Q are 0 volts, provided a minimum of 42 ohms of series resistance is used between the V

supply and the input pin.

2. Although not required by the Micron device, JEDEC specifies resetting the DLL with A8 = H.
3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.
4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command,
RA = Row Address, Bank Address

(

)

(

)

(

)

(

)

Ta0

Tb0

Tc0

Td0

Te0

(

)

(

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(

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(

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(

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(

)

DON'T CARE

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tRP

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (2.5)

7.5

CK (2)

7.5

1.1

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

1.1

MRD

RFC

VTD

TIMING PARAMETERS

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

POWER-DOWN MODE

CK#

COMMAND

VALID1

NOP

ADDR

CKE

NOTE: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down. If this command is an ACTIVE (or if

at least one row is already active), then the power-down mode shown is active power-down.
2. No column accesses are allowed to be in progress at the time power-down is entered.

DQS

VALID

Enter 2

Power-Down

Mode

Exit

Power-Down

Mode

REFC

(

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(

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(

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(

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Ta0

Ta1

Ta2

NOP

DON'T CARE

(

)

(

)

(

)

(

)

VALID

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (2.5)

7.5

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

CK (2)

7.5

1.1

TIMING PARAMETERS

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

AUTO REFRESH MODE

CK#

COMMAND

NOP2

VALID

NOP 2

NOP2

PRE

CKE

A0-A9,

A11, A12

A10

BA0, BA1

Bank(s)3

NOTE: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.

2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
CKE must be active during clock positive transitions.
3. "Don't Care" if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e.,

must precharge all active banks).

4. DM, DQ, and DQS signals are all "Don't Care"/High-Z for operations shown.
5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back

AUTO REFRESH commands.

NOP2

AR5

NOP2

ACT

NOP2

ONE BANK

ALL BANKS

(

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DQS

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(

)

tRFC5

tRP

tRFC

Ta0

Tb0

Ta1

Tb1

Tb2

DON'T CARE

(

)

(

)

(

)

(

)

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (2.5)

7.5

CK (2)

7.5

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

1.1

RFC

TIMING PARAMETERS

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

SELF REFRESH MODE

CK#

COMMAND

NOP

ADDR

CKE

VALID

DQS

VALID

NOP

NOTE: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within

specifications by Ta0.

2. Device must be in the all banks idle state prior to entering self refresh mode.
3.

XSNR is required before any non-READ command can be applied, and

XSRD (200 cycles of CK)

is required before a READ command can be applied.

4. AR = AUTO REFRESH command.

tCK

tXSNR/
tXSRD

tIS

tIH

tIS

Enter Self Refresh Mode

Exit Self Refresh Mode

(

)

(

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(

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(

)

(

)

Tb0

Ta1

(

)

(

)

(

)

(

)

(

)

(

)

DON'T CARE

(

)

(

)

(

)

(

)

Ta0

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (2.5)

7.5

CK (2)

7.5

1.1

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

1.1

XSNR

XSRD

200

TIMING PARAMETERS

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

BANK READ WITHOUT AUTO PRECHARGE

CK#

CKE

A10

BA0, BA1

RCD

RAS7

CL = 2

T5n

T6n

DQS

Case 1:

(

MIN)

and

DQSCK

(

MIN)

Case 2:

(

MAX)

and

DQSCK

(

MAX)

DQS

RPRE

RPST

DQSCK

(

MIN)

DQSCK

(

MAX)

(

MIN)

(

MAX)

(

MIN)

(

MIN)

(

MAX)

(

MAX)

(

MAX)

NOP6

COMMAND

ACT

Col n

PRE

Bank x

Bank x4

ACT

Bank x

NOP6

(

MIN)

NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. "Don't Care" if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. The PRECHARGE command can only be applied at T5 if

RAS minimum is met.

8. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.

ONE BANK

ALL BANKS

DON'T CARE

TRANSITIONING DATA

x4: A0-A9, A11, A12

x8: A0-A11
x16: A0-A9

x8: A12

x16: A11, A12

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

BANK READ WITH AUTO PRECHARGE

CK#

CKE

A10

BA0, BA1

CL = 2

T5n

T6n

DQS

Case 1:

(MIN)

and

DQSCK

(MIN)

Case 2:

(MAX)

and

DQSCK

(MAX)

DQS

RPRE

RPST

DQSCK

(MIN)

DQSCK

(MAX)

(MIN)

(MAX)

NOP5

COMMAND

ACT

Col n

NOP5

Bank x

ACT

Bank x

NOP5

(MIN)

NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The READ command can only be applied at T3 if

RAP is satisfied at T3

7. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.

DON'T CARE

TRANSITIONING DATA

x4: A0-A9, A11,A12

x8: A0-A9, A11

x16: A0-A9

x8: A12

x16: A11, A12

RAS

(MIN)

(MAX)

RCD,

RAP6

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

BANK WRITE WITHOUT AUTO PRECHARGE

CK#

CKE

A10

BA0, BA1

RCD

RAS

T5n

T4n

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. "Don't Care" if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

. tDSH is applicable during tDQSS

(MIN)

and is referenced from CK T4 or T5.

. tDSS is applicable during tDQSS

(MAX)

and is referenced from CK T5 or T6.

NOP6

COMMAND

ACT

Col n

WRITE2

NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6

DQSL

DQSH

WPST

Bank x4

DQS

tDS

tDH

DON'T CARE

TRANSITIONING DATA

DQSS

(NOM)

WPRE

WPRES

x4: A0-A9, A11, A12

x8: A0-A9, A11

x16: A0-A9

x8: A12

x16: A11, A12

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (2.5)

7.5

CK (2)

7.5

0.5

0.6

0.5

0.6

DQSH

0.35

DQSL

0.35

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DSS

0.2

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

DSH

0.2

1.1

RAS

120,000

RCD

WPRE

0.25

WPRES

WPST

0.4

0.6

0.4

0.6

0.4

0.6

TIMING PARAMETERS

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

BANK WRITE WITH AUTO PRECHARGE

CK#

CKE

A10

BA0, BA1

tCL

RCD

RAS

T5n

T4n

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.

. tDSH is applicable during tDQSS

(

MIN)

and is referenced from CK T4 or T5.

. tDSS is applicable during tDQSS

(MAX)

and is referenced from CK T5 or T6.

NOP5

COMMAND

ACT

Col n

WRITE2

NOP5

Bank x

NOP5

Bank x

NOP5

DQSL

DQSH

WPST

DQS

DQSS

(NOM)

DON'T CARE

TRANSITIONING DATA

WPRES

WPRE

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8

x4: A12

x8: A11, A12

x16: A9, A11, A12

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (2.5)

7.5

CK (2)

7.5

0.5

0.6

0.5

0.6

DQSH

0.35

DQSL

0.35

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DSS

0.2

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

DSH

0.2

1.1

RAS

120,000

RCD

WPRE

0.25

WPRES

WPST

0.4

0.6

0.4

0.6

0.4

0.6

TIMING PARAMETERS

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

WRITE DM OPERATION

CK#

CKE

A10

BA0, BA1

RCD

RAS

tRP

tWR

T5n

T4n

. tDSH is applicable during tDQSS

(MIN)

and is referenced from CK T4 or T5.

. tDSS is applicable during tDQSS

(MAX)

and is referenced from CK T5 or T6.

NOP6

COMMAND

ACT

Col n

WRITE2

NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6

DQSL

DQSH

WPST

Bank x4

DQS

DON'T CARE

TRANSITIONING DATA

DQSS

(NOM)

WPRES

WPRE

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8

x4: A12

x8: A11, A12

x16: A9, A11, A12

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK (2.5)

7.5

CK (2)

7.5

0.5

0.6

0.5

0.6

DQSH

0.35

DQSL

0.35

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DSS

0.2

-75Z

-75

-8

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

DSH

0.2

1.1

RAS

120,000

RCD

WPRE

0.25

WPRES

WPST

0.4

0.6

0.4

0.6

0.4

0.6

TIMING PARAMETERS

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Document Outline

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