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Document Outline

Features
- Options
Table of Contents
List of Figures
List of Tables

09005aef80b12a05
256Mb_DDR2_1.fm - Rev. C 5/04 EN

256Mb: x4, x8, x16

DDR2 SDRAM

MT47H64M416 MEG X 4 X 4
MT47H32M88 MEG X 8 X 4
MT47H16M164 MEG X 16 X 4

For the latest data sheet, please refer to the Micron Web
site:

http://www.micron.com/datasheets

Features

· V

= +1.8V ±0.1V, V

Q = +1.8V ±0.1V

· JEDEC standard 1.8V I/O (SSTL_18-compatible)
· Differential data strobe (DQS, DQS#) option
· Four-bit prefetch architecture
· Duplicate output strobe (RDQS) option for x8

configuration

· DLL to align DQ and DQS transitions with CK
· Four internal banks for concurrent operation
· Programmable CAS Latency (CL): 3 and 4
· Posted CAS additive latency (AL): 0, 1, 2, 3, and 4
· WRITE latency = READ latency - 1

· Programmable burst lengths: 4 or 8
· Adjustable data-output drive strength
· 64ms, 8,192-cycle refresh
· On-die termination (ODT)

Options

Designation

· Configuration

64 Meg x 4 (16 Meg x 4 x 4)

64M4

32 Meg x 8 (8 Meg x 8 x 4)

32M8

16 Meg x 16 (4 Meg x 16 x 4)

16M16

· FBGA Package Lead-Free

x4x8
60-ball FBGA (8mm x 12mm)

x16
84-ball FBGA (8mm x 14)mm

· Timing Cycle Time

5.0ns @ CL = 4 (DDR2-400)

-5

5.0ns @ CL = 3 (DDR2-400)

-5E

3.75ns @ CL = 4 (DDR2-533)

-37E

ARCHITECTURE

64 MEG X 4

32 MEG X 8 16 MEG X 16

Configuration

16 Meg x 4 x 4

8 Meg x 8 x 4

4 Meg x 16 x 4

Refresh Count

Row Addressing

8K (A0-A12)

Bank Addressing

4 (BA0 - BA1)

Column
Addressing

2K (A0-A9, A11)

1K (A0-A9)

512K (A0-A8)

Table 1:

Key Timing Parameters

SPEED

GRADE

DATA RATE

(MHz)

RCD

(ns)

CL = 3

CL = 4

-5

400

-5E

400 400

-37E

400

533 15

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR2_256MbTOC.fm - Rev. C 5/04 EN

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Mode Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Write Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DQS# Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
RDQS Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
On Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Off-Chip Driver (OCD) Impedance Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Posted CAS Additive Latency (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Extended Mode Register 2 (EMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Extended Mode Register 3 (EMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Command Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
DESELECT, NOP, and LOAD MODE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
ACTIVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

SELF REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Precharge Power-Down Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
RESET Function (CKE LOW Anytime) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
ODT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR2_256MbTOC.fm - Rev. C 5/04 EN

AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Input Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Input Slew Rate Derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Power and Ground Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Output Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Full Strength Pull-Down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Full Strength Pull-Up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
FBGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
I

Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR2_256MbLOF.fm - Rev. C 5/04 EN

List of Figures

Figure 1:

256Mb DDR2 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 2:

84-ball FBGA Pin Assignment (x16), 8mm x 14mm (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 3:

60-Ball FBGA Pin Assignment (x 4, x 8), 8mm x 12mm (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 4:

Functional Block Diagram (64 Meg x 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 5:

Functional Block Diagram (32 Meg x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 6:

Functional Block Diagram (16 Meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 7:

DDR2 Power-Up and Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 8:

Mode Register (MR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 9:

CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 10:

Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 11:

READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 12:

Write Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 13:

Extended Mode Register 2 (EMR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 14:

Extended Mode Register 3 (EMR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 15:

ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 16:

READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 17:

Example: Meeting

RRD (MIN) and

RCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 18:

READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 19:

Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 20:

Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 21:

READ Interrupted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 22:

READ to PRECHARGE BL = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 23:

READ to PRECHARGE BL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 24:

READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 25:

Bank Read Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 26:

Bank Read With Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 27:

x4, x8 Data Output Timing

DQSQ,

QH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 28:

x16 Data Output Timing

DQSQ,

QH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 29:

Data Output Timing

AC and

DQSCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 30:

WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 31:

WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 32:

Consecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 33:

Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 34:

Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 35:

WRITE Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 36:

WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 37:

WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 38:

Bank WriteWithout Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 39:

Bank Writewith Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 40:

WRITEDM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 41:

Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 42:

PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 43:

Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 44:

Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 45:

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 46:

READ to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 47:

READ with Auto Precharge to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 48:

WRITE to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 49:

WRITE with Auto Precharge to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 50:

REFRESH command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 51:

ACTIVE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 52:

PRECHARGE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 53:

LOAD MODE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 54:

Input Clock Frequency Change During PRECHARGE Power Down Mode . . . . . . . . . . . . . . . . . . . . . .65

Figure 55:

RESET Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 56:

ODT Timing for Active or "Fast-Exit" Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR2_256MbLOF.fm - Rev. C 5/04 EN

Figure 57:

ODT timing for "Slow-Exit" or Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 58:

ODT "Turn Off" Timings when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 59:

ODT "Turn-On" Timing when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 60:

ODT "Turn-Off" Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 61:

ODT "Turn On" Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 62:

Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 63:

Single-Ended Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 64:

Differential Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Figure 65:

Nominal Slew Rate for

IS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 66:

Tangent Line for

IS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 67:

Nominal Slew Rate for

IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Figure 68:

Tangent Line for

IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Figure 69:

AC Input Test Signal Waveform Command/Address pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 70:

AC Input Test Signal Waveform for Data with DQS,DQS# (differential) . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 71:

AC Input Test Signal Waveform for Data with DQS (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 72:

AC Input Test Signal Waveform (differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 73:

Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 74:

Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Figure 75:

Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Figure 76:

Differential Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Figure 77:

Output Slew Rate Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Figure 78:

Full Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Figure 79:

Full Strength Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Figure 80:

Package Drawing 60-Ball (8mmx12mm) FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 81:

Package Drawing 84-Ball (8mmx14mm) FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR2_256MbLOT.fm - Rev. C 5/04 EN

List of Tables

Table 1:

Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2:

FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 3:

Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 4:

Truth Table DDR2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 5:

Truth Table Current State Bank n - Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 6:

Truth Table Current State Bank n - Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 7:

READ Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 8:

WRITE Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 9:

CKE Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 10:

ODT Timing for Active and "Fast-Exit" Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 11:

ODT timing for "Slow-Exit" and Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 12:

ODT "Turn Off" Timings when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 13:

ODT "Turn-On" Timing when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 14:

ODT "Turn-Of" Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 15:

ODT "Turn On" Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 16:

Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 17:

Recommended DC Operating Conditions (SSTL_18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 18:

ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 19:

Input DC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 20:

Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 21:

Differential Input Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 22:

AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 23:

Setup and Hold Time Derating Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 24:

Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 25:

Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 26:

Clock, Data, Strobe, and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 27:

Differential AC Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 28:

Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 29:

Output Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 30:

Pulldown Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 31:

Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 32:

Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 33:

DDR2 I

Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 34:

General I

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 35:

7 Timing Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Table 36:

AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Part Numbers

Figure 1: 256Mb DDR2 Part Numbers

NOTE:

Not all speeds and configurations are avail-
able.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged compo-

nents have an abbreviated part marking that is differ-
ent from the part number. Micron's new FBGA Part
Marking Decoder makes it easier to understand that
part marking. Visit the web site at

www.micron.com/

decoder

General Description

The 256Mb DDR2 SDRAM is a high-speed, CMOS

dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-
bank DRAM. The functional block diagrams of the 16
Meg x 16, 32 Meg x 8, and 64 Meg x 4 devices, respec-
tively are shown in the Functional Description section.
Ball assignments for the 64 Meg x 4 are shown in
Figure 2 and signal descriptions are shown in Table 1.
Ball assignments for the 32 Meg x 8 and 64 Meg x 4 are
shown in Figure 2 and signal descriptions are shown in
Table 2.

The 256Mb DDR2 SDRAM uses a double data rate

architecture to achieve high-speed operation. The
double data rate architecture is essentially a 4n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 256Mb DDR2
SDRAM effectively consists of a single 4n-bit-wide,
one-clock-cycle data transfer at the internal DRAM
core and four corresponding n-bit-wide, one-half-
clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) is transmit-

ted externally, along with data, for use in data capture
at the receiver. DQS is a strobe transmitted by the
DDR2 SDRAM during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data
for READs and center-aligned with data for WRITEs.
The x16 offering has two data strobes, one for the lower
byte (LDQS, LDQS#) and one for the upper byte
(UDQS, UDQS#).

The 256Mb DDR2 SDRAM operates from a differen-

tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.

Read and write accesses to the DDR2 SDRAM are

burst-oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed.
The address bits registered coincident with the READ
or WRITE command are used to select the bank and
the starting column location for the burst access.

The DDR2 SDRAM provides for programmable read

or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight
with another read, or a burst write of eight with
another write. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst access.

As with standard DDR SDRAMs, the pipelined,

multibank architecture of DDR2 SDRAMs allows for
concurrent operation, thereby providing high, effec-
tive bandwidth by hiding row precharge and activation
time.

A self refresh mode is provided, along with a power-

saving power-down mode.

All inputs are compatible with the JEDEC standard

for SSTL_18. All full drive-strength outputs are
SSTL_18-compatible.

NOTE: 1. The functionality and the timing specifica-

tions discussed in this data sheet are for the
DLL-enabled mode of operation.

2. Throughout the data sheet, the various fig-

ures and text refer to DQs as "DQ." The DQ
term is to be interpreted as any and all DQ

Configuration

MT47H

Package

Speed

Configuration

64 Meg x 4

32 Meg x 8

16 Meg x 16

64M4

32M8

16M16

Package

60-Ball 8 x 12 FBGA Lead-free

84-Ball 8 x 14 FBGA Lead-free

Speed Grade

tCK = 5ns, CL = 4

tCK = 5ns, CL = 3

tCK = 3.75ns, CL = 4

-5

-5E

-37E

Example Part Number: MT47H64M4FT-37E

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

collectively, unless specifically stated other-
wise. Additionally, the x16 is divided into
two bytes, the lower byte and upper byte.
For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS. For
the upper byte (DQ8 through DQ15) DM
refers to UDM and DQS refers to UDQS.

3. Complete functionality is described

throughout the document and any page or
diagram may have been simplified to con-
vey a topic and may not be inclusive of all
requirements.

4. Any specific requirement takes precedence

over a general statement.

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 2: 84-ball FBGA Pin Assignment

(x16), 8mm x 14mm (Top View)

Figure 3: 60-Ball FBGA Pin Assignment

(x 4, x 8), 8mm x 12mm (Top View)

DQ14

DQ12

DQ6

DQ4

RFU

DQ9

DQ1

VREF

CKE

BA0

A10

A12

UDM

DQ11

LDM

DQ3

WE#

BA1

RFU

UDQS

DQ10

LDQS

DQ2

RAS#

CAS#

A11

RFU

DQ15

DQ13

DQ7

DQ5

ODT

NU/UDQS#

DQ8

NU/LDQS#

DQ0

CK#

CS#

RFU

NF,DQ6

NF,DQ4

RFU

NC,NU/RDQS#

DQ1

VREF

CKE

BA0

A10

A12

NU/DQS#

DQ0

CK#

CS#

RFU

DM,DM/RDQS

DQ3

WE#

BA1

RFU

DQS

DQ2

RAS#

CAS#

A11

RFU

NF,DQ7

NF,DQ5

ODT

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Table 2:

FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16

x16 FBGA

BALL

ASSIGNMENT

x4, x8 FBGA

BALL

ASSIGNMENT SYMBOL

TYPE

DESCRIPTION

ODT

Input

On-Die Termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following pins: DQ0DQ15, LDM, UDM,
LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0-DQ7, DQS, DQS#,
RDQS, RDQS#, and DM for the x8; DQ0-DQ3, DQS, DQS#, and DM
for the x4. The ODT input will be ignored if disabled via the LOAD
MODE command.

J8, K8

E8, F8

CK, CK#

Input

Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and DQS/
DQS#) is referenced to the crossings of CK and CK#.

CKE

Input

Clock Enable: CKE (registered HIGH) activates and CKE (registered
LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the DDR2
SDRAM configuration and operating mode. CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is
synchronous for POWER-DOWN entry, POWER-DOWN exit, output
disable, and for SELF REFRESH entry. CKE is asynchronous for SELF
REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE) are
disabled during SELF REFRESH. CKE is an SSTL_18 input but will
detect a LVCMOS LOW level once Vdd is applied during first power-
up. After Vref has become stable during the power on and
initialization sequence, it must be maintained for proper operation
of the CKE receiver. For proper self-refresh operation V

REF

must be

maintained.

CS#

Input

Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS#
is registered HIGH. CS# provides for external bank selection on
systems with multiple ranks. CS# is considered part of the command
code.

K7, L7, K3

F7, G7, F3

RAS#,
CAS#,

WE#

Input

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.

F3, B3

LDM,
UDM

Input

Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins. LDM is DM for lower byte DQ0
DQ7 and UDM is DM for upper byte DQ8DQ15.

L2, L3

G2, G3

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0 and
BA1 define which mode register including MR, EMR, EMR(2), and
EMR(3) is loaded during the LOAD MODE command.

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

M8, M3, M7,

N2, N8, N3,

N7, P2, P8, P3,

M2, P7, R2

H8, H3, H7, J2,

J8, J3, J7, K2,

K8, K3, H2, K7,

A0A12

Input

Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for Read/Write
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
command.

G8, G2, H7,

H3, H1, H9, F1,

F9, C8, C2, D7,

D3, D1, D9, B1,

DQ0

DQ15

I/O

Data Input/Output: Bidirectional data bus for 16 Meg x 16.

C8, C2, D7, D3,

D1, D9, B1, B9

DQ0DQ7

I/O

Data Input/Output: Bidirectional data bus for 32 Meg x 8.

C8, C2, D7, D3 DQ0DQ3

I/O

Data Input/Output: Bidirectional data bus for 64 Meg x 4.

B7, A8

UDQS,

UDQS#

I/O

Data Strobe for Upper Byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. UDQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.

F7, E8

LDQS,

LDQS#

I/O

Data Strobe for Lower Byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. LDQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.

B7, A8

DQS,

DQS#

I/O

Data Strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data, center
aligned with write data. DQS# is only used when differential data
strobe mode is enabled via the LOAD MODE command.

B3, A2

RDQS,

RDQS#

Output

Redundant Data Strobe for 32 Meg x 8 only. RDQS is enabled/
disabled via the LOAD MODE command to the Extended Mode
Register (EMR). When RDQS is enabled, RDQS is output with read
data only and is ignored during write data. When RDQS is disabled,
pin B3 becomes Data Mask (see DM pin). RDQS# is only used when
RDQS is enabled AND differential data strobe mode is enabled.

A1, E1, J9, M9,

A1, E9, H9, L1

Supply

Power Supply: 1.8V ±0.1V

Supply

DLL Power Supply: 1.8V ±0.1V

A9, C1, C3, C7,
C9, E9, G1, G3,

G7, G9

A9, C1, C3, C7,

Supply DQ Power Supply: 1.8V ±0.1V. Isolated on the device for improved

noise immunity.

REF

Supply

SSTL_18 reference voltage.

A3, E3, J3, N1,

A3, E3, J1, K9

Supply

Ground.

Supply

DLL Ground. Isolated on the device from V

and V

A7, B2, B8, D2,

D8, E7, F2, F8,

H2, H8,

A7, B2, B8, D2,

Supply DQ Ground. Isolated on the device for improved noise immunity.

Table 2:

FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16

x16 FBGA

BALL

ASSIGNMENT

x4, x8 FBGA

BALL

ASSIGNMENT SYMBOL

TYPE

DESCRIPTION

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

A2, E2

A2, B1, B9, D1,

No Connect: These pins should be left unconnected.

D1, D9, B1, B9

No Function: These pins are used as DQ4-DQ7 on the 32 Meg x 8,
but are NF (No Function) on the 16 Meg x 16 configuration.

A8, E8

A2, A8

Not Used: If EMR[E10] = 0, A8 and E8 are UDQS# and LDQS#.
If EMR[E10] = 1, then A8 and E8 are Not Used.

L1, R3, R7, R8

G1, L3, L7, L8

RFU

Reserved for Future Use; Bank address bit BA2(L1) for 1Gb, 2Gb, and
4Gb densities. Row address bits A13(R8), A14(R3) and A15(R7) for
higher densities.

Table 2:

FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16

x16 FBGA

BALL

ASSIGNMENT

x4, x8 FBGA

BALL

ASSIGNMENT SYMBOL

TYPE

DESCRIPTION

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Functional Description

The 256Mb DDR2 SDRAM is a high-speed, CMOS

dynamic random-access memory containing
268,435,456 bits. The 256Mb DDR2 SDRAM is inter-
nally configured as a four-bank DRAM.

The 256Mb DDR2 SDRAM uses a double data rate

architecture to achieve high-speed operation. The
DDR2 architecture is essentially a 4n-prefetch archi-
tecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or

write access for the 256Mb DDR2 SDRAM consists of a
single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and four corresponding n-bit-
wide, one-half-clock-cycle data transfers at the I/O
pins.

Prior to normal operation, the DDR2 SDRAM must

be initialized. The following sections provide detailed
information covering device initialization, register def-
inition, command descriptions, and device operation.

Figure 4: Functional Block Diagram (64 Meg x 4)

RAS#

CAS#

ROW-

ADDRESS

MUX

CS#

WE#

CK#

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTERS

COMMAND

DECODE

A0-A12,

BA0, BA1

CKE

ADDRESS
REGISTER

512

(x16)

8,192

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 512 x 16)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8,192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

RCVRS

CK OUT

DATA

DQS, DQS#

CK, CK#

COL0,COL1

CK IN

DRVRS

DLL

MUX

DQS

GENERATOR

DQ0 - DQ3

DQS, DQS#

READ

LATCH

WRITE

FIFO

DRIVERS

DATA

MASK

BANK1

BANK2

BANK3

INPUT

REGISTERS

VDDQ

sw1

sw2

VssQ

sw1

sw2

sw1

sw2

ODT

sw1

sw2

ODT CONTROL

Internal
CK, CK#

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 5: Functional Block Diagram (32 Meg x 8)

Figure 6: Functional Block Diagram (16 Meg x 16)

ROW-

ADDRESS

MUX

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTERS

COMMAND

DECODE

0A12,

0, BA1

ADDRESS
REGISTER

256

(x32)

8,192

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 256 x 32)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8,192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

RCVRS

CK OUT

DATA

DQS, DQS#

internal
CK, CK#

CK,CK#

COL0,COL1

CK IN

DRVRS

DLL

MUX

DQS

GENERATOR

DQ0DQ7

DQS, DQS#

READ

LATCH

WRITE

FIFO

DRIVERS

DATA

MASK

BANK1

BANK2

BANK3

INPUT

REGISTERS

RDQS#

sw1

sw2

VssQ

sw1

sw2

sw1

sw2

sw1

sw2

ODT CONTROL

RAS#

CAS#

CS#

WE#

CK#

CKE

ODT

RDQS

ROW-

ADDRESS

MUX

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTERS

A0A12,

BA0, BA1

ADDRESS
REGISTER

128

(x64)

8,192

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 128 x 64)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8,192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

RCVRS

CK OUT

DATA

UDQS, UDQS#
LDQS, LDQS#

Internal
CK, CK#

CK,CK#

COL0,COL1

CK IN

DLL

MUX

DQS

GENERATOR

UDQS, UDQS#
LDQS, LDQS#

READ

LATCH

WRITE

FIFO

DRIVERS

DATA

MASK

BANK1

BANK2

BANK3

INPUT

REGISTERS

UDM, LDM

DQ0DQ15

sw1

sw2

VssQ

sw1

sw2

sw1

sw2

sw1

sw2

ODT CONTROL

RAS#

CAS#

CS#

WE#

CK#

COMMAND

DECODE

CKE

ODT

DRVRS

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Initialization

The following sequence is required for power-up

and initialization and is shown in Figure 7.

1. Apply power; if CKE is maintained below 0.2*

Q, outputs remain disabled. To guarantee R

(ODT Resistance) is off, V

REF

must be valid and a

low level must be applied to the ODT pin (all other
inputs may be undefined). At least one of the fol-
lowing two sets of conditions (A or B) must be
met:

. C

ONDITION

· V

, V

L and V

Q are driven from a single

power converter output

· V

is limited to 0.95V MAX

· V

REF

tracks V

Q/2.

. C

ONDITION

· Apply V

before or at the same time as V

· Apply V

L before or at the same time as V

· Apply V

Q before or at the same time as V

and V

REF

2. For a minimum of 200µs after stable power and

clock (CK, CK#), apply NOP or DESELECT com-
mands and take CKE HIGH.

3. Wait a minimum of 400ns, then issue a PRE-

CHARGE ALL command.

4. Issue an LOAD MODE command to the EMR(2)

5. Issue a LOAD MODE command to the EMR(3)

6. Issue an LOAD MODE command to the EMR reg-

ister to enable DLL. To issue a DLL ENABLE com-
mand, provide LOW to BA1 and A0, provide HIGH
to BA0. Bits E7, E8, and E9 must all be set to 0.

7. Issue a LOAD MODE command for DLL Reset.

200 cycles of clock input is required to lock the
DLL. (To issue a DLL Reset, provide HIGH to A8
and provide LOW to BA1 and BA0.) CKE must be
HIGH the entire time.

8. Issue PRECHARGE ALL command.
9. Issue two or more REFRESH commands.

10. Issue a LOAD MODE command with LOW to A8 to

initialize device operation (i.e., to program oper-
ating parameters without resetting the DLL).

11. Issue a LOAD MODE command to the EMR to

enable OCD default by setting Bits E7, E8, and E9
to 1 and set all other desired parameters.

12. Issue a LOAD MODE command to the EMR to

enable OCD exit by setting Bits E7, E8, and E9 to 0
and set all other desired parameters.

13. The DDR2 SDRAM is now intialized and ready for

normal operation 200 clocks after DLL Reset in
step 7.

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 7: DDR2 Power-Up and Initialization

NOTE:

1. V

is not applied directly to the device; however,

VTD should be greater than or equal to zero to avoid device latch-up.

One of the following two conditions (a or b) MUST be met:

a) V

, V

L, and V

Q are driven from a single power converter output.

may be 0.95V maximum during power up.

REF

tracks V

Q/2.

b) Apply V

before or at the same time as V

Apply V

L before or at the same time as V

Apply V

Q before or at the same time as V

and V

REF

2. Either a NOP or DESELECT command may be applied.
3. 200 cycles of clock (CK, CK#) are required before a READ command can be issued. CKE must be HIGH the entire time.
4. Two or more REFRESH commands are required.
5. Bits E7, E8, and E9 must all be set to 0 with all other operating parameters of EMRS set as required.
6. PRE = PRECHARGE command, LM = LOAD MODE command, REF = REFRESH command, ACT = ACTIVE command, RA =

Row Address, BA = Bank Address.

7. DM represents DM for x4, x8 configuration and UDM, LDM for x16 configuration. DQS represents DQS, DQS#, UDQS,

UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate configuration (x4, x8, x16). DQ represents DQ0DQ3 for x4,
DQ0DQ7 for x8, and DQ0DQ15 for x16.

8. CKE pin uses LVCMOS input levels prior to state T0. After state T0, CKE pin uses SSTL_18 input levels.
9. The LM command for EMR(2) and EMR(3) may be before or after LM command for MR (Tf0) and EMR (Te0).

10. ADDRESS represents A12-A0 for x4, x8, and A12-A0 for x16, BA0-BA1. A10 should be HIGH at states Tb0 and Tg0 to

ensure a PRECHARGE (all banks) command is issued.

11. Bits E7, E8, and E9 must be set to 1 to set OCD default.
12. Bits E7, E8, and E9 must be set to 0 to set OCD exit and all other operating parameters of EMRS set as required.

VTD

CKE

Rtt

Power-up:
V

and stable

clock (CK, CK#)

T = 200µs (min)

High-Z

DQS

High-Z

ADDRESS

CK#

TT1

REF

DDL

COMMAND

NOP2

PRE

Ta0

DON'T CARE

ODT

High-Z

T = 400ns (min)

Tb0

200 cycles of CK

EMR with

DLL Enable

MR with

DLL Reset

tMRD

tRFC

CODE

PRE

LM5

REF4

CODE

Tg0

Th0

Ti0

Tj0

MR w/o

DLL Resett

EMR with

OCD Default

tMRD

Tk0

Tl0

Tm0

Te0

Tf0

EMR(2)

EMR(3)

tMRD

LM9

CODE

RPA

Tc0

Td0

LVCMOS

LOW LEVEL

SSTL_18

LOW LEVEL

VALID3

VALID

Indicates a break in
time scale

RPA

CODE

EMR with

OCD Exit

CODE

Normal

Operation

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Mode Register (MR)

The mode register is used to define the specific

mode of operation of the DDR2 SDRAM. This defini-
tion includes the selection of a burst length, burst type,
CAS latency, operating mode, DLL reset, write recov-
ery, and power-down mode as shown in Figure 8. Con-
tents of the mode register can be altered by re-
executing the LOAD MODE (LM) command. If the
user chooses to modify only a subset of the MR vari-
ables, all variables (M0M14) must be programmed
when the LOAD MODE command is issued.

The mode register is programmed via the LM com-

mand (bits BA1-BA0 = 0, 0) and other bits (M12 - M0)
will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit M8, which is self-clearing). Reprogramming the
mode register will not alter the contents of the mem-
ory array, provided it is performed correctly.

The LOAD MODE command can only be issued (or

reissued) when all banks are in the precharged state.
The controller must wait the specified time

MRD

before initiating any subsequent operations such as an
ACTIVE command. Violating either of these require-
ments will result in unspecified operation.

Burst Length

Burst length is defined by bits M0M3 as shown in

Figure 8. Read and write accesses to the DDR2 SDRAM
are burst-oriented, with the burst length being pro-
grammable to either four or eight. The burst length
determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE
command.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A2Ai when the burst length is set to four
and by A3Ai when the burst length is set to eight
(where Ai is the most significant column address bit for
a given configuration). The remaining (least signifi-

cant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst
length applies to both READ and WRITE bursts.

Figure 8: Mode Register (MR)

Definition

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved. The burst type is
selected via bit M3 as shown in Figure 8. The ordering
of accesses within a burst is determined by the burst
length, the burst type, and the starting column address
as shown in Table 3. DDR2 SDRAM supports 4-bit
burst and 8-bit burst modes only. For 8-bit burst mode,
full interleave address ordering is supported; however,
sequential address ordering is nibble-based.

Burst Length

CAS# Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

A10

A12 A11

BA0

BA1

Burst Length

Reserved

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Mode

Normal

Test

DLL TM

DLL Reset

Yes

Write Recovery

Reserved

M10

M11

Mode Register

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

M14

PD Mode

Fast Exit

(Normal)

Slow Exit

(Low Power)

M12

M13

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Operating Mode

The normal operating mode is selected by issuing a

LOAD MODE command with bit M7 set to zero, and all
other bits set to the desired values as shown in
Figure 8. When bit M7 is `1,' no other bits of the mode
register are programmed. Programming bit M7 to `1'
places the DDR2 SDRAM into a test mode that is only
used by the Manufacturer and should NOT be used. No
operation or functionality is guaranteed if M7 bit is `1.'

DLL Reset

DLL reset is defined by bit M8 as shown in Figure 8.

Programming bit M8 to `1' will activate the DLL RESET
function. Bit M8 is self-clearing, meaning it returns
back to a value of `0' after the DLL RESET function has
been issued.

Anytime the DLL RESET function is used, 200 clock

cycles must occur before a READ command can be
issued to allow time for the internal clock to be syn-
chronized with the external clock. Failing to wait for
synchronization to occur may result in a violation of
the

AC or

DQSCK parameters.

Write Recovery

Write recovery (WR) time is defined by bits M9M11

as shown in Figure 8. The WR Register is used by the
DDR2 SDRAM during WRITE /w AUTO PRECHARGE
operation. During WRITE /w AUTO PRECHARGE
operation, the DDR2 SDRAM delays the internal AUTO
PRECHARGE operation by WR clocks (programmed in

bits M9-M11) from the last data burst. An example of
Write /w AUTO PRECHARGE is shown in Figure 26 on
page 30.

Write Recovery (WR) values of 2, 3, 4, 5, or 6 clocks

may be used for programming bits M9M11. The user
is required to program the value of write recovery,
which is calculated by dividing

WR (in ns) by

CK (in

ns) and rounding up a noninteger value to the next
integer; WR [cycles] =

WR [ns] /

CK [ns]. Reserved

states should not be used as unknown operation or
incompatibility with future versions may result.

Power-Down Mode

Active power-down (PD) mode is defined by bit M12

as shown in Figure 8. PD mode allows the user to
determine the active power-down mode, which deter-
mines performance vs. power savings. PD mode bit
M12 does not apply to precharge power-down mode.

When bit M12 = 0, standard Active Power-down

mode or `fast-exit' active power-down mode is
enabled. The

XARD parameter is used for `fast-exit'

active power-down exit timing. The DLL is expected to
be enabled and running during this mode.

When bit M12 = 1, a lower power active power-down

mode or `slow-exit' active power-down mode is
enabled. The

XARDS parameter is used for `slow-exit'

active power-down exit timing. The DLL can be
enabled, but `frozen' during active power-down mode
since the exit-to-READ command timing is relaxed.
The power difference expected between PD `normal'
and PD `low-power' mode is defined in the I

table.

CAS Latency (CL)

The CAS Latency (CL) is defined by bits M4M6 as

shown in Figure 8. CAS Latency is the delay, in clock
cycles, between the registration of a READ command
and the availability of the first bit of output data. The
CAS Latency can be set to 3 or 4 clocks. CAS Latency of
2 or 5 clocks are JEDEC optional features and may be
enabled in future speed grades. DDR2 SDRAM does
not support any half clock latencies. Reserved states
should not be used as unknown operation or incom-
patibility with future versions may result.

DDR2 SDRAM also supports a feature called Posted

CAS additive latency (AL). This feature allows the
READ command to be issued prior to

RCD(MIN) by

delaying the internal command to the DDR2 SDRAM
by AL clocks. The AL feature is described in more detail
in the Extended Mode Register (EMR) and Operational
sections.

Table 3:

Burst Definition

BURST

LENGTH

STARTING

COLUMN

ADDRESS

(A2, A1,

A0)

ORDER OF ACCESSES WITHIN

A BURST

BURST TYPE =

SEQUENTIAL

BURST TYPE =

INTERLEAVED

0 0 0

0,1,2,3

0 0 1

1,2,3,0

1,0,3,2

0 1 0

2,3,0,1

0 1 1

3,0,1,2

3,2,1,0

0 0 0

0,1,2,3,4,5,6,7

0 0 1

1,2,3,0,5,6,7,4

1,0,3,2,5,4,7,6

0 1 0

2,3,0,1,6,7,4,5

0 1 1

3,0,1,2,7,4,5,6

3,2,1,0,7,6,5,4

1 0 0

4,5,6,7,0,1,2,3

1 0 1

5,6,7,4,1,2,3,0

5,4,7,6,1,0,3,2

1 1 0

6,7,4,5,2,3,0,1

1 1 1

7,4,5,6,3,0,1,2

7,6,5,4,3,2,1,0

256Mb: x4, x8, x16

DDR2 SDRAM

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Examples of CL = 3 and CL = 4 are shown in Figure 9;

both assume AL = 0. If a READ command is registered
at clock edge n, and the CAS Latency is m clocks, the
data will be available nominally coincident with clock
edge n + m (this assumes AL = 0).

Figure 9: CAS Latency (CL)

OUT

n + 3

OUT

n + 2

OUT

n + 1

CK#

COMMAND

DQS, DQS#

CL = 3 (AL = 0)

READ

Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal tAC, tDQSCK, and tDQSQ

DON'T CARE

TRANSITIONING DATA

NOP

OUT

NOP

OUT

n + 3

OUT

n + 2

OUT

n + 1

CK#

COMMAND

DQS, DQS#

CL = 4 (AL = 0)

READ

NOP

OUT

NOP

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DDR2 SDRAM

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Extended Mode Register (EMR)

The extended mode register controls functions

beyond those controlled by the mode register; these
additional functions are DLL enable/disable, output
drive strength, ODT (R

), Posted CAS additive latency

(AL), off-chip driver impedance calibration (OCD),
DQS# enable/disable, RDQS/RDQS# enable/disable,
and OUTPUT disable/enable. These functions are
controlled via the bits shown in Figure 10. The
extended mode register is programmed via the LOAD
MODE (LM) command and will retain the stored infor-
mation until it is programmed again or the device
loses power. Reprogramming the extended mode reg-
ister will not alter the contents of the memory array,
provided it is performed correctly.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the
controller must wait the specified time

MRD before

initiating any subsequent operation. Violating either of
these requirements could result in unspecified opera-
tion.

Figure 10: Extended Mode Register

Definition

DLL Enable/Disable

The DLL may be enabled or disabled by program-

ming bit E0 during the LOAD MODE command as
shown in Figure 10. The DLL must be enabled for nor-
mal operation. DLL enable is required during power-
up initialization and upon returning to normal opera-
tion after having disabled the DLL for the purpose of
debugging or evaluation. Enabling the DLL should
always be followed by resetting the DLL using a LOAD
MODE command.

The DLL is automatically disabled when entering

self refresh operation and is automatically re-enabled
and reset upon exit of self refresh operation.

Any time the DLL is enabled (and subsequently

reset), 200 clock cycles must occur before a READ
command can be issued to allow time for the internal
clock to be synchronized with the external clock. Fail-
ing to wait for synchronization to occur may result in a
violation of the

AC or

DQSCK parameters.

Output Drive Strength

The output drive strength is defined by bit E1 as

shown in Figure 10. The normal drive strength for all
outputs are specified to be SSTL_18. Programming bit
E1 = 0 selects normal (100 percent) drive strength for
all outputs. Selecting a reduced drive strength option
(bit E1 = 1) will reduce all outputs to approximately 60
percent of the SSTL_18 drive strength. This option is
intended for the support of the lighter load and/or
point-to-point environments.

DQS# Enable/Disable

The DQS# enable function is defined by bit E10.

When enabled (bit E10 = 0), DQS# is the complement
of the differential data strobe pair DQS/DQS#. When
disabled (bit E10 = 1), DQS is used in a single-ended
mode and the DQS# pin is disabled. This function is
also used to enable/disable RDQS#. If RDQS is enabled
(E11 = 1) and DQS# is enabled (E10 = 0), then both
DQS# and RDQS# will be enabled.

RDQS Enable/Disable

The RDQS enable function is defined by bit E11 as

shown in Figure 10. This feature is only applicable to
the x8 configuration. When enabled (E11 = 1), RDQS is
identical in function and timing to data strobe DQS
during a READ. During a WRITE operation, RDQS is
ignored by the DDR2 SDRAM.

DLL

Posted CAS# R

out

A7 A6 A5 A4 A3

A1 A0

Extended Mode

Address Bus

A10

A12 A11

BA0

BA1

Output Drive Strength

100%

60%

Posted CAS# Additive Latency (AL)

Reserved

DLL Enable

Enable (Normal)

Disable (Test/Debug)

RDQS Enable

Yes

E11

OCD Program

ODS

DQS#

DQS# Enable

Enable

Disable

E10

RDQS

(nominal)

Disabled

75 ohm

150 ohm

Reserved

Outputs

Enabled

Disabled

E12

Mode Register

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

M14

M13

EMR

OCD Operation

OCD Exit

Reserved

OCD Default

256Mb: x4, x8, x16

DDR2 SDRAM

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Output Enable/Disable

The OUTPUT enable function is defined by bit E12

as shown in Figure 10. When enabled (E12 = 0), all out-
puts (DQs, DQS, DQS#, RDQS, RDQS#) function nor-
mally. When disabled (E12 = 1), all DDR2 SDRAM
outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled
removing output buffer current. The OUTPUT disable
feature is intended to be used during I

characteriza-

tion of read current.

On Die Termination (ODT)

ODT effective resistance R

(

EFF

) is defined by bits

E2 and E6 of the EMR as shown in Figure 10. The ODT
feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM con-
troller to independently turn on/off ODT for any or all
devices. R

effective resistance values of 75 and

150 are selectable and apply to each DQ, DQS/DQS#,
RDQS/RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM,
and UDM/LDM signals. A functional representation of
ODT is shown in block diagrams in "Functional
Description" on page 13. Bits (E6, E2) determine what
ODT resistance is enabled by turning on/off `sw1' or

`sw2'. The ODT effective resistance value is selected by
enabling switch `sw1,' which enables all `R1' values
that are 150 each, enabling an effective resistance of
75 (

EFF

)

= `R1' / 2). Similarly, if `sw2' is enabled,

all `R2' values that are 300 each, enable an effective
ODT resistance of 150 (

EFF

)

= `R2'/2). Reserved

states should not be used, as unknown operation or
incompatibility with future versions may result.

The ODT control pin is used to determine when

(

EFF

) is turned on and off, assuming ODT has been

enabled via bits E2 and E6 of the EMR. The ODT fea-
ture and ODT input pin are only used during active,
active power-down (both fast-exit and slow-exit
modes), and precharge power-down modes of opera-
tion. If SELF REFRESH operation is used, R

(

EFF

)

should always be disabled and the ODT input pin is
disabled by the DDR2 SDRAM. During power-up and
initialization of the DDR2 SDRAM, ODT should be dis-
abled until the EMR command is issued to enable the
ODT feature, at which point the ODT pin will deter-
mine the R

(

EFF

) value. See "ODT Timing" on page 9

for ODT timing diagrams.

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Off-Chip Driver (OCD) Impedance Calibration

The OCD function is no longer supported and must

be set to the default state. See "Initialization" on
page 15 to propertly set OCD defaults.

Posted CAS Additive Latency (AL)

Posted CAS additive latency (AL) is supported to

make the command and data bus efficient for sustain-
able bandwidths in DDR2 SDRAM. Bits E3E5 define
the value of AL as shown in Figure 10. Bits E3E5 allow
the user to program the DDR2 SDRAM with a CAS#
Additive latency of 0, 1, 2, 3, or 4 clocks. Reserved states
should not be used as unknown operation or incom-
patibility with future versions may result.

In this operation, the DDR2 SDRAM allows a READ

or WRITE command to be issued prior to

RCD (MIN)

with the requirement that AL

RCD(MIN). A typical

application using this feature would set AL =

RCD

(MIN) - 1 x

CK. The READ or WRITE command is held

for the time of the additive latency (AL) before it is
issued internally to the DDR2 SDRAM device. READ
Latency (RL) is controlled by the sum of the Posted
CAS additive latency (AL) and CAS Latency (CL); RL =
AL + CL. Write latency (WL) is equal to READ latency
minus one clock; WL = AL + CL - 1 x

CK. An example

of a READ latency is shown in Figure 11. An example of
a WRITE latency is shown in Figure 12.

Figure 11: READ Latency

Figure 12: Write Latency

OUT

n + 3

OUT

n + 2

OUT

n + 1

CK#

COMMAND

DQS, DQS#

AL = 2

ACTIVE n

Burst length = 4
Shown with nominal tAC, tDQSCK, and tDQSQ

DON'T CARE

TRANSITIONING DATA

READ n

NOP

OUT

NOP

CL = 3

RL = 5

CAS# latency (CL) = 3
Additive latency (AL) = 2
READ latency (RL) = AL + CL = 5

tRCD (MIN)

NOP

CK#

COMMAND

DQS, DQS#

ACTIVE n

Burst length = 4

DON'T CARE

TRANSITIONING DATA

NOP

WRITE n

NOP

n + 3

n + 2

n + 1

WL = AL + CL - 1 = 4

NOP

CAS# latency (CL) = 3
Additive latency (AL) = 2
WRITE latency = AL + CL -1 = 4

RCD (MIN)

NOP

AL = 2

CL - 1 = 2

256Mb: x4, x8, x16

DDR2 SDRAM

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Extended Mode Register 2 (EMR2)

The Extended Mode Register 2 (EMR2) controls

functions beyond those controlled by the mode regis-
ter. Currently all bits in EMR2 are reserved as shown in
Figure 13. The EMR2 is programmed via the LOAD
MODE command and will retain the stored informa-
tion until it is programmed again or the device loses
power. Reprogramming the extended mode register
will not alter the contents of the memory array, pro-
vided it is performed correctly.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the
controller must wait the specified time

MRD before

initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.

Figure 13: Extended Mode Register 2

(EMR2) Definition

Extended Mode Register 3 (EMR3)

The Extended Mode Register 3 (EMR3) controls

functions beyond those controlled by the mode regis-
ter. Currently all bits in EMR3 are reserved as shown in
Figure 14. The EMR3 is programmed via the LOAD
MODE command and will retain the stored informa-
tion until it is programmed again or the device loses
power. Reprogramming the extended mode register
will not alter the contents of the memory array, pro-
vided it is performed correctly.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the
controller must wait the specified time

MRD before

initiating any subsequent operation. Violating either of
these requirements could result in unspecified opera-
tion.

Figure 14: Extended Mode Register 3

(EMR3) Definition

A7 A6 A5 A4 A3

A1 A0

Extended Mode

Address Bus

A10

A12 A11

BA0

BA1

* E12 (A12)E0 (A0) are reserved for future

use and must all be programmed to '0.'

Mode Register

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

E14

E13

EMR(2) 0* 0*

0* 0* 0* 0* 0* 0* 0* 0*

0* 0*

A7 A6 A5 A4 A3

A1 A0

Extended Mode

Address Bus

A10

A12 A11

BA0

BA1

* E12 (A12)E0 (A0) are reserved for future

use and must all be programmed to '0.'

Mode Register

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

E14

E13

EMR(3) 0* 0*

0* 0* 0* 0* 0* 0* 0* 0*

0* 0*

256Mb: x4, x8, x16

DDR2 SDRAM

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Command Truth Tables

The following tables provide a quick reference of

DDR2 SDRAM available commands, including CKE
power-down modes, and bank-to-bank commands.

NOTE:

1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA1-BA0 determine which bank is to be operated upon. BA during a Load Mode command selects

which mode register is programmed.

3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See sections "Read Interrupted by a Read" and

"Write Interrupted by a Write" for other restrictions and details.

4. The Power Down Mode does not perform any refresh operations. The duration of power-down is therefore limited by

the refresh requirements outlined in the AC parametric section.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh.

See the ODT section for details.

6. "X" means "H or L" (but a defined logic level).
7. Self refresh exit is asynchronous.

Table 4:

Truth Table DDR2 Commands

Notes: 1, 5, and 6 apply to the entire Table.

FUNCTION

CKE

CS#

RAS# CAS# WE#

BA1
BA0

A12
A11

A10

A9A0

NOTES

CYCLE

CURRENT

CYCLE

Load Mode

OP Code

Refresh

Self Refresh Entry

Self Refresh Exit

Single Bank
Precharge

ALL Banks Precharge

Bank Activate

Row Address

Write

Column
Address

2, 3

Write with Auto
Precharge

Column
Address

2, 3

Read

Column
Address

2, 3

Read with Auto
Precharge

Column
Address

2, 3

No Operation

Device Deselect

Power-Down Entry

Power-Down Exit

256Mb: x4, x8, x16

DDR2 SDRAM

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NOTE:

1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 5) and after

XSNR has been met (if the previous

state was self refresh).

2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are

those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses and no reg-

4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or

allowable commands to the other bank, should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and Table 5, and according to Table 6.

Precharging: Starts with registration of a PRECHARGE command and ends when

RP is met. Once

RP is met, the

bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when

RCD is met. Once

RCD is met,

the bank will be in the "row active" state.
Read with Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled
and ends when

RP has been met. Once

RP is met, the bank will be in the idle state.

Write with Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled
and ends when

RP has been met. Once

RP is met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be

applied on each positive clock edge during these states.

Refreshing: Starts with registration of an REFRESH command and ends when

RFC is met. Once

RFC is met, the

DDR2 SDRAM will be in the all banks idle state.
Accessing Mode Register: Starts with registration of a LOAD MODE command and ends when

MRD has been

met. Once

MRD is met, the DDR2 SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when

RP is met. Once

RP is

met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.

Table 5:

Truth Table Current State Bank n - Command to Bank n

Notes: 16; notes appear below and on next page.

CURRENT

STATE

CS#

RAS#

CAS#

WE#

COMMAND/ACTION

NOTES

Any

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous
operation)

Idle

ACTIVE (select and activate row)

REFRESH

LOAD MODE

Row Active

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE (deactivate row in bank or banks)

Read (Auto-

Precharge

Disabled

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

9, 11

PRECHARGE ( start precharge)

Write (Auto-

Precharge

Disabled)

READ (select column and start READ burst)

9, 10

WRITE (select column and start new WRITE burst)

PRECHARGE (start precharge)

8, 10

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DDR2 SDRAM

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9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.

10. Requires appropriate DM masking.
11. A WRITE command may be applied after the completion of the READ burst.

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DDR2 SDRAM

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NOTE:

1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Truth Table 2) and after

XSNR has been met (if the

previous state was self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the com-

mands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given com-
mand is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses and no reg-

ister accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated.
Read with Auto Precharge Enabled: See following text 3a
Write with Auto Precharge Enabled: See following text 3a
3a.The read with auto precharge enabled or write with auto precharge enabled states can each be broken into
two parts: the access period and the precharge period. For read with auto precharge, the precharge period is
defined as if the same burst was executed with auto precharge disabled and then followed with the earliest pos-
sible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the pre-
charge period begins when

WR ends, with

WR measured as if auto precharge was disabled. The access period

starts with registration of the command and ends where the precharge period (or

RP) begins.

This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write
with auto precharge is enabled any command to other banks is allowed, as long as that command does not
interrupt the read or write data transfer already in process. In either case, all other related limitations apply
(e.g., contention between read data and write data must be avoided).

Table 6:

Truth Table Current State Bank n - Command to Bank m

Notes: 16; notes appear below and on next page.

CURRENT STATE

CS#

RAS#

CAS#

WE#

COMMAND/ACTION

NOTES

Any

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

Idle

Any Command Otherwise Allowed to Bank m

Row Activating,
Active, or
Precharging

ACTIVE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

Read (Auto
Precharge
Disabled

ACTIVE (select and activate row)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

7, 9

PRECHARGE

Write (Auto
Precharge
Disabled.)

ACTIVE (select and activate row)

READ (select column and start READ burst)

7, 8

WRITE (select column and start new WRITE burst)

PRECHARGE

Read (with Auto-
Precharge)

ACTIVE (select and activate row)

READ (select column and start new READ burst)

7, 3a

WRITE (select column and start WRITE burst)

7, 9, 3a

PRECHARGE

Write (with Auto-
Precharge)

ACTIVE (select and activate row)

READ (select column and start READ burst)

7, 3a

WRITE (select column and start new WRITE burst)

7, 3a

PRECHARGE

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3b.The minimum delay from a read or write command with auto precharge enabled, to a command to a differ-
ent bank is summarized below.

4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.
5. Not used.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.

8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst.

10.

WTR is defined as Min (2 or

WTR/

CK rounded up to the next integer).

CL = CAS Latency; BL = bust length; WL = WRITE latency

FROM

COMMAND

(BANK n)

TO COMMAND (BANK m)

MINIMUM DELAY (WITH

CONCURRENT AUTO

PRECHARGE)

UNITS

WRITE with

Auto

Precharge

READ or READ w/AP

(CL - 1) + (BL / 2) +

WTR

WRITE or WRITE w/AP

(BL / 2)

PRECHARGE or ACTIVE

READ with

Auto

Precharge

READ or READ w/AP

(BL / 2)

WRITE or WRITE w/AP

(BL / 2) + 2

PRECHARGE or ACTIVE

256Mb: x4, x8, x16

DDR2 SDRAM

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DESELECT, NOP, and LOAD MODE Commands

DESELECT

The DESELECT function (CS# HIGH) prevents new

commands from being executed by the DDR2 SDRAM.
The DDR2 SDRAM is effectively deselected. Opera-
tions already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

instruct the selected DDR2 SDRAM to perform a NOP
(CS# is LOW; RAS#, CAS#, and WE are HIGH). This pre-

vents unwanted commands from being registered dur-
ing idle or wait states. Operations already in progress
are not affected.

LOAD MODE (LM)

The mode registers are loaded via inputs BA1-BA0

and A12 A0 for x4 and x8, and A12 - A0 for x16 config-
urations. BA1-BA0 determine which mode register will
be programmed. See "Mode Register (MR)" on
page 14. The LOAD MODE command can only be
issued when all banks are idle, and a subsequent exe-
cutable command cannot be issued until

MRD is met.

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DDR2 SDRAM

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Bank/Row Activation

ACTIVE Command

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The
value on the BA1-BA0 inputs selects the bank, and the
address provided on inputs A12 A0 for x4 and x8, and
A12 - A0 for x16 selects the row. This row remains
active (or open) for accesses until a PRECHARGE com-
mand is issued to that bank. A PRECHARGE command
must be issued before opening a different row in the
same bank.

ACTIVE Operation

Before any READ or WRITE commands can be

issued to a bank within the DDR2 SDRAM, a row in
that bank must be "opened" (activated). This is accom-
plished via the ACTIVE command, which selects both
the bank and the row to be activated, as shown in
Figure 15.

Figure 15: ACTIVE Command

After a row is opened with an ACTIVE command, a

READ or WRITE command may be issued to that row,
subject to the

RCD specification.

RCD (MIN) should

be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be entered. The same procedure
is used to convert other specification limits from time
units to clock cycles. For example, a

RCD(MIN) speci-

fication of 20ns with a 266 MHz clock (

CK = 3.75ns)

results in 5.3 clocks rounded up to 6. This is reflected
in Figure 17, which covers any case where 5 <

RCD

(MIN) /

CK 6. Figure 17 also shows the case for

RRD

where 2 <

RRD (MIN) /

CK 3.

A subsequent ACTIVE command to a different row

in the same bank can only be issued after the previous
active row has been "closed" (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by

RC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by

RRD.

DON'T CARE

CK#

CS#

RAS#

CAS#

WE#

CKE

Row

Bank

ADDRESS

BANK ADDRESS

256Mb: x4, x8, x16

DDR2 SDRAM

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READs

READ Command

The READ command is used to initiate a burst read

access to an active row. The value on the BA1-BA0
inputs selects the bank, and the address provided on
inputs A0i (where i = A9 for x16, A9 for x8, or A9, A11
for x4) selects the starting column location. The value
on input A10 determines whether or not auto pre-
charge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses.

READ Operation

READ bursts are initiated with a READ command, as

shown in Figure 16. The starting column and bank
addresses are provided with the READ command and
auto precharge is either enabled or disabled for that
burst access. If auto precharge is enabled, the row
being accessed is automatically precharged at the
completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the
burst.

During READ bursts, the valid data-out element

from the starting column address will be available
READ latency (RL) clocks later. READ latency (RL) is
defined as the sum of Posted CAS additive latency (AL)
and CAS Latency (CL); RL = AL + CL. The value for AL
and CL are programmable via the MR and EMR com-
mands, respectively. Each subsequent data-out ele-
ment will be valid nominally at the next positive or

negative clock edge (i.e., at the next crossing of CK and
CK#). Figure 18 shows examples of READ latency
based on different AL and CL settings.

Figure 16: READ Command

Figure 17: Example: Meeting

RRD (MIN) and

RCD (MIN)

DON'T CARE

CK#

CS#

RAS#

CAS#

WE#

CKE

Col

Bank

ADDRESS

BANK ADDRESS

AUTO PRECHARGE

ENABLE

DISABLE

A10

COMMAND

DON'T CARE

RRD

Row

Col

Bank x

Bank y

NOP

ACT

NOP

ACT

NOP

RD/WR

RCD

BA0, BA1

CK#

ADDRESS

NOP

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 18: READ Latency

NOTE:

1. DO n = data-out from column n.
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Shown with nominal

AC,

DQSCK, and

DQSQ.

READ

NOP

Bank a,

Col n

CK#

COMMAND

ADDRESS

DQS,DQS#

T4n

T5n

CK#

COMMAND

READ

NOP

ADDRESS

Bank a,

Col n

RL = 3 (AL = 0, CL = 3)

DQS, DQS#

T3n

T4n

CK#

COMMAND

READ

NOP

ADDRESS

Bank a,

Col n

RL = 4 (AL = 0, CL = 4)

DQS, DQS#

T3n

T4n

AL = 1

CL = 3

RL = 4 (AL + CL)

DON'T CARE

TRANSITIONING DATA

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

DQS/DQS# is driven by the DDR2 SDRAM along

with output data. The initial LOW state on DQS and
HIGH state on DQS# is known as the READ preamble
(

RPRE). The LOW state on DQS and HIGH state on

DQS# coincident with the last data-out element is
known as the read postamble (

RPST).

Upon completion of a burst, assuming no other

commands have been initiated, the DQs will go High-
Z. A detailed explanation of

DQSQ (valid data-out

skew),

QH (data-out window hold), the valid data win-

dow are depicted in Figure 27 on page 40 and Figure 28

on page 41. A detailed explanation of

DQSCK (DQS

transition skew to CK) and

AC (data-out transition

skew to CK) is shown in Figure 29 on page 42.

Data from any READ burst may be concatenated

with data from a subsequent READ command to pro-
vide a continuous flow of data. The first data element
from the new burst follows the last element of a com-
pleted burst. The new READ command should be
issued x cycles after the first READ command, where x
equals BL / 2 cycles. This is shown in Figure 19.

Figure 19: Consecutive READ Bursts

NOTE:

1. 1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal

AC,

DQSCK, and

DQSQ.

6. Example applies only when READ commands are issued to same device.

CK#

COMMAND

READ

NOP

READ

NOP

ADDRESS

Bank,

Col n

Bank,

Col b

COMMAND

READ

NOP

READ

NOP

ADDRESS

Bank,

Col n

Bank,

Col b

RL = 3

CK#

COMMAND

ADDRESS

DQS, DQS#

RL = 4

DQS, DQS#

T3n

T4n

T5n

T6n

T2n

NOP

T3n

T4n

T5n

T6n

DON'T CARE

TRANSITIONING DATA

CCD

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 20: Nonconsecutive READ Bursts

NOTE:

1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal

AC,

DQSCK, and

DQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecutive READs.

Nonconsecutive read data is illustrated in Figure 20

on page 34. Full-speed random read accesses within a
page (or pages) can be performed. DDR2 SDRAM sup-
ports the use of concurrent auto precharge timing,
which is shown in Table 7 on page 36.

DDR2 SDRAM does not allow interrupting or trun-

cating of any READ burst using BL = 4 operations.
Once the BL = 4 READ command is registered, it must
be allowed to complete the entire READ burst. How-

ever, a READ (with AUTO PRECHARGE disabled) using
BL = 8 operation may be interrupted and truncated
ONLY by another READ burst as long as the interrup-
tion occurs on a four-bit boundary due to the 4n
prefetch architecture of DDR2 SDRAM. READ burst BL
= 8 operations may not be interrupted or truncated
with any command except another READ command as
shown in Figure 21 on page 35.

CK#

COMMAND

READ

NOP

ADDRESS

Bank,

Col n

READ

Bank,

Col b

COMMAND

ADDRESS

CL = 3

CK#

COMMAND

ADDRESS

DQS, DQS#

CL = 4

DQS, DQS#

T3n

T4n

T6n

T7n

NOP

T5n

T4n

T7n

READ

NOP

Bank,

Col n

READ

Bank,

Col b

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 21: READ Interrupted by READ

NOTE:

1. Burst length = 8 required, AUTO PRECHARGE must be disabled (A10 = LOW).
2. READ command can be issued to any valid bank and row address (READ command at T0 and T2 can be either same bank

or different bank).

3. Interupting READ command must be issued exactly 2 x

CK from previous READ.

4. AUTO PRECHARGE can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interupting READ command.
5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to banks used for READs at T0

and T2.

6. Example shown uses additive latency = 0; CAS Latency = 3, BL = 8, shown with nominal

AC,

DQSCK, and

DQSQ.

OUT

CK#

COMMAND

DQS, DQS#

CL = 3 (AL = 0)

DON'T CARE

TRANSITIONING DATA

NOP5

OUT

VALID

OUT

VALID

CL = 3 (AL = 0)

CCD

ADDRESS

A10

VALID4

VALID2

256Mb: x4, x8, x16

DDR2 SDRAM

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Data from any READ burst must be completed

before a subsequent WRITE burst is allowed. An exam-
ple of a READ burst followed by a WRITE burst is
shown in Figure 24. The

DQSS (MIN) case is shown;

the

DQSS (MAX) case has a longer bus idle time.

(

DQSS [MIN] and

DQSS [MAX] are defined in the sec-

tion on WRITEs.)

A READ burst may be followed by a PRECHARGE

command to the same bank provided that AUTO PRE-
CHARGE is not activated. Examples of READ to PRE-
CHARGE are shown in Figure 22 for BL=4 and
Figure 23 for BL=8. The delay from READ command to
PRECHARGE command to the same bank is AL + BL/2
+ tRTP - 2 clocks.

If A10 is HIGH when a READ command is issued,

the READ with AUTO PRECHARGE function is
engaged. The DDR2 SDRAM starts an AUTO PRE-
CHARGE operation on the rising edge which is (AL +

BL/2) cycles later than the READ with AP command if

RAS (MIN) and

RTP are satisfied. If

RAS (MIN) is not

satisfied at the edge, the start point of AUTO PRE-
CHARGE operation will be delayed until

RAS (MIN) is

satisfied. If

RTP (MIN) is not satisfied at the edge, the

start point of the AUTO PRECHARGE operation will be
delayed until

RTP (MIN) is satisfied. In case the inter-

nal precharge is pushed out by

RTP,

RP starts at the

point where the internal precharge happens (not at the
next rising clock edge after this event). So for BL = 4 the
minimum time from READ with AP to the next activate
command becomes AL + (

RTP +

RP)* (see Figure 22

on page 36); for BL = 8 the time from READ with AP to
the next activate is AL + 2 clocks + (

RTP +

RP)* (see

Figure 23 on page 37), where * means each parameter
term is divided by

CK and rounded up to the next inte-

ger. In any event, internal precharge does not start ear-
lier than two clocks after the last four-bit prefetch.

Figure 22: READ to PRECHARGE BL = 4

Table 7:

READ Using Concurrent Auto Precharge

BL = burst length.

FROM

COMMAND

(BANK n)

TO COMMAND

(BANK m)

MINIMUM DELAY (WITH CONCURRENT

AUTO PRECHARGE)

UNITS

READ with

Auto

Precharge

READ or READ w/AP

(BL/2)

WRITE or WRITE w/AP

(BL/2) + 2

PRECHARGE or ACTIVE

OUT

CK#

COMMAND

DQS, DQS#

CL = 3

READ

Read Latency = 4 (AL = 1, CL = 3), BL = 4, tRTP

2 clocks

Shown with nominal tAC, tDQSCK, and tDQSQ

DON'T CARE

TRANSITIONING DATA

NOP

PRECHARGE

OUT

ACTIVE

ADDRESS

A10

AL=1

NOP

Bank a

tRTP(MIN)

Bank a

tRAS(MIN)

Bank a

tRP(MIN)

NOP

AL + BL/2 + tRTP - 2 clocks

NOP

tRC(MIN)

4-bit
prefetch

Valid

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 23: READ to PRECHARGE BL = 8

Figure 24: READ to WRITE

OUT

CK#

COMMAND

DQS, DQS#

CL = 3

READ

Read Latency = 4 (AL=1, CL=3), BL=8, tRTP

2 clocks

Shown with nominal tAC, tDQSCK, and tDQSQ

DON'T CARE

TRANSITIONING DATA

NOP

OUT

ADDRESS

A10

AL=1

NOP

Bank a

tRC(MIN)

tRTP(MIN)

NOP

OUT

first 4-bit
prefetch

second 4-bit
prefetch

tRP(MIN)

PRECHARGE

Bank a

NOP

AL + BL/2 + tRTP - 2 clocks

NOP

ACTIVE

tRAS(MIN)

Valid

OUT

n + 3

OUT

n + 2

OUT

n + 1

CK#

COMMAND

DQS, DQS#

AL = 2

ACTIVE n

Burst length = 4
Shown with nominal tAC, tDQSCK, and tDQSQ

DON'T CARE

TRANSITIONING DATA

READ n

NOP

OUT

NOP

WRITE n

NOP

n + 3

n + 2

n + 1

WL = RL - 1 = 4

NOP

T10

T11

NOP

CL = 3

RL = 5

CAS# read latency (CL) = 3
Posted CAS# additive latency (AL) = 2

RCD = 3

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 25: Bank Read Without Auto Precharge

NOTE:

1. DO n = data-out from column n; subsequent elements are applied in the programmed order.
2. Burst length = 4 and AL = 0 in the case shown.
3. Disable auto precharge.
4. "Don't Care" if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

7. The PRECHARGE command can only be applied at T6 if

RAS minimum is met.

8. Read to Precharge = AL +BL/2 +

RTP-2 clocks.

CK#

CKE

A10

BA0, BA1

RCD

RAS7

CL = 3

T7n

T8n

DQS, DQS#

Case 1:

AC (MIN) and

DQSCK (MIN)

Case 2:

AC (MAX) and

DQSCK (MAX)

DQS, DQS#

RPRE

RPST

DQSCK (MIN)

DQSCK (MAX)

LZ (MIN)

LZ (MAX)

AC (MIN)

LZ (MIN)

HZ (MAX)

AC (MAX)

LZ (MIN)

NOP6

COMMAND

ACT

Col n

PRE

Bank x

Bank x4

ACT

Bank x

NOP6

HZ (MIN)

ONE BANK

ALL BANKS

DON'T CARE

TRANSITIONING DATA

ADDRESS

tRTP

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 26: Bank Read With Auto Precharge

NOTE:

1. DO n = data-out from column n; subsequent elements are applied in the programmed order.
2. Burst length = 4, RL = 4 (AL = 1, CL = 3) in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = row address, BA = bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.

6. The DDR2 SDRAM internally delays auto precharge until both

RAS (MIN) and

RTP (MIN) have been satisfied.

CK#

CKE

A10

BA0, BA1

RCD

RAS

CL = 3

T7n

T8n

DQS,DQS#

Case 1:

AC (MIN) and

DQSCK (MIN)

Case 2:

AC (MAX) and

DQSCK (MAX)

DQS, DQS#

RPRE

RPST

DQSCK (MIN)

DQSCK (MAX)

LZ (MIN)

LZ (MAX)

AC (MIN)

LZ (MIN)

HZ (MAX)

AC (MAX)

LZ (MAX)

NOP5

COMMAND

ACT

Col n

Bank x

ACT

Bank x

NOP5

HZ (MIN)

DON'T CARE

TRANSITIONING DATA

ADDRESS

AL=1

4-bit
prefetch

tRTP

Internal
precharge

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 27: x4, x8 Data Output Timing

DQSQ,

QH, and Data Valid Window

NOTE:

1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are "early DQS," at T3

are "nominal DQS," and at T3n are "late DQS."

2. For a x4, only two DQs apply.

DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transitions and ends with

the last valid transition of DQs .

QH is derived from

HP:

QH =

HP -

QHS.

HP is the lesser of

CL or

CH clock transitions collectively when a bank is active.

6. The data valid window is derived for each DQS transition and is defined as

QH minus

DQSQ.

DQ (Last data valid)

DQS#

DQS

DQ (Last data valid)

DQ (First data no longer valid)

All DQs and DQS, collectively

Earliest signal transition

Latest signal transition

T2n

T3n

CK#

T2n

T3n

tQH

tHP

tQH

tHP

tQH

tDQSQ

Data

Valid

window

Data

Valid

window

Data

Valid

window

Data

Valid

window

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 28: x16 Data Output Timing

DQSQ,

QH, and Data Valid Window

NOTE:

1. DQs transitioning after DQS transitions define the

DQSQ window. LDQS defines the lower byte, and UDQS defines the

upper byte.

2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transitions and ends with

the last valid transition of DQs.

QH is derived from

HP:

QH =

HP -

QHS.

HP is the lesser of

CL or

CH clock transitions collectively when a bank is active.

6. The data valid window is derived for each DQS transition and is

QH minus

DQSQ.

7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

DQ (Last data valid)

LDSQ#

LDQS

DQ (Last data valid)

DQ (First data no longer valid)

DQ0DQ7 and LDQS, collectively

T2n

T3n

CK#

T2n

T3n

tQH

tDQSQ

Data Valid

window

Data Valid

window

DQ (Last data valid)

UDQS#

UDQS

DQ (Last data valid)

DQ (First data no longer valid)

DQ8DQ15 and UDQS, collectively

T2n

T3n

tQH

tDQSQ

tHP

tQH

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

Upper Byte

Lower Byte

Data Valid

window

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 29: Data Output Timing

AC and

DQSCK

NOTE:

DQSCK is the DQS output window relative to CK and is the"long-term" component of DQS skew.

2. DQs transitioning after DQS transitions define

DQSQ window.

3. All DQs must transition by

DQSQ after DQS transitions, regardless of

AC.

AC is the DQ output window relative to CK and is the"long term" component of DQ skew.

LZ (MIN) and

AC (MIN) are the first valid signal transitions.

HZ (MAX) and

AC (MAX) are the latest valid signal transitions.

7. READ command with CL=3, AL=0 issued at T0.

CK#

DQS#/DQS, or

LDQS#/LDQS / UDQ#/UDQS

T3n

T4n

T5n

T6n

tRPST

tLZ (MIN)

tDQSCK

(MAX)

tDQSCK

(MIN)

tDQSCK

(MAX)

tDQSCK

(MIN)

tHZ (MAX)

tRPRE

DQ (Last data valid)

DQ (First data valid)

All DQs collectively

tAC

(MIN)

tAC

(MAX)

tLZ (MIN)

tHZ (MAX)

T3n

T4n

T5n

T6n

T3n

T4n

T5n

T6n

256Mb: x4, x8, x16

DDR2 SDRAM

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WRITEs

WRITE Command

The WRITE command is used to initiate a burst

write access to an active row. The value on the BA1-
BA0 inputs selects the bank, and the address provided
on inputs A0i (where i = A9 for x8 and x16; or A9, A11
for x4) selects the starting column location. The value
on input A10 determines whether or not auto pre-
charge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
write burst; if auto precharge is not selected, the row
will remain open for subsequent accesses.

Figure 30: WRITE Command

Input data appearing on the DQs is written to the

memory array subject to the DM input logic level
appearing coincident with the data. If a given DM sig-
nal is registered LOW, the corresponding data will be
written to memory; if the DM signal is registered
HIGH, the corresponding data inputs will be ignored,
and a write will not be executed to that byte/column
location (Figure 40).

WRITE Operation

WRITE bursts are initiated with a WRITE command,

as shown in Figure 30. DDR2 SDRAM uses Write
Latency (WL) equal to Read Latency minus 1 clock
cycle (WL = RL - 1 = AL + CL - 1). The starting column
and bank addresses are provided with the WRITE com-
mand, and auto precharge is either enabled or dis-
abled for that access. If auto precharge is enabled, the
row being accessed is precharged at the completion of
the burst. For the generic WRITE commands used in
the following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element

will be registered on the first rising edge of DQS follow-
ing the WRITE command, and subsequent data ele-
ments will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command
and the first rising edge is known as the write pream-
ble; the LOW state on DQS following the last data-in
element is known as the write postamble.

The time between the WRITE command and the

first corresponding rising edge of DQS (

DQSS) is spec-

ified with a relatively wide range (from 75 percent to
125 percent of one clock cycle). All of the WRITE dia-
grams show the nominal case, and where the two
extreme cases (i.e.,

DQSS [MIN] and

DQSS [MAX])

might not be intuitive, they have also been included.
Figure 31 shows the nominal case and the extremes of

DQSS for a burst of 4. Upon completion of a burst,

assuming no other commands have been initiated, the
DQs will remain High-Z and any additional input data
will be ignored.

Data for any WRITE burst may be concatenated

with a subsequent WRITE command to provide con-
tinuous flow of input data. The first data element from
the new burst is applied after the last element of a
completed burst. The new WRITE command should be
issued x cycles after the first WRITE command, where
x equals BL/2.

Figure 32 shows concatenated bursts of 4. An exam-

ple of nonconsecutive WRITEs is shown in Figure 33.
Full-speed random write accesses within a page or
pages can be performed as shown in Figure 34. DDR2
SDRAM supports concurrent auto precharge options
shown in Table 8.

DDR2 SDRAM does not allow interrupting or trun-

cating any WRITE burst using BL = 4 operation. Once
the BL = 4 WRITE command is registered, it must be
allowed to complete the entire WRITE burst cycle.
However, a WRITE (with AUTO PRECHARGE disabled)
using BL = 8 operations may be interrupted and trun-

CS#

WE#

CAS#

RAS#

CKE

A10

BANK ADDRESS

HIGH

EN AP

DIS AP

CK#

CA = column address
BA = bank address
EN AP = enable auto precharge
DIS AP = disable auto precharge

DON'T CARE

ADDRESS

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

cated ONLY by another WRITE burst as long as the
interruption occurs on a four-bit boundary due to the
4n prefetch architecture of DDR2 SDRAM. WRITE
burst BL = 8 operations may NOT be interrupted or
truncated with any command except another WRITE
command as shown in Figure 35.

Data for any WRITE burst may be followed by a sub-

sequent READ command. To follow a WRITE

WTR

should be met as shown in Figure 36.

WTR is defined

as Min(2 or

WTR/

CK rounded up to the next integer).

Data for any WRITE burst may be followed by a subse-
quent PRECHARGE command.

WR must be met as

shown in Figure 30.

WR starts at the end of the data

burst regardless of the data mask condition.

Table 8:

WRITE Using Concurrent Auto Precharge

CL = CAS latency, BL = burst length

FROM

COMMAND

(BANK n)

TO COMMAND

(BANK m)

MINIMUM DELAY (WITH CONCURRENT

AUTO PRECHARGE)

UNITS

WRITE with

Auto

Precharge

READ or READ w/AP

(CL-1) + (BL/2) +

WTR

WRITE or WRITE w/AP

(BL/2)

PRECHARGE or ACTIVE

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 31: WRITE Burst

NOTE:

1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. A burst of 4 is shown with AL = 0, CL = 3; thus, WL = 2.
4. A10 is LOW with the WRITE command (auto precharge is disabled).

DQS, DQS#

DQSS (MAX)

DQSS (NOM)

DQSS (MIN)

tDQSS

CK#

COMMAND

WRITE

NOP

ADDRESS

Bank a,

Col b

NOP

T2n

T3n

DQS, DQS#

tDQSS

DQS, DQS#

tDQSS

DON'T CARE

TRANSITIONING DATA

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 32: Consecutive WRITE to WRITE

NOTE:

1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. A burst of 4 is shown with AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.

Figure 33: Nonconsecutive WRITE to WRITE

NOTE:

1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. A burst of 4 is shown. AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.

CK#

COMMAND

WRITE

NOP

WRITE

NOP

ADDRESS

Bank,

Col b

NOP

Bank,

Col n

T2n

T4n

T5n

T3n

T1n

DQS, DQS#

DON'T CARE

TRANSITIONING DATA

DQSS

DQSS (NOM)

WL = 2

CCD

WL = 2

CK#

COMMAND

WRITE

NOP

ADDRESS

Bank,

Col b

WRITE

Bank,

Col n

T2n

T4n

T3n

T5n

T6n

DQS, DQS#

DQSS (NOM)

DQSS

DON'T CARE

TRANSITIONING DATA

WL = 2

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 34: Random WRITE Cycles

NOTE:

1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An burst of 4 is shown. AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.

Figure 35: WRITE Interrupted by WRITE

NOTE:

1. Burst length = 8 required, AUTO PRECHARGE must be disabled (A10 = LOW).
2. WRITE command can be issued to any valid bank and row address (WRITE command at T0 and T2 can be either same

bank or different bank).

3. Interupting WRITE command must be issued exactly 2 x

CK from previous WRITE.

4. AUTO PRECHARGE can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interupting WRITE command.
5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command can not be issued to banks used for WRITEs at

T0 and T2.

6. Earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 +

WR where

WR starts with T7 and not T5 (since BL

= 8 from MR and not the truncated length).

7. Example shown uses Additive Latency = 0; CAS Latency = 4, BL = 8.

CK#

COMMAND

WRITE

NOP

WRITE

NOP

ADDRESS

Bank,

Col b

NOP

Bank,

Col n

T2n

T4n

T5n

T3n

T1n

DQS, DQS#

DON'T CARE

TRANSITIONING DATA

DQSS

DQSS (NOM)

WL = 2

CCD

WL = 2

a + 3

a + 2

a + 1

CK#

COMMAND

DQS, DQS#

WL = 3

WRITE1

DON'T CARE

TRANSITIONING DATA

WRITE3

b + 3

b + 2

b + 1

b + 7

b + 6

b + 5

b + 4

WL = 3

2 clock requirement

ADDRESS

A10

VALID4

VALID2

VALID6

NOP5

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 36: WRITE to READ

NOTE:

1. DI b = data-in for column b; Dout n = data out from column n.
2. A burst of 4 is shown; AL = 0, CL = 3; thus, WL = 2.
3. One subsequent element of data-in is applied in the programmed order following DI b.

WTR is referenced from the first positive CK edge after the last data-in pair.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

WTR is defined as Min(2 or

WTR/

CK rounded up to the next integer).

7. Required for any READ following a WRITE to the same device.

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

ADDRESS

Bank a,

Col b

Bank a,

Col n

READ

T2n

T9n

T3n

WTR7

CL = 3

DQS, DQS#

DQSS (MIN)

DQS, DQS#

DQSS (MAX)

DQS, DQS#

Dout

DON'T CARE

TRANSITIONING DATA

DQSS

NOP

Dout

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DDR2 SDRAM

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Figure 37: WRITE to PRECHARGE

NOTE:

1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. BL=4; CL = 3; AL = 0; thus, WL = 2.

WR is referenced from the first positive CK edge after the last data-in pair.

5. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE and WRITE commands may be

to different banks, in which case

WR is not required and the PRECHARGE command could be applied earlier.

6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.

DQSS (NOM)

CK#

COMMAND

WRITE

NOP

ADDRESS

Bank a,

Col b

Bank,

(a or all)

NOP

T2n

T3n

DQS#

DQS

DQSS (MIN)

DQS#

DQS

DQSS (MAX)

DQS#

DQS

DON'T CARE

TRANSITIONING DATA

DQSS

PRE

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 38: Bank WriteWithout Auto Precharge

NOTE:

1. DI n = data-in from column n; subsequent elements are applied in the programmed order.
2. BL = 4, AL = 0, and WL = 2 in the case shown.
3. Disable auto precharge.
4. "Don't Care" if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

DSH is applicable during

DQSS (MIN) and is referenced from CK T5 or T6.

DSS is applicable during

DQSS (MAX) and is referenced from CK T6 or T7.

CK#

CKE

A10

BA0, BA1

RCD

RAS

T6n

T5n

NOP6

COMMAND

ACT

Col n

WRITE2

NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6

DQSL

DQSH

WPST

Bank x4

DON'T CARE

TRANSITIONING DATA

DQSS (NOM)

WPRE

DQS, DQS#

ADDRESS

NOP6

WL=2

notes appear below and on next page.

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 39: Bank Writewith Auto Precharge

NOTE:

1. DI n = data-in from column n; subsequent elements are applied in the programmed order.
2. Burst length = 4, AL = 0, and WL = 2 shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = row address, BA = bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.

DSH is applicable during

DQSS (MIN) and is referenced from CK T5 or T6.

DSS is applicable during

DQSS (MAX) and is referenced from CK T6 or T7.

8. WR is programmed via MR[11,10,9] and is calculated by dividing

WR(ns) by

CK and rounding up to the next integer

value.

CK#

CKE

A10

BA0, BA1

tCL

RCD

RAS

T5n

T6n

NOP5

COMMAND

ACT

Col n

WRITE2

NOP5

Bank x

NOP5

Bank x

NOP5

DQSL

DQSH

WPST

DQSS (NOM)

DON'T CARE

TRANSITIONING DATA

WPRE

DQS,DQS#

ADDRESS

NOP5

WL = 2

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 40: WRITEDM Operation

NOTE:

1. DI n = data-in from column n; subsequent elements are applied in the programmed order.
2. Burst length = 4, AL = 1, and WL = 2 in the case shown.
3. Disable auto precharge.
4. "Don't Care" if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

DSH is applicable during

DQSS (MIN) and is referenced from CK T6 or T7.

DSS is applicable during

DQSS (MAX) and is referenced from CK T7 or T8.

WR starts at the end of the data burst regardless of the data mask condition.

CK#

CKE

A10

BA0, BA1

RCD

RAS

tRP

tWR

T7n

T6n

NOP6

COMMAND

ACT

Col n

WRITE2

NOP6

ONE BANK

ALL BANKS

Bank x

NOP6

DQSL

DQSH

WPST

Bank x4

DON'T CARE

TRANSITIONING DATA

DQSS (NOM)

WPRE

PRE

DQS, DQS#

ADDRESS

T10

T11

AL=1

WL=2

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 41: Data Input Timing

NOTE:

DSH (MIN) generally occurs during

DQSS (MIN).

DSS (MIN) generally occurs during

DQSS (MAX).

3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
5. WRITE command with WL=2 (CL=3, AL=0) issued at T0.

DQS#

DQS

tDQSS(nominal)

tDQSH tWPST

tDQSL

tDSS2 tDSH1

tDSH1

tDSS2

CK#

T1n

T2n

T3n

DON'T CARE

TRANSITIONING DATA

tWPRE

256Mb: x4, x8, x16

DDR2 SDRAM

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Precharge

PRECHARGE Command

The PRECHARGE command, illustrated in

Figure 42, is used to deactivate the open row in a par-
ticular bank or the open row in all banks. The bank(s)
will be available for a subsequent row activation a
specified time (

RP) after the precharge command is

issued, except in the case of concurrent auto pre-
charge, where a READ or WRITE command to a differ-
ent bank is allowed as long as it does not interrupt the
data transfer in the current bank and does not violate
any other timing parameters. Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle
state) or if the previously open row is already in the
process of precharging.

PRECHARGE Operation

Input A10 determines whether one or all banks are

to be precharged, and in the case where only one bank
is to be precharged, inputs BA1-BA0 select the bank.
Otherwise BA1-BA0 are treated as "Don't Care."

When all banks are to be precharged, inputs BA1-

BA0 are treated as "Don't Care." Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.

RPA timing applies when the PRE-

CHARGE(ALL) command is issued, regardless of the
number of banks already open or closed. If a single-
bank PRECHARGE command is issued,

RP timing

applies.

Figure 42: PRECHARGE Command

CS#

WE#

CAS#

RAS#

CKE

A10

BA0, BA1

HIGH

ALL BANKS

ONE BANK

ADDRESS

CK#

BA = bank address (if A10 is LOW;

otherwise "Don't Care")

DON'T CARE

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

Self Refresh

SELF REFRESH Command

The SELF REFRESH command can be used to retain

data in the DDR2 SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR2 SDRAM retains data without external clocking.
All power supply inputs (including V

REF

) must be

maintained at valid levels upon entry/exit AND during
self refresh operation.

The SELF REFRESH command is initiated like a

REFRESH command except CKE is (LOW). The DLL is
automatically disabled upon entering self refresh and
is automatically enabled upon exiting self refresh (200
clock cycles must then occur before a READ command
can be issued). Clock should remain stable and meet-

ing

CKE specifications at least 1 x

CK after entering

self refresh mode. All command and address input sig-
nals except CKE are "Don't Care" during self refresh.

The procedure for exiting self refresh requires a

sequence of commands. First, CK, CK# must be stable
and meeting

CK specifications at least 1 x

CK prior to

CKE going back HIGH. Once CKE is HIGH (

CKE(min)

has been satified with four clock registrations), the
DDR2 SDRAM must have NOP or DESELECT com-
mands issued for

XSNR because time is required for

the completion of any internal refresh in progress. A
simple algorithm for meeting both refresh and DLL
requirements is to apply NOP or DESELECT com-
mands for 200 clock cycles before applying any other
command.

256Mb: x4, x8, x16

DDR2 SDRAM

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Figure 43: Self Refresh

NOTE:

1. Clock must be stable and meeting

CK specifications at least 1 x

CK after entering self refresh and at least 1 x

CK prior

to exiting self refresh mode.

2. Device must be in the all banks idle state prior to entering self refresh mode.

XSNR is required before any non-READ command can be applied.

XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.

5. REF = REFRESH command.

6. Self Refresh exit is asynchronous, however,

XSNR and

XSRD timing starts at the first rising clock edge where CKE HIGH

satisfies

ISXR.

7. NOP or DESELECT commands are required prior to exiting SELF REFRESH until state Tc0, which allows any non-READ

command.

8. ODT must be disabled and R

off (

AOFD and

AOFPD have been satisfied) prior to entering Self Refresh at state T1.

9. Once Self Refresh has been entered

CKE(min) must be satisfied prior to exiting self refresh.

10. CKE must stay high;

CKE(min) High = 3 clock registrations.

CK#

COMMAND

NOP

REF

ADDRESS

CKE

VALID

DQS#,

DQS

NOP7

tCK

tXSNR

3,6

tISXR

Enter Self Refresh
Mode (synchronous)

Exit Self Refresh
Mode (asynchronous)

Ta2

Ta1

DON'T CARE

Ta0

Tc0

Tb0

tXSRD

4,6

VALID3

tCKE (MIN)

NOP7

CKE (MIN)

ODT

AOFD /

AOFPD

Td0

VALID4

VALID3

Indicates a break in
time scale

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REFRESH

REFRESH Command

REFRESH is used during normal operation of the

DDR2 SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) refresh. This command is nonpersistent,
so it must be issued each time a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits a "Don't Care"
during an REFRESH command. The 256Mb DDR2
SDRAM requires REFRESH cycles at an average inter-
val of 7.8125µs (maximum). To allow for improved effi-

ciency in scheduling and switching between tasks,
some flexibility in the absolute refresh interval is pro-
vided. A maximum of eight REFRESH commands can
be posted to any given DDR2 SDRAM, meaning that
the maximum absolute interval between any
REFRESH command and the next REFRESH command
is 9 × 7.8125µs (70.3µs). The REFRESH period begins
when the REFRESH command is registered and ends

RFC (min) later.

Figure 44: Refresh Mode

NOTE:

1. PRE = PRECHARGE, ACT = ACTIVE, AR = REFRESH, RA = row address, BA = bank address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be

active during clock positive transitions.

3. "Don't Care" if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all

active banks).

4. DM, DQ, and DQS signals are all "Don't Care"/High-Z for operations shown.
5. The second REFRESH is not required and is only shown as an example of two back-to-back REFRESH commands.

CK#

COMMAND

NOP2

NOP 2

NOP2

PRE

CKE

ADDRESS

A10

BANK

Bank(s)3

REF

NOP2

REF5

NOP2

ACT

NOP2

ONE BANK

ALL BANKS

DQS, DQS#

Ta0

Tb0

Ta1

Tb1

Tb2

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Power-Down Mode

DDR2 SDRAMs support multiple power-down

modes that allow a significant power savings over nor-
mal operating modes. The CKE input pin is used to
enter and exit different power-down modes. Power-
down entry and exit timings are shown in Figure 45.
Detailed power-down entry conditions are shown in
Figure 46 through Figure 53. The Truth Table for CKE is
shown in Table 9 on page 60 for DDR2 SDRAM.

DDR2 SDRAMs require CKE to be registered high

(active) at all times that an access is in progress: from
the issuing of a READ or WRITE command until com-
pletion of the burst. Thus a clock suspend is not sup-
ported. For READs, a burst completion is defined when
the read postamble is satisfied; for WRITEs, a burst
completion is defined when the write postamble and

WR or

WTR are satisfied, and shown in Figure 48 and

Figure 49.

WTR is defined as Min(2 or

WTR/

rounded up to the next integer).

Power-down in Figure 45, is entered when CKE is

registered LOW coincident with a NOP or DESELECT
command. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down.
If power-down occurs when there is a row active in any
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and out-

put buffers, excluding CK, CK#, ODT, and CKE. For
maximum power savings, the DLL is frozen during pre-
charge power-down. Exiting active power-down
requires the device to be at the same voltage and fre-
quency as when it entered power-down. Exiting pre-
charge power-down requires the device to be at the
same voltage as when it entered power-down; how-
ever, the clock frequency is allowed to change (See
"Precharge Power-Down Clock Frequency Change" on
page 7.)

The maximum duration for either active or pre-

charge power-down is limited by the refresh require-
ments of the device

RFC (MAX). The minimum

duration for power-down entry and exit is limited by

CKE(min) parameter. While in power-down mode,

CKE LOW, a stable clock signal, and stable power sup-
ply signals must be maintained at the inputs of the
DDR2 SDRAM, while all other input signals are "Don't
Care" except ODT. Detailed ODT timing diagrams for
different power-down modes are shown for Figure 3 on
page 10 through Figure 8 on page 15.

The power-down state is synchronously exited

when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command) as shown in Figure 45.

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 45: Power-Down

NOTE:

1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is pre-

charge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode
shown is active power-down.

2. No column accesses are allowed to be in progress at the time power-down is entered.

CKE (MIN) of 3 clocks means CKE must be registered on three consecutive positve clock edges. CKE must remain at the

valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may

not trainsition from its valid level during the time period of

IS + 2 *

CK +

IH. CKE must not transition during its

IS and

IH window.

XP timing is used for exit precharge power-down and active power-down to any non-READ command.

XPRD timing is used for exit precharge power-down to any READ command

XARD timing is used for exit active power-down to READ command if 'fast exit' is selected via MR (bit 12 = 0).

XARDS timing is used for exit active power-down to READ command if 'slow exit' is selected via MR (bit 12 = 1).

CK#

COMMAND

NOP

ADDRESS

CKE

DQS, DQS#

VALID

Enter

Power-Down

Mode2

Exit

Power-Down

Mode

DON'T CARE

CKE (MIN)

VALID

VALID1

VALID

XPRD

XARD

6, t

XARDS

VALID

T1 T2 T3 T4 T5 T6 T7 T8

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

NOTE:

1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.
3. COMMAND (n) is the command registered at clock edge n, and ACTION (n) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.

5. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge occurring during the

XSNR period.

Read commands may be issued only after

XSRD (200 clocks) is satisfied.

6. Self refresh mode can only be entered from the all banks idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for power-down entry and exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.

10. Power-down and self refresh can not be entered while READ or WRITE operations, LOAD MODE operations, or PRE-

CHARGE or REFRESH operations are in progress. See Power-Down and Self Refresh sections for a list of detailed restric-
tions.

11. Minimum CKE HIGH time is

CKE = 3 x

CK. Minimum CKE low time is

CKE = 3 x

CK. This requires a minimum of 3 clock

cycles of registration.

12. The state of on-die termination (ODT) does not affect the states described in this table. The ODT function is not avail-

able during self refresh. See ODT section for more details and specific restrictions.

13. Power-down modes do not perform any refresh operations. The duration of power-down mode is therefore limited by

the refresh requirements.

14. "X" means "Don't Care" (including floating around V

REF

) in self refresh and power-down. However, ODT must be driven

HIGH or LOW in power-down if the ODT function is enabled via EMR(1).

Table 9:

CKE Truth Table

Notes 13, 12

CURRENT STATE

CKE

COMMAND (n)

CS#,RAS#,CAS#,WE#

ACTION (n)

NOTES

CYCLE (n-1)

CURRENT

CYCLE (n)

Power Down

Maintain Power-Down

13, 14

DESELECT or NOP

Power-Down Exit

4, 8

Self Refresh

Maintain Self Refresh

DESELECT or NOP

Self Refresh Exit

4, 5, 9

Bank(s) Active

DESELECT or NOP

Active Power-Down Entry

4, 8, 10, 11

All Banks Idle

DESELECT or NOP

Precharge Power-Down Entry

4, 8, 10

REFRESH

Self Refresh Entry

6, 9, 11

Refer to Command Truth Table 1 on page 7

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 46: READ to Power-Down Entry

NOTE:

1. Power-down entry may occur after the READ burst completes.
2. In the example shown, READ burst completes at T5; earliest power-down entry is at T6.

Figure 47: READ with Auto Precharge to Power-Down Entry

NOTE:

1. Power-down entry may occur 1 x

CK after the internal precharge is issued and may be prior to

RP being satisfied.

2. Timing shown above assumes internal PRECHARGE was issued at T5 or earlier.
3. Refer to READ-to-PRECHARGE section for internal precharge timing details.

OUT

CK#

COMMAND

DQS, DQS#

RL = 3

DON'T CARE

TRANSITIONING DATA

NOP

OUT

VALID

CKE (MIN)

ADDRESS

A10

NOP

CKE

READ

VALID

T10

Power-Down

Entry

NOP

OUT

CK#

COMMAND

DQS, DQS#

RL = 3

DON'T CARE

TRANSITIONING DATA

NOP

OUT

VALID

CKE (MIN)

ADDRESS

A10

NOP

CKE

READ

VALID

T10

Power-Down

Entry

NOP

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 48: WRITE to Power-Down Entry

Figure 49: WRITE with Auto Precharge to Power-Down Entry

NOTE:

1. Write Recovery (WR) is programmed through MR[9,10,11] and represents [

WR (MIN) ns /

CK] rounded up to next inte-

ger

CK.

2. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may occur 1 x

CK later at Ta1 prior to

RP being satisfied.

Figure 50: REFRESH command to Power-Down Entry

NOTE:

1. The earliest PRECHARGE power-down entry may occur is at T2 which is 1 x

CK after the REFRESH command. Precharge

power down entry occurs prior to

RFC (MIN) being satisfied.

OUT

CK#

COMMAND

DQS, DQS#

WL = 3

DON'T CARE

TRANSITIONING DATA

NOP

OUT

VALID

VALID1

tCKE (MIN)

ADDRESS

A10

NOP

CKE

WRITE

VALID

T10

Power-Down
Entry

tWTR

NOP

OUT

CK#

COMMAND

DQS, DQS#

WL = 3

DON'T CARE

TRANSITIONING DATA

NOP

OUT

VALID

Ta0

VALID2

NOP

Ta1

Ta2

Ta3

CKE (MIN)

ADDRESS

A10

NOP

CKE

WRITE

VALID

Ta4

Power-Down
Entry

Indicates a break in
time scale

CK#

COMMAND

DON'T CARE

VALID

REFRESH

CKE (MIN)

CKE

Power-Down

Entry

1 x

NOP

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 51: ACTIVE Command to Power-Down Entry

NOTE:

1. The earliest PRECHARGE power-down entry may occur is at T2, which is 1 x

CK after the ACTIVE command. Active

power-down entry occurs prior to

RCD (MIN) being satisfied.

Figure 52: PRECHARGE Command to Power-Down Entry

NOTE:

1. The earliest power-down entry may occur is at T2, which is 1 x

CK after the PRECHARGE command. Power-down entry

occurs prior to

RP (MIN) being satisfied.

CK#

COMMAND

DON'T CARE

VALID

ACTIVE

NOP

tCKE (MIN)

CKE

Power-Down

Entry

1 tCK

ADDRESS

VALID

CK#

COMMAND

DON'T CARE

VALID

PRECHARGE

NOP

CKE (MIN)

CKE

Power-Down

Entry

1 x

ADDRESS

A10

VALID

ALL BANKS

SINGLE BANK

256Mb: x4, x8, x16

DDR2 SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 53: LOAD MODE Command to Power-Down Entry

NOTE:

1. The earliest PRECHARGE power-down entry is at T3, which is after

MRD is satisfied.

2. All banks must be in the precharged state and

RP met prior to issuing LM command.

3. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.

CK#

COMMAND

DON'T CARE

VALID

NOP

CKE (MIN)

CKE

Power-Down

Entry

MRD

ADDRESS

VALID

NOP

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Precharge Power-Down Clock Frequency Change

When the DRAM is in precharged power-down

mode, on-die termination (ODT) must be turned off
and CKE must be at a logic LOW level. A minimum of
two clocks must pass after CKE goes LOW before clock
frequency may change. The DRAM input clock fre-
quency is allowed to change only within minimum and
maximum operating frequencies specified for the par-
ticular speed grade. During input clock frequency
change, ODT and CKE must be held at stable LOW lev-
els. Once the input clock frequency is changed, new

stable clocks must be provided to the DRAM before
precharge power-down may be exited and DLL must
be RESET via EMR after precharge power-down exit.
Depending on the new clock frequency an additional
MR command may need to be issued to appropriately
set the WR MR[11, 10, 9] register. During the DLL
relock period of 200 cycles, ODT must remain off. After
the DLL lock time, the DRAM is ready to operate with a
new clock frequency.

Figure 54: Input Clock Frequency Change During PRECHARGE Power Down Mode

NOTE:

1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is pre-

charge power-down, which is required prior to the clock frequency change.

2. A minimum of 2 x

CK is required after entering PRECHARGE power-down prior to changing clock frequencies.

3. Once the new clock frequency has changed and is stable, a minimum of 1 x

CK is required prior to exiting PRECHARGE

power-down.

4. Minimum CKE HIGH time is

CKE = 3 x

CK. Minimum CKE low time is

CKE = 3 x

CK. This requires a minimum of 3 clock

cycles of registration.

CK#

COMMAND

VALID1

NOP

ADDR

CKE

DQS, DQS#

NOP

Enter PRECHARGE

Power-Down Mode

Exit PRECHARGE

Power-Down Mode

Ta0

DON'T CARE

VALID

CKE (MIN)

DLL RESET

VALID

NOP

Ta1

Ta2

Tb0

Ta3

x t

CK (MIN)

1 x

CK (MIN)

ODT

200 x

NOP

Ta4

PREVIOUS CLOCK FREQUENCY

NEW CLOCK FREQUENCY

Frequency

Change

High-Z

Indicates a break in
time scale

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

RESET Function (CKE LOW Anytime)

DDR2 SDRAM applications may go into a RESET

state at any time during normal operation. If an appli-
cation enters a reset condition, the CKE input pin is
used to ensure the DDR2 SDRAM device resumes nor-
mal operation after reinitializing. All data will be lost
during a reset condition; however, the DDR2 SDRAM
device will continue to operate properly if the follow-
ing conditions outlined in this section are satisfied.

The RESET condition defined here assumes all sup-

ply voltages (V

, V

Q, V

L, and V

REF

) are stable

and meet all DC specifications prior to, during, and
after the RESET operation. All other input pins of the

DDR2 SDRAM device are a "don't care" during RESET
with the exception of CKE.

If CKE asynchronously drops LOW during any valid

operation (including a READ or WRITE burst), the
memory controller must satisfy the timing parameter

ELAY

before turning off the clocks. Stable clocks must

exist at the CK, CK# inputs of DRAM before CKE is
raised HIGH, at which time the normal initialization
sequence must occur (See "Initialization" on page 12).
The DDR2 SDRAM is now ready for normal operation
after the initialization sequence. Figure 55 shows the
proper sequence for a RESET condition.

Figure 55: RESET Condition

CKE

Rtt

BA0, BA1

High-Z

DQS

High-Z

ADDRESS

A10

CK#

COMMAND

NOP2

PRE

ALL BANKS

Ta0

DON'T CARE

TRANSITIONING DATA

tRP

ODT

High-Z

T = 400ns (MIN)

Tb0

READ

NOP2

Col n

Bank a

DELAY

OUT

(

)

(

)

(

)

(

)

(

)

(

)

READ

NOP2

Col n

Bank b

OUT

High-Z

Unknown

System

RESET

Start of Normal

Initialization

Sequence

NOP2

Indicates a break in
time scale

CKE

(MIN)

For Initilization timing, see time sequence Ta0 in

Figure 10, DDR2 Power-Up and Initialization, on

page 13

256Mb: x4, x8, x16

DDR2 SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

ODT Timing

There are two timing categories for ODT, turn-on

and turn-off. During active mode (CKE HIGH) and
"fast-exit" power-down mode (any row of any bank
open, CKE LOW, MR[bit12 = 0]),

AOND,

AON,

AOFD,

and

AOF timing parameters are applied as shown in

Figure 56 and Table 10 on page 68. During "slow-exit"
power-down mode (any row of any bank open, CKE
LOW, MR[bit12=1]) and precharge power-down mode
(all banks/rows precharged and idle, CKE LOW),

AONPD and

AOFPD timing parameters are applied as

shown in Figure 57 and Table 11 on page 69.

ODT turn-off timing prior to entering any power-

down mode is determined by the parameter

ANPD

(MIN) shown in Figure 58. At state T2 the ODT HIGH
signal satisfies

ANPD (MIN) prior to entering power-

down mode at T5. When

ANPD (MIN) is satisfied

AOFD and

AOF timing parameters apply. Figure 58

also shows the example where

ANPD (MIN) is NOT

satisfied since ODT HIGH does not occur until state
T3. When

ANPD (MIN) is NOT satisfied,

AOFPD tim-

ing parameters apply.

ODT turn-on timing prior to entering any power-

down mode is determined by the parameter

ANPD

shown in Figure 59. At state T2, the ODT HIGH signal
satisfies

ANPD (MIN) prior to entering power-down

mode at T5. When

ANPD (MIN) is satisfied

AOND

and

AON timing parameters apply. Figure 59 also

shows the example where

ANPD (MIN) is NOT satis-

fied since ODT HIGH does not occur until state T3.
When

ANPD (MIN) is NOT satisfied,

AONPD timing

parameters apply.

ODT turn-off timing after exiting any power-down

mode is determined by the parameter

AXPD (MIN)

shown in Figure 60. At state Ta1, the ODT LOW signal
satisfies

AXPD (MIN) after exiting power-down mode

at state T1. When

AXPD (MIN) is satisfied,

AOFD and

AOF timing parameters apply. Figure 60 also shows

the example where

AXPD (MIN) is NOT satisfied since

ODT LOW occurs at state Ta0. When

AXPD (MIN) is

NOT satisfied,

AOFPD timing parameters apply.

ODT turn-on timing after exiting any power-down

mode is determined by the parameter

AXPD (MIN)

shown in Figure 61. At state Ta1, the ODT HIGH signal
satisfies

AXPD (MIN) after exiting power-down mode

at state T1. When

AXPD (MIN) is satisfied,

AOND and

AON timing parameters apply. Figure 61 also shows

the example where

AXPD (MIN) is NOT satisfied since

ODT HIGH occurs at state Ta0. When

AXPD (MIN) is

NOT satisfied,

AONPD timing parameters apply.

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 56: ODT Timing for Active or "Fast-Exit" Power-Down Mode

VALID

CK#

CKE

tAOF (MAX)

ODT

RTT

tAON (MIN)

tAON (MAX)

tAOND

ADDR

tAOFD

tAOF (MIN)

VALID

CMD

DON'T CARE

Unknown

Table 10: ODT Timing for Active and "Fast-Exit" Power-Down Modes

PARAMETER

SYMBOL

MIN

MAX

UNITS

ODT turn-on delay

AOND

ODT turn-on

AON

AC (MIN)

AC (MAX) + 1,000

ODT turn-off delay

AOFD

2.5

ODT turn-off

AOF

AC (MIN)

AC (MAX) + 600

256Mb: x4, x8, x16

DDR2 SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 57: ODT timing for "Slow-Exit" or Precharge Power-Down Modes

DON'T CARE

VALID

CK#

CKE

ODT

ADDR

VALID

CMD

AONPD (MIN)

AONPD (MAX)

AOFPD (MIN)

AOFPD (MAX)

Transitioning R

VALID

Unknown

Table 11: ODT timing for "Slow-Exit" and Precharge Power-Down Modes

PARAMETER

SYMBOL

MIN

MAX

UNITS

ODT turn-on (power-down mode)

AONPD

AC (MIN) + 2,000

CK+

AC (MAX) + 1,000

ODT turn-off (power-down mode)

AOFPD

AC (MIN) + 2,000

2.5 x

CK +

AC (MAX) + 1,000

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 58: ODT "Turn Off" Timings when Entering Power-Down Mode

NOP

CK#

CKE

tANPD (MIN)

ODT

tAOF (MIN)

tAOF (MAX)

tAOFD

ODT

tAOFPD (MIN)

tAOFPD (MAX)

DON'T CARE

Transitioning R

Unknown

RTT On

Table 12: ODT "Turn Off" Timings when Entering Power-Down Mode

PARAMETER

SYMBOL

MIN

MAX

UNITS

ODT turn-off delay

AOFD

2.5

ODT turn-off

AOF

AC (MIN)

AC (MAX) + 600

ODT turn-off (power-down mode)

AOFPD

AC (MIN) + 2,000

2.5 x

CK +

AC (MAX) + 1,000

ODT to power-down entry latency

ANPD

256Mb: x4, x8, x16

DDR2 SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 59: ODT "Turn-On" Timing when Entering Power-Down Mode

NOP

CK#

CKE

ANPD (MIN)

ODT

AON (MIN)

AON (MAX)

AOND

ODT

AONPD (MIN)

AONPD (MAX)

DON'T CARE

Transitioning R

Unknown

Table 13: ODT "Turn-On" Timing when Entering Power-Down Mode

PARAMETER

SYMBOL

MIN

MAX

UNITS

ODT turn-on delay

AOND

ODT turn-on

AON

AC (MIN)

AC (MAX) + 1,000

ODT turn-on (power-down mode)

AONPD

AC (MIN) + 2,000

2 x

CK +

AC (MAX) + 1,000

ODT to power-down entry latency

ANPD

256Mb: x4, x8, x16

DDR2 SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 60: ODT "Turn-Off" Timing when Exiting Power-Down Mode

Ta0

Ta1

NOP

CK#

CKE

tAXPD (MIN)

ODT

tAOF (MAX)

ODT

tAOFPD (MIN)

tAOFPD (MAX)

COMMAND

tCKE (MIN)

Ta2

Ta3

Ta4

Ta5

NOP

DON'T CARE

Transitioning R

Unknown

tAOF (MIN)

tAOFD

Indicates a break in
time scale

Table 14: ODT "Turn-Of" Timing when Exiting Power-Down Mode

PARAMETER

SYMBOL

MIN

MAX

UNITS

ODT turn-off delay

AOFD

2.5

ODT turn-off

AOF

AC (MIN)

AC (MAX) + 600

ODT turn-off (power-down mode)

AOFPD

AC (MIN) + 2,000

2.5 x

CK +

AC (MAX) + 1,000

ODT to power-down exit latency

AXPD

256Mb: x4, x8, x16

DDR2 SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Figure 61: ODT "Turn On" Timing when Exiting Power-Down Mode

Ta0

Ta1

NOP

CK#

CKE

AXPD (MIN)

COMMAND

Ta2

Ta3

Ta4

Ta5

NOP

ODT

AON (MIN)

AON (MAX)

AOND

ODT

AONPD (MIN)

AONPD (MAX)

DON'T CARE

Transitioning

Unknown

Indicates a break in
time scale

tCKE (MIN)

Table 15: ODT "Turn On" Timing when Exiting Power-Down Mode

PARAMETER

SYMBOL

MIN

MAX

UNITS

ODT turn-on delay

AOND

ODT turn-on

AON

AC (MIN)

AC (MAX) + 1,000

ODT turn-on (power-down mode)

AONPD

AC (MIN) + 2,000

2 x

CK +

AC (MAX) + 1,000

ODT to power-down exit latency

AXPD

256Mb: x4, x8, x16

DDR2 SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Figure 62: Example Temperature Test Point Location

Table 16: Absolute Maximum DC Ratings

SYMBOL

PARAMETER

MIN

MAX

UNITS

Supply Voltage Relative to V

-1.0

2.3

Q Supply Voltage Relative to V

-0.5

2.3

L Supply Voltage Relative to VssL

-0.5

2.3

, V

OUT

Voltage on any Pin Relative to V

-0.5

2.3

STG

Storage Temperature (T

case

)

-55

100

°C

Operating Temperature (T

case

)

1,2

°C

Input Leakage Current
Any input 0V <= V

<= VDD

(All other pins not under test = 0V)

-5

Output Leakage Current
0V <= V

OUT

<= V

DQs and ODT are disabled

-5

REF

Leakage Current

REF

= Valid V

REF

level

-2

NOTE:

1. MAX operating case temperature; T

is measured in the center of the package illustrated in Figure 62.

2. Device functionality is not guaranteed if the DRAM device exceeds the maximum T

during operation.

8.00

4.00

12.00

6.00

Test Point

8mm x 12mm "FP" FBGA

8.00

4.00

14.00

7.00

8mm x 14mm "FG" FBGA

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

AC and DC Operating Conditions

NOTE:

1. V

and V

Q must track each other. V

Q must be less than or equal to V

2. V

REF

is expected to equal V

Q/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-

peak noise (non-common mode) on V

REF

may not exceed ±1% of the DC value.

Peak-to-peak AC noise on V

REF

may not

exceed ±2 percent of V

REF

(

This measurement is to be taken at the nearest V

REF

bypass capacitor.

3. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal

to V

REF

and must track variations in the DC level of V

REF

4. V

Q tracks with V

; V

L tracks with V

5. VssQ = VssL = Vss

NOTE:

1. R

EFF

) and R

EFF

) are determined by applying V

(

) and V

(

) to pin under test separately, then measure current

I(V

(

)) and I(V

(

)) respectively.

2. Measure voltage (VM) at tested pin with no load.

Table 17: Recommended DC Operating Conditions (SSTL_18)

All voltages referenced to V

PARAMETER

SYMBOL

MIN

NOM

MAX

UNITS NOTES

Supply Voltage

1.7

1.8

1.9

1, 5

L Supply Voltage

1.7

1.8

1.9

4, 5

I/O Supply Voltage

1.7

1.8

1.9

4, 5

I/O Reference Voltage

REF

(

)

0.49 x V

0.50 x V

0.51

I/O Termination Voltage (system)

REF

(

) - 40

REF

(

)

REF

(

) + 40

Table 18: ODT DC Electrical Characteristics

All voltages referenced to V

PARAMETER

SYMBOL

MIN

NOM

MAX

UNITS

NOTES

effective impedance value for 75

setting

EMR (A6, A2) = 0, 1

EFF

)

effective impedance value for 150

setting

EMR (A6, A2) = 1, 0

EFF

)

120

150

180

Deviation of VM with respect to V

Q/2

-6%

TT EFF

(

)

IH AC

(

) V

IL AC

( )

I V

IH AC

(

)

(

) I V

IL AC

( )

(

)

-------------------------------------------------------------

2 VM

------------------ 1

100%

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Input Electrical Characteristics and Operating Conditions

Figure 63: Single-Ended Input Signal Levels

NOTE:

Numbers in diagram reflect nomimal values.

Table 19: Input DC Logic Levels

All voltages referenced to V

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

(

) + 125

Q + 300

Input Low (Logic 0) Voltage

(

)

-300

REF

(

) - 125

Table 20: Input AC Logic Levels

All voltages referenced to V

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

(

) + 250

Input Low (Logic 0) Voltage

(

)

REF

(

) - 250

650mV

775mV

864mV

882mV

900mV

918mV

936mV

1,025mV

1,150mV

(AC)

(DC)

REF

- AC Noise

REF

- DC Error

REF

+ DC Error

REF

+ AC Noise

(DC)

(AC)

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NOTE:

1. V

(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK#, DQS, DQS#, LDQS,

LDQS#, UDQS, UDQS#, and RDQS, RDQS#.

2. V

(DC) specifies the input differential voltage | V

- V

| required for switching, where V

is the true input (such as

CK, DQS, LDQS, UDQS, RDQS) level and V

is the complementary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#). The

minimum value is equal to V

(DC) - V

(DC). Differential input signal levels are shown in Figure 64.

3. V

(AC) specifies the input differential voltage | V

- V

| required for switching, where V

is the true input (such as

CK, DQS, LDQS, UDQS, RDQS) level and V

is the complementary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#). The

minimum value is equal to V

(AC) - V

(AC) from Table 20 on page 76.

4. The typical value of V

(AC) is expected to be about 0.5 x V

Q of the transmitting device and V

(AC) is expected to

track variations in V

Q. V

(AC) indicates the voltage at which differential input signals must cross as shown in

Figure 64.

5. V

(

) specifies the input differential common mode voltage (V

+ V

)/2 where V

is the true input (CK, DQS) level

and V

is the complementary input (CK#, DQS#). V

(

) is expected to be about 0.5*V

Figure 64: Differential Input Signal Levels

NOTE:

1. This provides a minimum of 850mV to a maximum of 950mV and is expected to be V

Q/2.

2. TR and CP must cross in this region.
3. TR and CP must meet at least V

(DC) min when static and is centered around V

(DC).

4. TR and CP must have a minimum 500mV peak-to-peak swing.
5. TR and CP may not be more positive than V

Q + 0.3V or more negative than V

- 0.3V.

6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values.
8. TR represents the CK, DQS, RDQS, LDQS and UDQS signals; CP represents CK#, DQS#, RDQS#, LDQS# and UDQS# signals.

Table 21: Differential Input Logic Levels

All voltages referenced to V

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

DC Input Signal Voltage

(DC)

-300

Q + 300

DC Differential Input Voltage

(DC)

250

Q + 600

AC Differential Input Voltage

(AC)

500

Q + 600

AC Differential Cross-Point Voltage

(AC)

0.50 x V

Q - 175

0.50 x V

Q + 175

Input Midpoint Voltage

(

)

850

950

2.1 V

@ V

Q=1.8V

IN(DC)

MAX5

IN(DC)

MIN5

- 0.30V

0.9V

1.075 V

0.725 V

(AC)

(DC)

(AC)

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NOTE:

1. All voltages referenced to V

2. Input waveform setup timing (

) is referenced from the input signal crossing at the V

IH(AC)

level for a rising signal and

(

) for a falling signal applied to the device under test as shown in Figure 69.

3. Input waveform hold (

) timing is referenced from the input signal crossing at the V

(

) level for a rising signal and

(

) for a falling signal applied to the device under test as shown in Figure 69

4. Input waveform setup timing (

DS) and hold timing (

DH) for single-ended data strobe is referenced from the crossing of

DQS, UDQS, or LDQS through the V

REF

level applied to the device under test as shown in Figure 71.

5. Input waveform setup timing (

DS) and hold timing (

DH) when differential data strobe is enabled is referenced from

the crosspoint of DQS,DQS# or UDQS,UDQS# or LDQS,LDQS# as shown in Figure 70.

6. Input waveform timing is referenced to the crossing point level (V

) of two input signals (V

and V

) applied to the

device under test, where V

is the "true" input signal and V

is the "complementary" input signal shown in Figure 72.

7. See "Input Slew Rate Derating" on page 79.

Table 22: AC Input Test Conditions

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Input setup timing measurement reference level
BA1-BA0, A0-A12, CS#, RAS#, CAS#, WE#, ODT, DM,
UDM, LDM and CKE

See Note 2

1, 2,

Input hold timing measurement reference level
BA1-BA0, A0-A12, CS#, RAS#, CAS#, WE#, ODT, DM,
UDM, LDM and CKE

See Note3

1, 3,

Input timing measurement reference level (single-ended)
DQS for x4x8; UDQS, LDQS for x16

REF

(

)

Q*0.49

Q*0.51

1, 4

Input timing measurement reference level (differential)
CK, CK# for x4,x8,x16
DQS, DQS# for x4,x8; RDQS, RDQS# for x8
UDQS, UDQS#, LDQS, LDQS# for x16

(

)

1, 5, 6

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Input Slew Rate Derating

For all input signals the total

IS (setup time) and

(hold time) required is calculated by adding the data
sheet

IS(base) and

IH(base) value to the

IS and

derating value respectively. Example:

IS (total setup

time) =

IS(base) +

Setup (

IS) nominal slew rate for a rising signal is

defined as the slew rate between the last crossing of
V

REF

(

) and the first crossing of V

(

)min. Setup

(

IS) nominal slew rate for a falling signal is defined as

the slew rate between the last crossing of V

REF

) and

the first crossing of V

)

MAX

. If the actual signal is

always earlier than the nominal slew rate line between
shaded `V

REF

) to AC region', use nominal slew rate

for derating value (Figure 65 on page 80) If the actual
signal is later than the nominal slew rate line anywhere
between shaded `V

REF

) to ac region', the slew rate of

a tangent line to the actual signal from the AC level to
DC level is used for derating value (Figure 66 on
page 80)

Hold (

IH) nominal slew rate for a rising signal is

defined as the slew rate between the last crossing of
V

(

)

MAX

and the first crossing of V

REF

). Hold

(

IH) nominal slew rate for a falling signal is defined as

the slew rate between the last crossing of V

(

)

MIN

and the first crossing of V

REF

). If the actual signal is

always later than the nominal slew rate line between
shaded `dc to V

REF

(

) region', use nominal slew rate

for derating value (Figure 67 on page 81) If the actual
signal is earlier than the nominal slew rate line any-
where between shaded `dc to V

REF

(

) region', the slew

rate of a tangent line to the actual signal from the dc
level to V

REF

(

) level is used for derating value

(Figure 68 on page 81)

Although for slow slew rates the total setup time

might be negative (i.e. a valid input signal will not have
reached V

(

) at the time of the rising clock tran-

sition) a valid input signal is still required to complete
the transition and reach V

(

)).

For slew rates in between the values listed in

Table 23, the derating values may obtained by linear
interpolation.

Table 23: Setup and Hold Time Derating Values

CK,CK# DIFFERENTIAL SLEW RATE

2.0 V/NS

1.5 V/NS

1.0 V/NS

UNITS

Command/

Address Slew

rate

(V/ns)

4.0

+187

+94

+217

+124

+247

+154

3.5

+179

+89

+209

+119

+239

+149

3.0

+167

+83

+197

+113

+227

+143

2.5

+150

+75

+180

+105

+210

+135

2.0

+125

+45

+155

+75

+185

+105

1.5

+83

+21

+113

+51

+143

+81

1.0

+30

+60

0.9

-11

-14

+19

+16

+49

+46

0.8

-25

-31

-1

+35

+29

0.7

-43

-54

-13

-24

+17

0.6

-67

-83

-37

-53

-7

-23

0.5

-110

-125

-80

-95

-50

-65

0.4

-175

-188

-145

-158

-115

-128

0.3

-285

-292

-255

-262

-225

-232

0.25

-350

-375

-320

-345

-290

-315

0.2

-525

-500

-495

-470

-465

-440

0.15

-800

-708

-770

-678

-740

-648

0.1

-1450

-1125

-1420

-1095

-1390

-1065

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Figure 65: Nominal Slew Rate for

Figure 66: Tangent Line for

tIH

tIS

tIH

Setup Slew Rate

Rising Signal

Falling Signal

Delta TF

Delta TR

REF(dc) - Vil(ac)max

Delta TF

Vih(ac)min -

REF(dc)

Delta TR

DDQ

IH(ac)

min

IH(dc)

min

REF(dc)

IL(dc)

max

IL(ac)

max

tIS

nominal slew

rate

nominal
slew rate

VREF to ac
region

VREF to ac

region

tIH

tIS

tIH

Setup Slew Rate

Rising Signal

Delta TF

Delta TR

tangent line[Vih(ac)min -

REF(dc)]

Delta TR

DDQ

IH(ac)

min

IH(dc)

min

REF(dc)

IL(dc)

max

IL(ac)

max

tIS

tangent

REF

to ac

region

REF

to ac

region

line

nominal
line

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Figure 67: Nominal Slew Rate for

Figure 68: Tangent Line for

tIH

tIS

tIH

Delta TR

Delta TF

DDQ

IH(ac)

min

IH(dc)

min

REF(dc)

IL(dc)

max

IL(ac)

max

tIS

nominal

slew rate

nominal
slew rate

dc to V

REF

region

dc to V

REF

region

tIH

tIS

tIH

Hold Slew Rate

Delta TF

Delta TR

tangent line [ Vih(dc)min -

REF(dc) ]

Delta TF

DDQ

IH(ac)

min

IH(dc)

min

REF(dc)

IL(dc)

max

IL(ac)

max

tIS

tangent

dc to V

REF

region

dc to V

REF

region

line

nominal
line

Falling Signal

Hold Slew Rate

tangent line [

REF(dc) - Vil(dc)max ]

Delta TR

Rising Signal

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Figure 69: AC Input Test Signal Waveform Command/Address pins

Figure 70: AC Input Test Signal Waveform for Data with DQS,DQS# (differential)

REF

(DC)

MAX

(AC)

MAX

(DC)

MIN

(AC)

MIN

SWING (MAX)

tIS

Logic Levels

REF

Levels

tIH

tIS

tIH

tIS

tIH

tIS

tIH

CK#

REF

(DC)

MAX

(AC)

MAX

(DC)

MIN

(AC)

MIN

SWING (MAX)

DQS#

DQS

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

Logic Levels

REF

Levels

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Figure 71: AC Input Test Signal Waveform for Data with DQS (single-ended)

Figure 72: AC Input Test Signal Waveform (differential)

REF

(DC)

MAX

(AC)

MAX

(DC)

MIN

(AC)

MIN

SWING (MAX)

DQS

REF

Logic Levels

REF

Levels

REF

Levels

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

SWING

Crossing Point

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Power and Ground Clamp Characteristics

Power and ground clamps are provided on the fol-

lowing input-only pins: BA1-BA0, A0-A12, CS#, RAS#,
CAS#, WE#, ODT, and CKE.

Figure 73: Input Clamp Characteristics

Table 24: Input Clamp Characteristics

VOLTAGE ACROSS CLAMP

(V)

MINIMUM POWER CLAMP CURRENT

(mA)

MINIMUM GROUND CLAMP

CURRENT (mA)

0.0

0.1

0.0

0.2

0.0

0.3

0.0

0.4

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.8

0.1

0.9

1.0

2.5

1.1

4.7

1.2

6.8

1.3

9.1

1.4

11.0

1.5

13.5

1.6

16.0

1.7

18.2

1.8

21.0

0.0

5.0

10.0

15.0

20.0

25.0

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

Voltage Across Clamp (V)

Minimum Clamp Cur

r
e

nt (mA)

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AC Overshoot/Undershoot Specification

Figure 74: Overshoot

Figure 75: Undershoot

Table 25: Address and Control Pins

Applies to BA1-BA0, A0-A12, CS#, RAS#, CAS#, WE#, CKE, ODT

PARAMETER

SPECIFICATION

-5, -5E

-37E

Maximum peak amplitude allowed for overshoot area (See Figure 74)

0.9V

Maximum peak amplitude allowed for undershoot area (See Figure 75)

0.9V

Maximum overshoot area above V

(See Figure 74)

0.75V-ns

0.56V-ns

Maximum undershoot area below V

(See Figure 75)

0.75V-ns

0.56V-ns

Table 26: Clock, Data, Strobe, and Mask Pins

Applies to DQ0DQxx, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, LDM

PARAMETER

SPECIFICATION

-5, -5E

-37E

Maximum peak amplitude allowed for overshoot area (See Figure 74)

0.9V

Maximum peak amplitude allowed for undershoot area (See Figure 74)

0.9V

Maximum overshoot area above V

Q (See Figure 74)

0.38V-ns

0.28V-ns

Maximum undershoot area below V

Q (See Figure 75)

0.38V-ns

0.28V-ns

Overshoot Area

Maximum Amplitude

SS/

Volts

Time (ns)

(V)

Undershoot Area

Maximum Amplitude

SS/

Volts

Time (ns)

(V)

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Output Electrical Characteristics and Operating Conditions

NOTE:

1. The typical value of V

(AC) is expected to be about 0.5 x V

Q of the transmitting device and V

(AC) is expected to

track variations in V

Q. V

(AC) indicates the voltage at which differential output signals must cross.

Figure 76: Differential Output Signal Levels

Table 27: Differential AC Output Parameters

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

AC Differential Cross-Point Voltage

(

)

0.50 x V

Q - 125

0.50 x V

Q + 125

AC Differential Voltage Swing

SWING

1.0

SWING

Crossing Point

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NOTE:

1. For I

(DC); V

Q = 1.7V, V

OUT

= 1420mV. (V

OUT

- V

Q)/I

must be less than 21

for values of V

OUT

between V

and V

Q - 280mV.

2. For I

(DC); V

Q = 1.7V, V

OUT

= 280mV. V

OUT

must be less than 21

for values of V

OUT

between 0V and 280mV.

3. The DC value of V

REF

applied to the receiving device is set to V

4. The values of I

(DC) and I

(DC) are based on the conditions given in Notes 1 and 2. They are used to test device drive

current capability to ensure V

(MIN) plus a noise margin and V

(MAX) minus a noise margin are delivered to an

SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (See output IV
curves) along a 21

load line to define a convenient driver current for measurement.

NOTE:

1. Absolute specifications: 0°C

case

+85°C

;

Q = +1.8V ±0.1V, V

= +1.8V ±0.1V.

2. Impedance measurement condition for output source DC current: V

Q = 1.7V; V

OUT

= 1420mV; (V

OUT

- V

Q)/I

must

be less than 23.4

for values of V

OUT

between V

Q and V

Q - 280mV. Impedance measurement condition for output

sink DC current: V

Q = 1.7V; V

OUT

= 280mV; V

OUT

must be less than 23.4

for values of V

OUT

between 0V and

280mV.

3. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage.
4. Output slew rate for falling and rising edges is measured between V

- 250mV and V

+ 250mV for single ended sig-

nals. For differential signals (e.g. DQS - DQS#) output slew rate is measured between DQS - DQS# = -500mV and DQS# -
DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.

5. The absolute value of the slew rate as measured from V

(DC)MAX to V

(DC) MIN is equal to or greater than the slew

rate as measured from V

(AC) MAX to V

(AC) MIN. This is guaranteed by design and characterization.

Figure 77: Output Slew Rate Load

Table 28: Output DC Current Drive

PARAMETER

SYMBOL

VALUE

UNITS

NOTES

Output Minimum Source DC Current

-13.4

1,3,4

Output Minimum Sink DC Current

13.4

2,3,4

Table 29: Output Characteristics

PARAMETER

SYMBOL

MIN

NOM

MAX

UNITS

NOTES

Output impedance

12.6

23.4

1,2

Pull-up and Pull-down mismatch

1,2,3

Output slew rate

1.5

V/ns

1,4,5

Output
(V

OUT

)

Reference

Point

TT =

Q/2

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Full Strength Pull-Down Driver Characteristics

Figure 78: Full Strength Pull-Down Characteristics

Pull-down Characteristics

0.00

20.00

40.00

60.00

80.00

100.00

120.00

0.0

0.5

1.0

1.5

Vout (V)

Iout (mA)

Table 30: Pulldown Current (mA)

VOLTAGE (V)

MINIMUM

NOMINAL

MAXIMUM

0.0

0.00

0.1

4.3

5.63

7.90

0.2

8.6

11.3

15.90

0.3

12.9

16.52

23.80

0.4

17.2

22.19

31.80

0.5

21.1

27.59

39.70

0.6

24.27

32.39

47.70

0.7

26.01

36.45

55.00

0.8

27.43

40.38

62.30

0.9

28.4

44.01

69.40

1.0

29.16

47.01

75.30

1.1

29.79

49.63

80.50

1.2

30.32

51.71

84.60

1.3

30.79

53.32

87.70

1.4

31.19

54.9

90.80

1.5

31.6

56.03

92.90

1.6

31.93

57.07

94.90

1.7

33.24

58.16

97.00

1.8

32.6

59.27

99.10

1.9

33.02

60.35

101.10

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Full Strength Pull-Up Driver Characteristics

Figure 79: Full Strength Pull-up Characteristics

Pull-up Characteristics

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

0.5

1.0

1.5

VDDQ - Vout (V)

Iout (mA)

Table 31: Pull-Up Current (mA)

VOLTAGE (V)

MINIMUM

NOMINAL

MAXIMUM

0.0

0.00

0.0

0.1

-4.3

-5.63

-7.9

0.2

-8.6

-11.3

-15.9

0.3

-12.9

-16.52

-23.8

0.4

-17.2

-22.19

-31.8

0.5

-21.1

-27.59

-39.7

0.6

-24.27

-32.39

-47.7

0.7

-26.01

-36.45

-55.0

0.8

-27.43

-40.38

-62.3

0.9

-28.4

-44.01

-69.4

1.0

-29.16

-47.01

-75.3

1.1

-29.79

-49.63

-80.5

1.2

-30.32

-51.71

-84.6

1.3

-30.79

-53.32

-87.7

1.4

-31.19

-54.9

-90.8

1.5

-31.6

-56.03

-92.9

1.6

-31.93

-57.07

-94.9

1.7

-33.24

-58.16

-97.0

1.8

-32.6

-59.27

-99.1

1.9

-33.02

-60.35

-101.1

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

FBGA Package Capacitance

NOTE:

1. This parameter is sampled. V

= +1.8V ±0.1V, V

Q = +1.8V ±0.1V, V

REF

= V

, f = 100 MHz, T

CASE

= 25°C, V

OUT

(DC) =

Q/2, V

OUT

(peak to peak) = 0.1V. DM input is grouped with I/O pins, reflecting the fact that they are matched in load-

ing.

2. The input capacitance per pin group will not differ by more than this maximum amount for any given device.
3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given

device.

Table 32: Input Capacitance

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Input Capacitance: CK, CK#

CCK

1.0

2.0

Delta Input Capacitance: CK, CK#

CDCK

0.25

Input Capacitance: BA1-BA0, A0-A12, CS#, RAS#,
CAS#, WE#, CKE, ODT

1.0

2.0

Delta Input Capacitance: BA1-BA0, A0-A12, CS#,
RAS#, CAS#, WE#, CKE, ODT

CDI

0.25

Input/Output Capacitance: DQs, DQS, DM, NF

CIO

2.5

4.0

Delta Input/Output Capacitance: DQs, DQS, DM, NF

CDIO

0.5

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

Specifications and Conditions

Table 33: DDR2 I

Specifications and Conditions

Notes: 15; notes appear on page 92.

PARAMETER/CONDITION

SYMBOL

CONFIG

-37E

-5E

-5

UNITS

Operating one bank active-precharge current;

CK =

CK (I

RC =

RC (I

RAS =

RAS MIN (I

); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING.

x4, x8

x16

Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(I

), AL = 0;

CK =

CK (I

RC =

RC (I

RAS =

RAS MIN (I

RCD =

RCD (I

); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as I

4W.

x4, x8

x16

Precharge power-down current;

All banks idle;

CK =

CK (I

); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING.

x4, x8, x16

Precharge quiet standby current;

All banks idle;

CK =

CK (I

); CKE is HIGH, CS# is HIGH; Other

control and address bus inputs are STABLE; Data bus inputs are
FLOATING.

x4, x8

x16

Precharge standby current;

All banks idle;

CK =

CK (I

); CKE is HIGH, CS# is HIGH; Other

control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.

x4, x8

x16

Active power-down current;
All banks open;

CK =

CK (I

); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING.

Fast PDN Exit

MR[12] = 0

Slow PDN Exit

MR[12] = 1

Active standby current;

All banks open;

CK =

CK(I

RAS =

RAS MAX (I

RP =

RP(I

); CKE is HIGH, CS# is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING.

x4, x8

x16

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL (I

AL = 0;

CK =

CK (I

RAS =

RAS MAX (I

RP =

RP (I

);

CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.

x4, x8

160

125

x16

180

140

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4,

CL = CL (I

), AL = 0;

CK =

CK (I

RAS =

RAS MAX (I

RP =

RP (I

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.

x4, x8

150

115

x16

160

120

Burst refresh current;

CK =

CK (I

); Refresh command at every

RFC (I

) interval;

CKE is HIGH, CS# is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.

x4, x8

170

165

x16

170

165

256Mb: x4, x8, x16

DDR2 SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

NOTE:

1. I

specifications are tested after the device is properly initialized. 0°C

CASE

85°C.

= +1.8V ±0.1V, V

Q = +1.8V ±0.1V, V

L= +1.8V ±0.1V, V

REF

Q/2.

2. Input slew rate is specified by AC Parametric Test Conditions.
3. I

parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#. I

values must be met with

all combinations of EMR bits 10 and 11.

5. Definitions for I

Conditions:

LOW is defined as V

(AC) (MAX).

HIGH is defined as V

(AC) (MIN).

STABLE is defined as inputs stable at a HIGH or LOW level.
FLOATING is defined as inputs at V

REF

= V

Q/2.

SWITCHING is defined as inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals.
Switching is defined as inputs changing between HIGH and LOW every other data transfer (once per clock) for
DQ signals not including masks or strobes.

Self refresh current;
CK and CK# at 0V; CKE

0.2V; Other control and address bus

inputs are FLOATING; Data bus inputs are FLOATING.

x4, x8, x16

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL (I

AL =

RCD (I

)-1 x

CK (I

);

CK =

CK (I

RC =

RC(I

RRD =

RRD(I

RCD =

RCD(I

); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are STABLE
during DESELECTs; Data bus inputs are SWITCHING; See I

Conditions for detail.

x4, x8

240

230

x16

240

230

Table 33: DDR2 I

Specifications and Conditions (Continued)

Notes: 15; notes appear on page 92.

PARAMETER/CONDITION

SYMBOL

CONFIG

-37E

-5E

-5

UNITS

Table 34: General I

Parameters

PARAMETER

-37E

-5E

-5

UNITS

CL (I

)

RCD (I

)

RC (I

)

RRD (I

) - x4/x8

7.5

RRD (I

) - x16

CK (I

)

3.75

RAS MIN (I

)

RAS MAX (I

)

70,000

RP (I

)

RFC (I

)

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DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

7 Conditions

The detailed timings are shown below for I

Changes will be required if timing parameter changes
are made to the specification.

NOTE:

1. Legend: A = active; RA = read auto precharge; D = deselect.

2. All banks are being interleaved at minimum

RC (I

) without violating

RRD (I

) using a burst length of 4.

3. Control and address bus inputs are STABLE during DESELECTs.
4. I

OUT

= 0mA.

Table 35: I

7 Timing Patterns

All Bank Interleave Read operation

SPEED GRADE

IDD7 TIMING PATTERNS FOR x4/x8/x16

-5

A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D

-5E

A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D

-37E

A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

Table 36: AC Operating Conditions (Sheet 1 of 4)

Notes: 15; notes appear on page 98; 0°C

case

+85°C; V

Q = +1.8V ±0.1V, V

= +1.8V ±0.1V

AC CHARACTERISTICS

-37E

-5E

-5

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Clock

Clock cycle
time

CL = 4

CK (4)

3,750

8,000

5,000

8,000

5,000

8,000

16, 25

CL = 3

CK (3)

5,000

8,000

5,000

8,000

16, 25

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

Half clock period

MIN

(

CH,

CL)

MIN

(

CH,

CL)

MIN

(

CH,

CL)

Clock jitter

JIT

TBD

Dat

DQ output access time
from CK/CK#

-500

+500

-600

+600

-600

+600

Data-out high-impedance
window from CK/CK#

AC MAX

8, 9

Data-out low-impedance
window from CK/CK#

AC MIN

AC MAX

AC MIN

AC MAX

AC MIN

AC MAX

8, 10

DQ and DM input setup
time relative to DQS

Vref

350

400

7, 15,

DQ and DM input hold
time relative to DQS

Vref

350

400

7, 15,

DQ and DM input setup
time relative to DQS

VAC

100

150

7, 15,

DQ and DM input hold
time relative to DQS

VDC

225

275

7, 15,

DQ and DM input pulse
width (for each input)

DIPW

0.35

Data hold skew factor

QHS

400

450

DQDQS hold, DQS to
first DQ to go nonvalid,
per access

HP -

QHS

HP -

QHS

HP -

QHS

15, 17

Data valid output
window (DVW)

DVW

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

15,

256Mb: x4, x8, x16

DDR2 SDRAM

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Data Str

obe

DQS input high pulse
width

DQSH

0.35

DQS input low pulse
width

DQSL

0.35

DQS output access time
from CK/CK#

DQSCK

-450

+450

-500

+500

-500

+500

DQS falling edge to CK
rising setup time

DSS

0.2

DQS falling edge from CK
rising hold time

DSH

0.2

DQSDQ skew, DQS to last
DQ valid, per group, per
access

DQSQ

300

350

15, 17

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

DQS write preamble
setup time

WPRES

12, 13

DQS write preamble

WPRE

0.25

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write command to first
DQS latching transition

DQSS

WL -

0.25

WL +

0.25

WL -

0.25

WL +

0.25

WL -

0.25

WL +

0.25

Table 36: AC Operating Conditions (Sheet 2 of 4)

Notes: 15; notes appear on page 98; 0°C

case

+85°C; V

Q = +1.8V ±0.1V, V

= +1.8V ±0.1V

AC CHARACTERISTICS

-37E

-5E

-5

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

Comm

and and Addr

ess

Address and control input
pulse width for each
input

IPW

0.6

Address and control input
setup time

500

600

6, 22

Address and control input
hold time

500

600

6, 22

Address and control input
setup time

250

350

6, 22

Address and control input
hold time

375

475

6, 22

CAS# to CAS# command
delay

CCD

ACTIVE to ACTIVE (same
bank) command

ACTIVE bank a to ACTIVE
bank b command

RRD

(x4, x8)

7.5

RRD

(x16)

ACTIVE to READ or WRITE
delay

RCD

Four Bank Activate period

FAW

(x4, x8)

37.5

Four Bank Activate period

FAW

(x16)

ACTIVE to PRECHARGE
command

RAS

70,000

21, 34

Internal READ to
precharge command
delay

RTP

7.5

24, 28

Write recovery time

Auto precharge write
recovery + precharge time

DAL

WR +

Internal WRITE to READ
command delay

WTR

7.5

PRECHARGE command
period

PRECHARGE ALL
command period

RPA

RP +

LOAD MODE command
cycle time

MRD

CKE low to CK,CK#
uncertainty

DELAY

4.375

5.83

Table 36: AC Operating Conditions (Sheet 3 of 4)

Notes: 15; notes appear on page 98; 0°C

case

+85°C; V

Q = +1.8V ±0.1V, V

= +1.8V ±0.1V

AC CHARACTERISTICS

-37E

-5E

-5

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

Refr

esh

REFRESH to Active or
Refresh to Refresh
command interval

RFC

70,000

Average periodic refresh
interval

REFI

7.8

µs

Self

Exit self refresh to non-
READ command

XSNR

RFC

(MIN) +

RFC

(MIN) +

RFC

(MIN) +

Exit self refresh to READ
command

XSRD

200

Exit self refresh timing
reference

ISXR

250

350

6, 30

ODT turn-on delay

AOND

ODT turn-on

AON

(MIN)

(MAX) +

1,000

(MIN)

(MAX) +

1000

(MIN)

(MAX) +

1000

ODT turn-off delay

AOFD

2.5

ODT turn-off

AOF

(MIN)

(MAX) +

600

(MIN)

(MAX) +

600

(MIN)

(MAX) +

600

ODT turn-on (power-
down mode)

AONPD

(MIN) +

2000

CK +

(MAX) +

1,000

(MIN) +

2,000

2 x

CK +

(MAX) +

1000

(MIN) +

2,000

2 x

CK +

(MAX) +

1000

ODT turn-off (power-
down mode)

AOFPD

(MIN) +

2,000

2.5 x

(MAX) +

1,000

(MIN) +

2,000

2.5 x

(MAX) +

1,000

(MIN) +

2,000

2.5 x

(MAX) +

1,000

ODT to power-down
entry latency

ANPD

ODT power-down exit
latency

AXPD

r
-
D

Exit active power-down to
READ command,
MR[bit12=0]

XARD

tCK

Exit active power-down to
READ command,
MR[bit12=1]

XARDS

6 - AL

Exit precharge power-
down to any non-READ
command.

Exit precharge power-
down to READ command.

XPRD

6 - AL

CKE minimum high/low
time

CKE

Table 36: AC Operating Conditions (Sheet 4 of 4)

Notes: 15; notes appear on page 98; 0°C

case

+85°C; V

Q = +1.8V ±0.1V, V

= +1.8V ±0.1V

AC CHARACTERISTICS

-37E

-5E

-5

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

256Mb: x4, x8, x16

DDR2 SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

Notes

1. All voltages referenced to V

2. Tests for AC timing,

, and electrical AC and DC

characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and

tests may use a V

-to-V

swing

of up to 1.0V in the test environment and parame-
ter specifications are guaranteed for the specified
AC input levels under normal use conditions. The
minimum slew rate for the input signals used to
test the device is 1.0V/ns for signals in the range
between V

(AC) and V

(AC). Slew rates less

than 1.0V/ns require the timing parameters to be
derated as specified.

5. The AC and DC input level specifications are as

defined in the SSTL_18 standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. Command/Address minimum input slew rate is at

1.0V/ns. Command/Address input timing needs
to be derated if the slew rate is less than 1.0V/ns.
This is easily accommodated using

and the

Setup and Hold Time Derating Values table.

timing (

) is referenced from V

(

) for a rising

signal and V

(

) for a falling signal.

IH timing

(

) is referenced from V

(

) for a rising signal

and V

(

) for a falling signal. The timing table

also lists the

and

values for a 1.0V/ns slew

rate; these are the "base" values.

7. Data minimum input slew rate is at 1.0V/ns. Data

input timing needs to be derated if the slew rate is
less than 1.0V/ns. This is easily accommodated if
the timing is referenced from the logic trip points.

DS timing (

VAC

) is referenced from V

(AC) for

a rising signal and V

(AC) for a falling signal.

timing (

VDC

) is referenced from V

(DC) for a

rising signal and V

(

) for a falling signal. The

timing table also lists the

(

VDC

)and

(

VAC

) values for a 1.0V/ns slew rate.

If the DQS/DQS# differential strobe feature is not
enabled, timing is no longer referenced to the

crosspoint of DQS/DQS#. Data timing is now ref-
erenced to V

REF

, provided the DQS slew rate is not

less than 1.0V/ns. If the DQS slew rate is less than
1.0V/ns, then data timing is now referenced to
V

(

) for a rising DQS and V

(

) for a falling

DQS.

HZ and

LZ transitions occur in the same access

time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (

HZ) or begins driving (

LZ).

9. This maximum value is derived from the refer-

enced test load.

HZ (MAX) will prevail over

DQSCK (MAX) +

RPST (MAX) condition.

10.

LZ (MIN) will prevail over a

DQSCK (MIN) +

RPRE (MAX) condition.

11. The intent of the Don't Care state after completion

of the postamble is the DQS-driven signal should
either be high, low or High-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is if DQS
transitions high (above V

DC(min) then it must

not transition low (below V

(DC) prior to

DQSH(min).

12. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

13. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on

DQSS.

14. The refresh period is 64ms. This equates to an

average refresh rate of 7.8125µs. However, a
REFRESH command must be asserted at least
once every 70.3µs or

RFC (MAX). To ensure all

rows of all banks are properly refreshed, 8192
REFRESH commands must be issued every 64ms.

15. Referenced to each output group: x4 = DQS with

DQ0-DQ3; x8 = DQS with DQ0DQ7; x16 = LDQS
with DQ0DQ7; and UDQS with DQ8DQ15.

16. CK and CK# input slew rate must be 1V/ns ( 2

V/ns if measured differentially).

17. The data valid window is derived by achieving

other specifications -

HP. (

CK/2),

DQSQ, and

QH(

QH=

HP-

QHS). The data valid window der-

ates in direct proportion to the clock duty cycle
and a practical data valid window can be derived.

18.

JIT specification is currently TBD.

Output
(V

OUT

)

Reference

Point

TT =

Q/2

256Mb: x4, x8, x16

DDR2 SDRAM

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256Mb_DDR2_2.fm - Rev. C 5/04 EN

19. MIN(

CL,

CH) refers to the smaller of the actual

clock low time and the actual clock high time as
provided to the device (i.e. This value can be
greater than the minimum specification limits for

CL and

CH). For example,

CL and

CH are = 50

percent of the period, less the half period jitter
[

JIT(HP)] of the clock source, and less the half

period jitter due to cross talk [

JIT(cross talk)] into

the clock traces.

20.

HP (MIN) is the lesser of

CL minimum and

minimum actually applied to the device CK and
CK# inputs.

21. READs and WRITEs with auto precharge are

allowed to be issued before

RAS (MIN) is satisfied

since

RAS lockout feature is supported in DDR2

SDRAM.

22. V

DDR2 overshoot/undershoot. See "AC

Overshoot/Undershoot Specification" on page 86.

23.

DAL = (nWR) + (

RP/

CK): For each of the terms

above, if not already an integer, round to the next
highest integer.

CK refers to the application clock

period; nWR refers to the

WR parameter stored in

the MR[11,10,9]. Example: For -37E at

CK = 3.75

ns with

WR programmed to four clocks.

DAL = 4

+ (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks.

24. The minimum READ to internal PRECHARGE

time. This parameter is only applicable when

RTP/(2*

CK) > 1. If

RTP/(2*

CK) 1, then equa-

tion AL + BL/2 applies. Notwithstanding,

RAS

(MIN) has to be satisfied as well. The DDR2
SDRAM will automatically delay the internal PRE-
CHARGE command until

RAS (MIN) has been

satisfied.

25. Operating frequency is only allowed to change

during self refresh mode (See "Self Refresh" on
page 34), precharge power-down mode (See
"Power-Down Mode" on page 37), and system
reset condition (see "RESET Function (CKE LOW
Anytime)" on page 8.

26. ODT turn-on time

AON (MIN) is when the device

leaves high impedance and ODT resistance

begins to turn on. ODT turn-on time

AON (MAX)

is when the ODT resistance is fully on. Both are
measured from

AOND.

27. ODT turn-off time

AOF (MIN) is when the device

starts to turn off ODT resistance. ODT turn off
time

AOF (MAX) is when the bus is in high

impedance. Both are measured from

AOFD.

28. This parameter has a two clock minimum require-

ment at any

CK.

29.

DELAY is calculated from

IS +

CK +

IH so that

CKE registration LOW is guaranteed prior to CK,
CK# being removed in a system RESET condition.
"RESET Function (CKE LOW Anytime)" on page 8.

30.

ISXR is equal to

IS and is used for CKE setup time

during self refresh exit shown in Figure 31 on
page 36.

31. No more than 4 bank ACTIVE commands may be

issued in a given

FAW(min) period.

RRD(min)

restriction still applies. The

FAW(min) parameter

applies to all 8 bank DDR2 devices, regardless of
the number of banks already open or closed.

32. tRPA timing applies when the PRECHARGE(ALL)

command is issued, regardless of the number of
banks already open or closed. If a single-bank
PRECHARGE command is issued,

RP timing

applies.

RPA(min) applies to all 8-bank DDR2

devices.

33. Value is minimum pulse width, not the number of

clock registrations.

34. Applicable to Read cycles only. Write cycles gener-

ally require additional time due to Write recovery
time (

WR) during auto precharge.

35.

CKE (MIN) of 3 clocks means CKE must be regis-

tered on three consecutive positive clock edges.
CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registration.
Thus, after any CKE transition, CKE may not tran-
sition from its valid level during the time period of

IS + 2 *

CK +

IH.

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

100

Figure 80: Package Drawing 60-Ball (8mmx12mm) FBGA

NOTE:

All dimensions are in millimeters.

BALL A1 ID

1.3 MAX

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR
95.5% Sn, 3% Ag, 0.5% Cu
SOLDER BALL PAD: Ø .33mm

BALL A9

0.80 TYP

8.00 ±0.10

4.00 ±0.05

3.20 ±0.05

4.00 ±0.05

0.850 ±0.05

0.155 ±0.013

SEATING PLANE

8.00

6.40

1.80 ±0.05

CTR

0.10 C

60X

0.45

SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS Ø 0.42

12.00 ±0.10

BALL A1

BALL A1 ID

0.80 TYP

6.00 ±0.05

256Mb: x4, x8, x16

DDR2 SDRAM

09005aef80b12a05

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb_DDR2_2.fm - Rev. C 5/04 EN

101

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 81: Package Drawing 84-Ball (8mmx14mm) FBGA

NOTE:

All dimensions are in millimeters.

Data Sheet Designation

Preliminary: Initial characterization limits, subject

to change upon full characterization of production
devices.

BALL #1 ID

SEATING PLANE

0.850 ±0.05

1.80 ±0.05

CTR

0.155 ±0.013

0.10 C

1.3 MAX

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag or
96.5% Sn, 3% Ag, 0.5% Cu
SOLDER BALL PAD: Ø 0.33mm

3.20 ±0.05 4.00 ±0.05

8.00 ±0.10

BALL A1 ID

11.20

5.60 ±0.05

BALL A9

BALL A1

SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS Ø0.42

84X Ø0.45

14.00 ±0.10

7.00 ±0.05

0.80 TYP

0.80

TYP

6.40

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