PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

09005aef80ca3ad1
128Mbx16Mobile_Addendum.fm - Rev. A 6/03 EN

128Mb: x16

Mobile SDRAM Addendum

PRELIMINARY

SYNCHRONOUS
DRAM

MT48LC8M16LFFF 2 MEG x 16 x 4 BANKS
MT48G8M16LFFF 2 MEG x 16 x 4 BANKS
MT48V8M16LFFF 2 MEG x 16 x 4 BANKS

This data sheet is an addendum. The complete 128Mb Mobile
SDRAM data sheet is at:

http://www.micron.com/products/

datasheet.jsp?path=/DRAM/Mobile&fileID=581

Features

· Temperature Compensated Self Refresh (TCSR)
· Fully synchronous; all signals registered on positive

edge of system clock

· Internal pipelined operation; column address can

be changed every clock cycle

· Internal banks for hiding row access/precharge
· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge, includes CONCURRENT auto

precharge, and Auto Refresh Modes

· Self Refresh Mode; standard and low power
· 64ms, 4,096-cycle refresh
· LVTTL-compatible inputs and outputs
· Low voltage power supply
· Partial Array Self Refresh power-saving mode
· Extended mode register (must be programmed)

NOTE:

1. IT supported only in LX version.

2. Lead-free.

Part Number Example:

MT48G8M16LFFF-8 XT

Figure 1: 54-Ball FBGA Pin Assignment

(Top View)

OPTIONS

MARKING

· V

3.3V

3.0V

2.5V/2.5V-1.8V

· Configurations

8 Meg x 16 (2 Meg x 16 x 4 banks)

8M16

· Self Refresh

Supported

Not Supported

· Package/Ball out

Plastic Package
54-ball FBGA (8mm x 9mm)

54-ball FBGA (8mm x 9mm)

· Timing (Cycle Time)

8ns @ CL = 3 (125 MHz)

-8

10ns @ CL = 3 (100 MHz)

-10

· Operating Temperature Range

Mobile (-25°C to +75°C)

Industrial(-40°C to +85°C)

Table 1:

Address Table

8 MEG x16

Configuration

2 Meg x 16 x 4 banks

Refresh Count

Row Addressing

4K (A0A11)

Bank Addressing

4 (BA0, BA1)

Column Addressing

512 (A0A8)

Table 2:

Key Timing Parameters

Maximums, based on

CK; CL = CAS (READ) latency

SPEED

GRADE

CLOCK

FREQUENCY

ACCESS TIME

RCD

CL = 1 CL = 2 CL = 3

-8

125 MHz

6ns

20ns 20ns

-10

100 MHz

6ns

20ns 20ns

-8

100 MHz

7ns

20ns 20ns

-10

83 MHz

7ns

20ns 20ns

-8

50 MHz

18ns

20ns 20ns

-10

40 MHz

18ns

20ns 20ns

1 2 3 4 5 6 7 8

Top View

(Ball Down)

DQ14

DQ12

DQ10

DQ8

UDQM

NC/A12

DQ15

DQ13

DQ11

DQ9

CLK

A11

CKE

CAS#

BA0

DQ0

DQ2

DQ4

DQ6

LDQM

RAS#

BA1

DQ1

DQ3

DQ5

DQ7

WE#

CS#

A10

128Mb: x16

Mobile SDRAM Addendum

PRELIMINARY

09005aef80ca3ad1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16Mobile_Addendum.fm - Rev. A 6/03 EN

NOTE:

1. Lead-free package.

General Description

The Micron® 128Mb SDRAM is a high-speed

CMOS, dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x16's 33,554,432-bit banks is orga-
nized as 4,096 rows by 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0-A11(x16) select the row).
The address bits registered coincident with the READ
or WRITE command are used to select the starting col-
umn location for the burst access.

The SDRAM provides for programmable read or

write burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.

The 128Mb SDRAM uses an internal pipelined

architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless high-speed,
random-access operation.

The 128Mb SDRAM is designed to operate in 3.3V or

3.0V or 2.5V low-power memory systems. An auto
refresh mode is provided, along with a power-saving,
power-down mode. All inputs and outputs are LVTTL-
compatible.

SDRAMs offer substantial advances in DRAM oper-

ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access.

Table 3:

128Mb SDRAM Part Numbers

PART NUMBER

ARCHITECTURE

PACKAGE

MT48LC8M16LFFF-xx

3.3V / 3.3V

8 Meg x 16

54-BALL FBGA

MT48LC8M16LFBF-xx

3.3V / 3.3V

8 Meg x 16

54-BALL FBGA

MT48G8M16LFFF-xx

3.0V / 3.0V

8 Meg x 16

54-BALL FBGA

MT48G8M16LFBF-xx

3.0V / 3.0V

8 Meg x 16

54-BALL FBGA

MT48G8M16LXFF-xx

3.0V / 3.0V

8 Meg x 16

54-BALL FBGA

MT48G8M16LXBF-xx

3.0V / 3.0V

8 Meg x 16

54-BALL FBGA

MT48V8M16LFFF-xx

2.5V / 2.5V-1.8V

8 Meg x 16

54-BALL FBGA

MT48V8M16LFBF-xx

2.5V / 2.5V-1.8V

8 Meg x 16

54-BALL FBGA

128Mb: x16

Mobile SDRAM Addendum

PRELIMINARY

09005aef80ca3ad1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16Mobile_Addendum.fm - Rev. A 6/03 EN

Table 4:

Ball Descriptions

54-BALL FBGA

SYMBOL

TYPE

DESCRIPTION

CLK

Input

Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.

CKE

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers, including
CLK, are disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.

CS#

Input

Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.

F7, F8, F9

CAS#, RAS#,

WE#

Input

Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the command
being entered.

E8, F1

LDQM,
UDQM

Input

Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. Input data is masked
during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock
latency) when during a READ cycle. LDQM corresponds to DQ0DQ7, UDQM
corresponds to DQ8DQ15. LDQM and UDQM are considered same state when
referenced as DQM.

G7, G8

BA0, BA1

Input

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. These pins also provide the op-
code during a LOAD MODE REGISTER command

H7, H8, J8, J7,
J3, J2, H3, H2,

H1, G3, H9, G2

A0A11

Input

Address Inputs: A0A11 are sampled during the ACTIVE command (row- address
A0A11) and READ/WRITE command (column-address A0A8; with A10 defining
auto precharge) to select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to determine if all banks
are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The
address inputs also provide the op-code during a LOAD MODE REGISTER
command.

A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,

C1, B2, B1, A2

DQ0DQ15

I/O

Data Input/Output: Data bus

E2, G1

No Connect: These pins should be left unconnected. G1 is a no connect for this
part but may be used as A12 in future designs.

A7, B3, C7, D3

Supply DQ Power: Provide isolated power to DQs for improved noise immunity.

A3, B7, C3, D7,

Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

A9, E7, J9

Supply Power Supply: Voltage dependant on option.

A1, E3, J1

Supply Ground.

128Mb: x16

Mobile SDRAM Addendum

PRELIMINARY

09005aef80ca3ad1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16Mobile_Addendum.fm - Rev. A 6/03 EN

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Table 5:

Absolute Maximum Ratings Table

PARAMETER/CONDITION

MIN

MAX

UNITS

Voltage on V

Q Supply

Relative to V

(3.3V)

-1

+4.6

Relative to V

(3.0V)

-1

+4.6

Relative to V

(2.5V)

-0.5

+3.6

Voltage on Inputs, NC or I/O Pins

Relative to V

(3.3V)

-1

+4.6

Relative to V

(3.0V)

-1

+4.6

Relative to V

(2.5V)

-0.5

+3.6

Operating Temperature

(Mobile; XT parts)

-25

+75

°C

(Industrial; IT parts)

-40

+85

°C

Storage Temperature (plastic)

-55 +150

°C

Power Dissipation

Table 6:

DC Electrical Characteristics and Operating Conditions LC Version

Notes appear on standard 128Mb Mobile SDRAM data sheet; Vdd/VddQ = +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

3.6

I/O Supply Voltage

3.6

Input High Voltage: Logic 1; All inputs

+ 0.3

Input Low Voltage: Logic 0; All inputs

-0.3

0.8

Data Output High Voltage: Logic 1; All inputs

2.4

Data Output LOW Voltage: LOGIC 0; All inputs

0.4

Input Leakage Current:

Any Input 0V

£ V

(All other

pins not under test = 0V)

-5

µA

Output Leakage Current: DQs are disabled; 0V

£ V

OUT

£ V

-5

µA

Table 7:

DC Electrical Characteristics and Operating Conditions G Version

Notes appear on standard 128Mb Mobile SDRAM data sheet; V

DDQ

= +3.0V ±0.4V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.6

3.4

I/O Supply Voltage

DDQ

2.6

3.4

Input High Voltage: Logic 1; All inputs

2.0

+ 0.3

Input Low Voltage: Logic 0; All inputs

-0.3

0.8

Data Output High Voltage: Logic 1; All inputs

2.4

Data Output Low Voltage: LOGIC 0; All inputs

0.4

Input Leakage Current:

Any input 0V

£ V

(All other pins

not under test = 0V)

-5

µA

Output Leakage Current: DQs are disabled; 0V

£ V

OUT

£ V

-5

µA

128Mb: x16

Mobile SDRAM Addendum

PRELIMINARY

09005aef80ca3ad1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16Mobile_Addendum.fm - Rev. A 6/03 EN

Table 8:

DC Electrical Characteristics and Operating Conditions V Version

Notes appear on standard 128Mb Mobile SDRAM data sheet; V

= 2.5 ±0.2V, V

Q = +2.5V ±0.2V or +1.8V ±0.15V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.3

2.7

I/O Supply Voltage

1.65

2.7

Input High Voltage: Logic 1; All inputs

1.25

+ 0.3

Input Low Voltage: Logic 0; All inputs

-0.3

+0.55

Data Output High Voltage: Logic 1; All inputs

Q - 0.2

Data Output Low Voltage: LOGIC 0; All inputs

0.2

Input Leakage Current:

Any input 0V

£ V

(All other

pins not under test = 0V)

-5

µA

Output Leakage Current: DQs are disabled; 0V

£ V

OUT

£ V

-5

µA

Table 9:

AC Electrical Characteristics and Operating Conditions

= +3.3V ±0.3V or +3.0V ±0.4V or +2.5V±0.2V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High Voltage: Logic 1; All inputs

1.4

Input Low Voltage: Logic 0; All inputs

0.4

128Mb: x16

Mobile SDRAM Addendum

PRELIMINARY

09005aef80ca3ad1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16Mobile_Addendum.fm - Rev. A 6/03 EN

Table 10: ELectrical Characteristics and Recommended AC Operating Conditions

Notes appear on standard 128Mb Mobile SDRAM data sheet

AC CHARACTERISTICS

-8

-10

UNITS NOTES

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Access time from CLK (pos.
edge)

CL = 3

AC (3)

CL = 2

AC (2)

CL = 1

AC (1)

Address hold time

Address setup time

2.5

CLK high-level width

CLK low-level width

Clock cycle time

CL = 3

CK (3)

CL = 2

CK (2)

CL = 1

CK (1)

CKE hold time

CKH

CKE setup time

CKS

2.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

2.5

Data-in hold time

Data-in setup time

2.5

Data-out high-impedance time CL = 3

HZ (3)

CL = 2

HZ (2)

CL = 1

HZ (1)

Data-out low-impedance time

Data-out hold time (load)

2.5

Data-out hold time (no load)

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

100

ACTIVE to READ or WRITE delay

RCD

Refresh period (4,096 rows)

REF

AUTO REFRESH period

RFC

100

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

RRD

Transition time

0.5

1.2

0.5

1.2

WRITE recovery time

Auto precharge mode

WR (a)

1 CLK +

7ns

1 CLK +

5ns

Manual precharge mode

WR (m)

Exit SELF REFRESH to ACTIVE command

XSR

100

128Mb: x16

Mobile SDRAM Addendum

PRELIMINARY

09005aef80ca3ad1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16Mobile_Addendum.fm - Rev. A 6/03 EN

Table 11: AC Functional Characteristics

Notes appear on standard 128Mb Mobile SDRAM data sheet

PARAMETER

SYMBOL

-8

-10 UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVE command

DAL

15, 21

Data-in to PRECHARGE command

DPL

16, 21

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH command

MRD

Data-out to high-impedance from PRECHARGE command

CL = 3

ROH(3)

CL = 2

ROH(2)

CL = 1

ROH(1)

Table 12: I

Specifications and Conditions x16

Notes appear on standard 128Mb Mobile SDRAM data sheet; V

= +3.3V ±0.3V or +3.0V ±0.4V or +2.5V±0.2V

PARAMETER/CONDITION

SYMBOL

-8

-10

UNITS

NOTES

Operating Current: Active Mode;

Burst = 2; READ or WRITE;

RC =

RC (MIN)

130

100

3, 18,

19, 32

Standby Current: Power-Down Mode;
All banks idle; CKE = LOW

350

µA

Standby Current: Active Mode;

CKE = HIGH; CS# = HIGH; All banks active after

RCD met;

No accesses in progress

3, 12,

19, 32

Operating Current: Burst Mode; Continuous burst;
READ or WRITE; All banks active

100

3, 18,

19, 32

Auto Refresh Current
CKE = HIGH; CS# = HIGH

RFC =

RFC (MIN)

210

170

3, 12, 18, 19,

32, 33

RFC = 15.625µs

128Mb: x16

Mobile SDRAM Addendum

PRELIMINARY

09005aef80ca3ad1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16Mobile_Addendum.fm - Rev. A 6/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Table 13: I

Self Refresh Current Options x16 (IT Only)

Notes appear on standard 128Mb Mobile SDRAM data sheet; V

= +3.3V ±0.3V or +3.0V ±0.4V or +2.5V±0.2V

TEMPERATURE COMPENSATED SELF REFRESH

MAX

TEMPERATURE

-8 AND -10

UNITS

NOTES

PARAMETER/CONDITION

Self Refresh Current:
CKE < 0.2V

800

µA

500

µA

350

µA

300

µA

Table 14: Capacitance

Notes appear on standard 128Mb Mobile SDRAM data sheet

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Input Capacitance: CLK

2.0

4.0

Input Capacitance: All other input-only pins

2.0

5.0

Input/Output Capacitance: DQs

3.5

6.0

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Document Outline

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