Document Outline
- Features
- Options
- Pin Assignment
- 16MB (x16) SDRAM Part Number
- Key Timing Parameters
- General Description
- Table of Contents
- Functional Block Diagram - 1 Meg x 16 SDRAM
- Pin Descriptions
- Functional Description
- Initialization
- Register Definition
- Mode Register
- Burst Length
- Burst Type
- CAS Latency
- Operating Mode
- Write Burst Mode
- Figure 1 Mode Register Definition
- Table 1 Burst Definition
- Figure 2 CAS Latency
- Table 2 CAS Latency
- Commands
- Command Inhibit
- No Operation (NOP)
- Load Mode Register
- Active
- Read
- Write
- Precharge
- Auto Precharge
- Burst Terminate
- Auto Refresh
- Self Refresh
- Truth Table 1 - Commands and DQM Operation
- Operation
- Bank/Row Activation
- READs
- WRITEs
- Precharge
- Power-Down
- Clock Suspend
- Burst Read/Single Write
- Figure 3 Activating a Specific Row in a Specific Bank
- Figure 4 Example
- Figure 5 READ Command
- Figure 6 CAS Latency
- Figure 7 Consecutive READ Bursts
- Figure 8 Random READ Accesses
- Figure 9 READ to WRITE
- Figure 10 READ to WRITE with Extra Clock Cycle
- Figure 11 READ to PRECHARGE
- Figure 12 Terminating a READ Burst
- Figure 13 WRITE Command
- Figure 14 WRITE Burst
- Figure 15 WRITE to WRITE
- Figure 16 Random WRITE Cycles
- Figure 17 WRITE to READ
- Figure 18 WRITE to PRECHARGE
- Figure 19 Terminating a WRITE Burst
- Figure 20 PRECHARGE Command
- Figure 21 Power-Down
- Figure 22 Clock Suspend During WRITE Burst
- Figure 23 Clock Suspend During READ Burst
- Concurrent Auto Precharge
- Figure 24 READ with AUTO PRECHARGE Interrupted by a READ
- Figure 25 READ with AUTO PRECHARGE Interrupted by a WRITE
- Figure 26 WRITE with AUTO PRECHARGE Interrupted by a READ
- Figure 27 WRITE with AUTO PRECHARGE Interrupted by a WRITE
- Truth Table 2 - CKE
- Truth Table 3 - Current State Bank n, Command to Bank n
- Truth Table 4 - Current State Bank n, Command to Bank m
- Absolute Maximum Ratings
- DC Electrical Characteristics and Operating Conditions
- IDD Specifications and Conditions
- Capacitance
- Electrical Characteristics and Recommended AC Operating Conditions
- AC Functional Characteristics
- Notes
- Initialize and Load Mode Register
- Power-Down Mode
- Clock Suspend Mode
- Auto Refresh Mode
- Self Refresh Mode
- Single Read - Without Auto Precharge
- Read - Without Auto Precharge
- Read - With Auto Precharge
- Alternating Bank Read Accesses
- Read - Full-Page Burst
- Read - DQM Operation
- Single Write - Without Auto Precharge
- Write - Without Auto Precharge
- Write - With Auto Precharge
- Alternating Bank Read Accesses
- Write - Full-Page Burst
- Write - DQM Operation
- 50-Pin Plastic TSOP (400 mil)
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
1
16Mb: x16
IT SDRAM
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
SETUP
HOLD
CL = 3**
-6
166 MHz
5.5ns
2ns
1ns
-7
143 MHz
5.5ns
2ns
1ns
-8A
125 MHz
6ns
2ns
1ns
*Off-center parting line
**CL = CAS (READ) latency
1 Meg x 16
Configuration
512K x 16 x 2 banks
Refresh Count
2K or 4K
Row Addressing
2K (A0-A10)
Bank Addressing
2 (BA)
Column Addressing
256 (A0-A7)
SYNCHRONOUS
DRAM
MT48LC1M16A1 SIT - 512K x 16 x 2 banks
INDUSTRIAL TEMPERATURE
For the latest data sheet, please refer to the Micron Web site:
www.micronsemi.com/datasheets/sdramds.html
PIN ASSIGNMENT (Top View)
50-Pin TSOP
FEATURES
PC100 functionality
Fully synchronous; all signals registered on
positive edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
1 Meg x 16 - 512K x 16 x 2 banks architecture with
11 row, 8 column addresses per bank
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge Mode, includes CONCURRENT
AUTO PRECHARGE
Self Refresh and Adaptable Auto Refresh Modes
- 32ms, 2,048-cycle refresh or
- 64ms, 2,048-cycle refresh or
- 64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Single +3.3V 0.3V power supply
Supports CAS latency of 1, 2 and 3
Industrial temperature range: -40C to +85C
OPTIONS
MARKING
Configuration
1 Meg x 16 (512K x 16 x 2 banks)
1M16A1
Plastic Package - OCPL*
50-pin TSOP (400 mil)
T G
Timing (Cycle Time)
6ns (166 MHz)
-6
7ns (143 MHz)
-7
8ns (125 MHz)
-8A
Refresh
2K or 4K with Self Refresh Mode at 64ms
S
Operating Temperature
-40C to +85C
IT
Part Number Example:
MT48LC1M16A1TG-7SIT
Note: The # symbol indicates signal is active LOW.
V
DD
DQ0
DQ1
VssQ
DQ2
DQ3
V
DD
Q
DQ4
DQ5
VssQ
DQ6
DQ7
V
DD
Q
DQML
WE#
CAS#
RAS#
CS#
BA
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
VssQ
DQ13
DQ12
V
DD
Q
DQ11
DQ10
VssQ
DQ9
DQ8
V
DD
Q
NC
DQMH
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
16MB (X16) SDRAM PART NUMBER
PART NUMBER
ARCHITECTURE
MT48LC1M16A1TG SIT
1 Meg x 16
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
2
16Mb: x16
IT SDRAM
precharge that is initiated at the end of the burst sequence.
The 1 Meg x 16 SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This archi-
tecture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be changed
on every clock cycle to achieve a high-speed, fully random
access. Precharging one bank while accessing the alter-
nate bank will hide the PRECHARGE cycles and provide
seamless, high-speed, random-access operation.
The 1 Meg x 16 SDRAM is designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operat-
ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between inter-
nal banks in order to hide precharge time, and the capability
to randomly change column addresses on each clock cycle
during a burst access.
GENERAL DESCRIPTION
The 16Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 16,777,216 bits. It is
internally configured as a dual 512K x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 512K x
16-bit banks is organized as 2,048 rows by 256 columns by
16 bits. Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA selects the bank, A0-A10 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page,
with a burst terminate option. An AUTO PRECHARGE
function may be enabled to provide a self-timed row
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
3
16Mb: x16
IT SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 1 Meg x 16 ................. 3
Pin Descriptions ........................................................ 4
Functional Description ........................................ 5
Initialization ........................................................ 5
Register Definitions ............................................. 5
Mode Register ................................................ 5
Burst Length .............................................. 5
Burst Type ................................................. 5
CAS Latency .............................................. 7
Operating Mode ....................................... 7
Write Burst Mode ..................................... 7
Commands .............................................................. 8
Truth Table 1 (Commands and DQM Operation)
.............. 8
Command Inhibit ............................................... 9
No Operation (NOP) .......................................... 9
Load Mode Register ............................................ 9
Active .................................................................. 9
Read
.................................................................. 9
Write .................................................................. 9
Precharge ............................................................. 9
Auto Precharge .................................................... 9
Burst Terminate ................................................... 9
Auto Refresh ........................................................ 10
Self Refresh .......................................................... 10
Operation ................................................................ 11
Bank/Row Activation ......................................... 11
Reads .................................................................. 12
Writes .................................................................. 18
Precharge ............................................................. 20
Power-Down ....................................................... 20
Clock Suspend .................................................... 21
Burst Read/Single Write ...................................... 21
Concurrent Auto Precharge ................................ 22
Truth Table 2 (CKE)
................................................... 24
Truth Table 3 (Current State, Same Bank)
....................... 25
Truth Table 4 (Current State, Different Bank)
................... 27
Absolute Maximum Ratings .................................... 29
DC Electrical Characteristics and
Operating Conditions ........................................... 29
I
DD
Specifications and Conditions .......................... 29
Capacitance .............................................................. 30
AC Electrical Characteristics (Timing Table) .... 30
Timing Waveforms
Initialize and Load Mode Register ...................... 33
Power-Down Mode ............................................ 34
Clock Suspend Mode .......................................... 35
Auto Refresh Mode ............................................. 36
Self Refresh Mode ............................................... 37
Reads
Read - Single Read ......................................... 38
Read - Without Auto Precharge .................... 39
Read - With Auto Precharge .......................... 40
Alternating Bank Read Accesses .................... 41
Read - Full-Page Burst .................................... 42
Read - DQM Operation ................................. 43
Writes
Write - Single Write ....................................... 44
Write - Without Auto Precharge ................... 45
Write - With Auto Precharge ......................... 46
Alternating Bank Write Accesses ................... 47
Write - Full-Page Burst ................................... 48
Write - DQM Operation ................................ 49
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
4
16Mb: x16
IT SDRAM
11
11
11
RAS#
REFRESH
CONTROLLER
2,048
REFRESH
COUNTER
CAS#
256
256 (x16)
8
COLUMN-
ADDRESS BUFFER
BURST COUNTER
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
256 (x16)
BANK1
MEMORY
ARRAY
(2,048 x 256 x 16)
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
CONTROL
LOGIC
COLUMN
DECODER
COLUMN-
ADDRESS LATCH
8
MODE REGISTER
ROW-
ADDRESS
LATCH
11
ROW
DECODER
11
COMMAND
DECODE
DQ0-
DQ15
A0-A10, BA
16
8
DQML,
DQMH
256
2,048
BANK0
MEMORY
ARRAY
(2,048 x 256 x 16)
ROW
DECODER
ROW-
ADDRESS
LATCH
11
12
ADDRESS
REGISTER
12
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
16
16
FUNCTIONAL BLOCK DIAGRAM
1 Meg x 16 SDRAM
16Mb: x16 IT SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16IT.p65 Rev. 5/99
1999, Micron Technology, Inc.
5
16Mb: x16
IT SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
35
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
34
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN
(row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access
in progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
18
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
15, 16, 17
WE#, CAS#,
Input
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
RAS#
command being entered.
14, 36
DQML,
Input
Input/Output Mask: DQM is an input mask signal for write accesses and an
DQMH
output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH
corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
19
BA
Input
Bank Address Inputs: BA defines to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. BA is also used to
program the twelfth bit of the Mode Register.
21-24, 27-32, 20
A0-A10
Input
Address Inputs: A0-A10 are sampled during the ACTIVE command
(row-address A0-A10) and READ/WRITE command (column-address A0-
A7, with A10 defining AUTO PRECHARGE) to select one location out of
the 512K available in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
2, 3, 5, 6, 8, 9,
DQ0-
Input/ Data I/Os: Data bus.
11, 12, 39, 40, 42,
DQ15
Output
43, 45, 46, 48, 49
33, 37
NC
No Connect: These pins should be left unconnected.
7, 13, 38, 44
V
DD
Q
Supply DQ Power: Provide isolated power to DQs for improved noise immu-
nity.
4, 10, 41, 47
V
SS
Q
Supply DQ Ground: Provide isolated ground to DQs for improved noise
immunity.
1, 25
V
DD
Supply Power Supply: +3.3V 0.3V.
26, 50
V
SS
Supply Ground.
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