Document Outline
- Features
- Options
- Key Timing Parameters
- Pin Assignment
- 4 Meg x 4 FPM DRAM Part Numbers
- General Description
- Fast Page Mode Access
- DRAM Refresh
- Standby
- Functional Block Diagrams
- Absolute Maximum Ratings
- DC Electrical Characteristics and Operating Conditions
- IDD Operating Conditions and Maximum Limits
- Capacitance
- AC Electrical Characteristics
- AC Electrical Characteristics
- Notes
- READ Cycle
- EARLY WRITE Cycle
- READ-WRITE Cycle
- FAST-PAGE-MODE READ Cycle
- FAST-PAGE-MODE EARLY WRITE Cycle
- FAST-PAGE-MODE READ-WRITE Cycle
- FAST-PAGE-MODE READ EARLY WRITE Cycle
- RAS#-ONLY REFRESH Cycle
- CBR REFRESH Cycle
- HIDDEN REFRESH Cycle
- SELF REFRESH Cycle
- 24/26-Pin Plastic SOJ (300 mil)
- 24/26-Pin Plastic TSOP (300 mil)
1
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
4 MEG x 4 FPM DRAM PART NUMBERS
REFRESH
PART NUMBER
V
CC
ADDRESSING PACKAGE REFRESH
MT4LC4M4B1DJ-6
3.3V
2K
SOJ
Standard
MT4LC4M4B1DJ-6 S 3.3V
2K
SOJ
Self
MT4LC4M4B1TG-6
3.3V
2K
TSOP
Standard
MT4LC4M4B1TG-6 S 3.3V
2K
TSOP
Self
MT4LC4M4A1DJ-6
3.3V
4K
SOJ
Standard
MT4LC4M4A1DJ-6 S 3.3V
4K
SOJ
Self
MT4LC4M4A1TG-6
3.3V
4K
TSOP
Standard
MT4C4M4A1TG-6 S 3.3V
4K
TSOP
Self
MT4C4M4B1DJ-6
5V
2K
SOJ
Standard
MT4C4M4B1DJ-6 S
5V
2K
SOJ
Self
MT4C4M4B1TG-6
5V
2K
TSOP
Standard
MT4C4M4B1TG-6 S
5V
2K
TSOP
Self
MT4C4M4A1DJ-6
5V
4K
SOJ
Standard
MT4C4M4A1DJ-6 S
5V
4K
SOJ
Self
MT4C4M4A1TG-6
5V
4K
TSOP
Standard
MT4C4M4A1TG-6 S
5V
4K
TSOP
Self
MT4LC4M4B1, MT4C4M4B1
MT4LC4M4A1, MT4C4M4A1
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/mti/msp/html/datasheet.html
DRAM
FEATURES
Industry-standard x4 pinout, timing, functions,
and packages
High-performance, low-power CMOS silicon-gate
process
Single power supply (+3.3V 0.3V or +5V 0.5V)
All inputs, outputs and clocks are TTL-compatible
Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
Optional self refresh (S) for low-power data
retention
11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
FAST-PAGE-MODE (FPM) access
5V tolerant inputs and I/Os on 3.3V devices
OPTIONS
MARKING
Voltage
3.3V
LC
5V
C
Refresh Addressing
2,048 (2K) rows
B1
4,096 (4K) rows
A1
Packages
Plastic SOJ (300 mil)
DJ
Plastic TSOP (300 mil)
TG
Timing
50ns access
-5
60ns access
-6
Refresh Rates
Standard Refresh
None
Self Refresh (128ms period)
S *
NOTE: 1. The 4 Meg x 4 FPM DRAM base number differenti-
ates the offerings in one place--MT4LC4M4B1. The
fifth field distinguishes various options: B1
designates a 2K refresh and A1 designates a 4K
refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC4M4B1DJ
**NC on 2K refresh and A11 on 4K refresh options.
PIN ASSIGNMENT (Top View)
V
CC
DQ0
DQ1
WE#
RAS#
**NC/
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ3
DQ2
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
WE#
RAS#
**NC/
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ3
DQ2
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
24/26-Pin SOJ
24/26-Pin TSOP
KEY TIMING PARAMETERS
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
-5
84ns
50ns
20ns
25ns
13ns
30ns
-6
110ns
60ns
35ns
30ns
15ns
40ns
2
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
Additional columns may be accessed by providing valid
column addresses, strobing CAS# and holding RAS#
LOW, thus executing faster memory cycles. Returning
RAS# HIGH terminates the page mode of operation,
i.e., closes the page.
DRAM REFRESH
Preserve correct memory cell data by maintaining
power and executing any RAS# cycle (READ, WRITE)
or RAS# REFRESH cycle (RAS#-ONLY, CBR, or HID-
DEN) so that all combinations of RAS# addresses (2,048
for 2K and 4,096 for 4K) are executed within
t
REF
(MAX), regardless of sequence. The CBR and SELF
REFRESH cycles will invoke the internal refresh counter
for automatic RAS# addressing.
An optional self refresh mode is also available the
"S" version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified
t
RASS. The "S" option allows the
user the choice of a fully static, low-power data reten-
tion mode or a dynamic refresh mode at the extended
refresh period of 128ms, or 31.25s per row for a 4K
refresh and 62.5s per row for a 2K refresh, when using
a distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller utilizes RAS#-ONLY or burst CBR refresh se-
quence, all rows must be refreshed with a refresh rate of
t
RC minimum prior to resuming normal operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-
state memory containing 16,777,216 bits organized in
a x4 configuration. RAS# is used to latch the row
address (first 11 bits for 2K and first 12 bits for 4K). Once
the page has been opened by RAS#, CAS# is used to latch
the column address (the latter 11 bits for 2K and the
latter 10 bits for 4K; address pins A10 and A11 are "Don't
Care").
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. If WE# goes
LOW prior to CAS# going LOW, the output pins
remain open (High- Z) until the next CAS# cycle,
regardless of OE#.
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE
occurs when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to
applying input data. If a LATE WRITE or READ-
MODIFY-WRITE is attempted while keeping OE# LOW,
no WRITE will occur, and the data outputs will drive
read data from the accessed location.
The four data inputs and the four data outputs are
routed through four pins using common I/O, and pin
direction is controlled by WE# and OE#.
The MT4LC4M4B1 and MT4LC4M4A1 must be
refreshed periodically in order to retain stored data.
FAST PAGE MODE ACCESS
Page operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-
address-defined page boundary. The page cycle is al-
ways initiated with a row address strobed in by RAS#,
followed by a column address strobed in by CAS#.
3
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
FUNCTIONAL BLOCK DIAGRAM 2K REFRESH
4,096
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS#
12
12
10
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
V
DD
Vss
12
WE#
CAS#
10
COLUMN-
ADDRESS
BUFFER(10)
ROW-
ADDRESS
BUFFERS (12)
ROW
DECODER
4,096
1,024
COLUMN
DECODER
OE#
DQ0
DQ1
DQ2
DQ3
4
4
4
4
REFRESH
COUNTER
1,024
4,096 x 1,024 x 4
MEMORY
ARRAY
SENSE AMPLIFIERS
I/O GATING
DATA-OUT
BUFFER
DATA-IN
BUFFER
COMPLEMENT
SELECT
4,096
ROW SELECT
(1 of 4096)
2,048
2,048
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS#
11
11
11
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
11
WE#
CAS#
10
COLUMN-
ADDRESS
BUFFER(11)
ROW-
ADDRESS
BUFFERS (11)
2,048
ROW
DECODER
2,048
1,024
COLUMN
DECODER
OE#
DQ0
DQ1
DQ2
DQ3
4
4
4
4
REFRESH
COUNTER
1
ROW TRANSFER
(2 OF 2)
ROW TRANSFER
(1 OF 2)
1,024
4,096 x 1,024 x 4
MEMORY
ARRAY
SENSE AMPLIFIERS
I/O GATING
DATA-OUT
BUFFER
DATA-IN
BUFFER
COMPLEMENT
SELECT
2,048
ROW SELECT
(2 of 4,096)
FUNCTIONAL BLOCK DIAGRAM 4K REFRESH
4
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Pin Relative to V
SS
3.3V............................................. ......... -1V to +4.6V
5V................................................ ............ -1V
TO
+7V
Voltage on NC, Inputs or I/O Pins Relative to V
SS
3.3V............................................. ......... -1V to +5.5V
5V................................................ ............ -1V
TO
+7V
Operating Temperature, T
A
(ambient) .... 0C to +70C
Storage Temperature (plastic) ............ -55C to +150C
Power Dissipation ................................................... 1W
*Stresses greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the
device. This is a stress rating only, and functional opera-
tion of the device at these or any other conditions above
those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 5, 6) (V
CC
(MIN)
V
CC
V
CC
(MAX))
3.3V
5V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
MIN
MAX UNITS NOTES
SUPPLY VOLTAGE
V
CC
3
3.6
4.5
5.5
V
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC
V
IH
2
5.5
2.4
Vcc+1
V
24
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC
V
IL
-1.0
0.8
-0.5
0.8
V
24
INPUT LEAKAGE CURRENT:
Any input at V
IN
[0V
V
IN
V
CC
(MAX)];
I
I
-2
2
-2
2
A
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
I
OUT
= -2mA
V
OH
2.4
2.4
V
OUTPUT LOW VOLTAGE:
I
OUT
= 2mA
V
OL
0.4
0.4
V
OUTPUT LEAKAGE CURRENT:
Any output at V
OUT
[0V
V
OUT
V
CC
(MAX)];
I
OZ
-5
5
-5
5
A
DQ is disabled and in High-Z state
5
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
I
CC
OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) [Vcc (MIN)
Vcc Vcc (MAX)]
3.3V
5V
2K
4K
2K
4K
PARAMETER/CONDITION
SYM SPEED REFRESH REFRESH REFRESH REFRESH UNITS NOTES
STANDBY CURRENT: TTL
I
CC
1
ALL
1
1
1
1
mA
(RAS# = CAS# = V
IH
)
STANDBY CURRENT: CMOS (non-"S" version only)
I
CC
2
ALL
500
500
500
500
mA
(RAS# = CAS# = other inputs = V
CC
- 0.2V)
STANDBY CURRENT: CMOS ("S" version only)
I
CC
2
ALL
150
150
150
150
A
(RAS# = CAS# = other inputs = V
CC
- 0.2V)
OPERATING CURRENT: Random READ/WRITE
-5
110
90
140
120
Average power supply current
I
CC
3
-6
100
80
130
110
mA
23
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: FAST PAGE MODE
-5
110
100
110
100
Average power supply current
I
CC
4
-6
100
90
100
90
mA
23
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT: RAS#-ONLY
-5
110
90
140
120
Average power supply current
I
CC
5
-6
100
80
130
110
mA
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
REFRESH CURRENT: CBR
-5
110
90
140
120
Average power supply current
I
CC
6
-6
100
80
130
110
mA
4, 7
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
REFRESH CURRENT: Extended ("S" version only)
ALL
300
300
300
300
A
4, 7
Average power supply current: CAS# = 0.2V or
I
CC
7
CBR cycling; RAS# =
t
RAS (MIN); WE# = V
CC
- 0.2V;
A0-A11, OE# and D
IN
= V
CC
- 0.2V or 0.2V
t
RC
62.5
31.25
62.5
31.25
s
23
(D
IN
may be left open)
REFRESH CURRENT: Self ("S" version only)
Average power supply current: CBR with
I
CC
8
ALL
300
300
300
300
A
4, 7
RAS#
t
RASS (MIN) and CAS# held LOW;
WE# = V
CC
- 0.2V; A0-A11, OE# and
D
IN
= V
CC
- 0.2V or 0.2V (D
IN
may be left open)
CAPACITANCE
(Note: 6)
PARAMETER
SYMBOL
MAX
UNITS
Input Capacitance: Address pins
C
I
1
5
p F
Input Capacitance: RAS#, CAS#, WE#, OE#
C
I
2
7
p F
Input/Output Capacitance: DQ
C
IO
7
p F
6
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN)
Vcc Vcc (MAX)]
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from column address
t
AA
25
30
ns
Column-address hold time (referenced to RAS#)
t
AR
38
45
ns
Column-address setup time
t
ASC
0
0
ns
Row-address setup time
t
ASR
0
0
ns
Column address to WE# delay time
t
AWD
42
49
ns
18
Access time from CAS#
t
CAC
13
15
ns
Column-address hold time
t
CAH
8
10
ns
CAS# pulse width
t
CAS
8
10,000
10
10,000
ns
CAS# LOW to "Don't Care" during Self Refresh
t
CHD
15
15
ns
CAS# hold time (CBR Refresh)
t
CHR
8
10
ns
4
CAS# to output in Low-Z
t
CLZ
0
0
ns
22
CAS# precharge time
t
CP
8
10
ns
13
Access time from CAS# precharge
t
CPA
28
35
ns
CAS# to RAS# precharge time
t
CRP
5
5
ns
CAS# hold time
t
CSH
38
45
ns
CAS# setup time (CBR Refresh)
t
CSR
5
5
ns
4
CAS# to WE# delay time
t
CWD
28
35
ns
18
WRITE command to CAS# lead time
t
CWL
8
10
ns
Data-in hold time
t
DH
8
10
ns
19
Data-in setup time
t
DS
0
0
ns
19
Output disable
t
OD
0
12
0
15
ns
22
Output enable
t
OE
12
15
ns
20
OE# hold time from WE# during
t
OEH
8
10
ns
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
t
OFF
0
12
0
15
ns
17, 22
OE# setup prior to RAS# during HIDDEN REFRESH cycle
t
ORD
0
0
ns
FAST-PAGE-MODE READ or WRITE cycle time
t
PC
20
25
ns
FAST-PAGE-MODE READ-WRITE cycle time
t
PRWC
47
56
ns
Access time from RAS#
t
RAC
50
60
ns
RAS# to column-address delay time
t
RAD
9
12
ns
15
Row-address hold time
t
RAH
9
10
ns
RAS# pulse width
t
RAS
50
10,000
60
10,000
ns
RAS# pulse width (FAST PAGE MODE)
t
RASP
50
125,000
60
125,000
ns
RAS# pulse width during Self Refresh
t
RASS
100
100
s
Random READ or WRITE cycle time
t
RC
84
104
ns
RAS# to CAS# delay time
t
RCD
11
14
ns
14
READ command hold time (referenced to CAS#)
t
RCH
0
0
ns
16
READ command setup time
t
RCS
0
0
ns
Refresh period (2,048 cycles)
t
REF
32
32
ms
Refresh period (4,096 cycles)
t
REF
64
64
ms
7
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN)
Vcc Vcc (MAX)]
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Refresh period "S" version
t
REF
128
128
ms
140
RAS# precharge time
t
RP
30
40
ns
RAS# to CAS# precharge time
t
RPC
5
5
ns
RAS# precharge time exiting Self Refresh
t
RPS
90
105
ns
READ command hold time (referenced to RAS#)
t
RRH
0
0
ns
16
RAS# hold time
t
RSH
13
15
ns
READ-WRITE cycle time
t
RWC
116
140
ns
RAS# to WE# delay time
t
RWD
67
79
ns
19
WRITE command to RAS# lead time
t
RWL
13
15
ns
Transition time (rise or fall)
t
T
2
50
2
50
ns
WRITE command hold time
t
WCH
8
10
ns
WRITE command hold time (referenced to RAS#)
t
WCR
38
45
ns
WE# command setup time
t
WCS
0
0
ns
18
WRITE command pulse width
t
WP
5
5
ns
WE# hold time (CBR Refresh)
t
WRH
8
10
ns
4, 23
WE# setup time (CBR Refresh)
t
WRP
8
10
ns
4, 23
8
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
CC
= +3.3V or 5.0V;
f = 1 MHz.
3.
I
CC
is dependent on output loading and cycle
rates. Specified values are obtained with
minimum cycle time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range is ensured.
6.
An initial pause of 100s is required after power-
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
t
REF
refresh requirement is exceeded.
7.
AC characteristics assume
t
T = 5ns.
8.
V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition
times are measured between V
IH
and V
IL
(or
between V
IL
and V
IH
).
9.
In addition to meeting the transition rate
specification, all input signals must transit
between V
IH
and V
IL
(or between V
IL
and V
IH
) in
a monotonic manner.
10. If CAS# = V
IH
, data output is High-Z.
11. If CAS# = V
IL
, data output may contain data
from the last valid READ cycle.
12. Measured with a load equivalent to two TTL
gates, 100pF and V
OL
= 0.8V and V
OH
= 2V.
13. If CAS# is LOW at the falling edge of RAS#, Q
will be maintained from the previous cycle. To
initiate a new cycle and clear the data-out
buffer, CAS# must be pulsed HIGH for
t
CP.
14. The
t
RCD (MAX) limit is no longer specified.
t
RCD (MAX) was specified as a reference point
only. If
t
RCD was greater than the specified
t
RCD (MAX) limit, then access time was con-
trolled exclusively by
t
CAC (
t
RAC [MIN] no
longer applied). With or without the
t
RCD limit,
t
AA and
t
CAC must always be met.
15. The
t
RAD (MAX) limit is no longer specified.
t
RAD (MAX) was specified as a reference point
only. If
t
RAD was greater than the specified
t
RAD (MAX) limit, then access time was con-
trolled exclusively by
t
AA (
t
RAC and
t
CAC no
longer applied). With or without the
t
RAD
(MAX) limit,
t
AA,
t
RAC, and
t
CAC must always
be met.
16. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
17.
t
OFF (MAX) defines the time at which the
output achieves the open circuit condition and
is not referenced to V
OH
or V
OL
.
18.
t
WCS,
t
RWD,
t
AWD, and
t
CWD are not
restrictive operating parameters.
t
WCS applies to
EARLY WRITE cycles.
t
RWD,
t
AWD, and
t
CWD
apply to READ-MODIFY-WRITE cycles. If
t
WCS
t
WCS (MIN), the cycle is an EARLY WRITE
cycle and the data output will remain an open
circuit throughout the entire cycle. If
t
RWD
t
RWD (MIN),
t
AWD
t
AWD (MIN), and
t
CWD
t
CWD (MIN), the cycle is a READ-MODIFY-
WRITE and the data output will contain data
read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW result in a LATE
WRITE (OE#-controlled) cycle.
t
WCS,
t
RWD,
t
CWD, and
t
AWD are not applicable in a LATE
WRITE cycle.
19. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
20. If OE# is tied permanently LOW, LATE WRITE,
or READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
21. A HIDDEN REFRESH may also be performed
after a WRITE cycle. In this case, WE# = LOW
and OE# = HIGH.
22. The 3ns minimum is a parameter guaranteed by
design.
23. Column address changed once each cycle.
24. V
IH
overshoot: V
IH
(MAX) = V
CC
+ 2V for a pulse
width
10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
10ns, and the pu lse width cannot be greater
than one third of the cycle rate.
9
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
READ CYCLE
tRRH
tCLZ
tCAC
tRAC
tAA
VALID DATA
OPEN
tOFF
tRCH
ROW
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD
tCAS
tRSH
tCSH
tRP
tRC
tRAS
tCRP
tASR
ROW
OPEN
RAS#
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
COLUMN
WE#
DON'T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OFF
0
12
0
15
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC
84
104
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
OD
0
12
0
15
ns
t
OE
12
15
ns
10
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
EARLY WRITE CYCLE
DON'T CARE
UNDEFINED
V
V
IH
IL
CAS#
VALID DATA
ROW
COLUMN
ROW
tDS
tDH
tWP
tWCH
tWCS
tWCR
tRWL
tCWL
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCAS
tRSH
tCSH
tRCD
tCRP
tRAS
tRC
tRP
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
RAS#
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
RAH
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC
84
104
ns
t
RCD
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCR
38
45
ns
t
WCS
0
0
ns
t
WP
5
5
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
CWL
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
t
RAD
9
12
ns
11
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
VALID D
OUT
VALID D
IN
ROW
COLUMN
ROW
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OPEN
OPEN
tOE
tOD
tCAC
tRAC
tAA
tCLZ
tDS
tDH
tAWD
tWP
tRWL
tCWL
tCWD
tRWD
tRCS
tASC
tCAH
tAR
tASR
tRAD
tCRP
tRCD
tCAS
tRSH
tCSH
tRAS
tRWC
tRP
tRAH
OE#
tOEH
WE#
DON'T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OD
0
12
0
15
ns
t
OE
12
15
ns
t
OEH
8
10
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RCD
11
14
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWC
116
140
ns
t
RWD
67
79
ns
t
RWL
13
15
ns
t
WP
5
5
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
AWD
42
49
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
CWD
28
35
ns
t
CWL
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
12
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
VALID
DATA
VALID
DATA
VALID
DATA
COLUMN
COLUMN
COLUMN
ROW
ROW
tRCS
tCAH
tASC
tCP
tCAS
tRSH
tCP
tCAS
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
tRP
tCAH
tASC
tCAH
tASC
tAR
tRAH
tRAD
tASR
tRCS
tRCH
tRCH
tRCS
tRRH
tRCH
tOFF
tCAC
tCPA
tAA
tCLZ
tOFF
tCAC
tCPA
tAA
tCLZ
tOFF
tCAC
tRAC
tAA
tCLZ
tOE
tOD
tOE
tOD
tOE
tOD
OPEN
OPEN
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OE#
DON'T CARE
UNDEFINED
FAST-PAGE-MODE READ CYCLE
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OE
12
15
ns
t
OFF
0
12
0
15
ns
t
PC
20
25
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
CP
8
10
ns
t
CPA
28
35
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
OD
0
12
0
15
ns
13
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
FAST-PAGE-MODE EARLY WRITE CYCLE
tDS
tDH
tDS
tDH
tDS
tDH
tWCR
VALID DATA
VALID DATA
VALID DATA
tRWL
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tCAH
tASC
tCAH
tASC
tCAH
tASC
tRAH
tASR
tRAD
tAR
COLUMN
COLUMN
COLUMN
ROW
ROW
tCP
tCAS
tRSH
tCP
tCAS
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
tRP
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
RAS#
OE#
V
V
IH
IL
DON'T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCR
38
45
ns
t
WCS
0
0
ns
t
WP
5
5
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
CWL
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
t
PC
20
25
ns
14
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
DON'T CARE
UNDEFINED
tOE
tOE
tOE
OPEN
D OUT
VALID
DIN
VALID
D OUT
VALID
D IN
VALID
D OUT
VALID
D IN
VALID
OPEN
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCLZ
tCAC
tRAC
tWP
tCWL
tRWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tRCS
tRWD
tASR
tRAH
tASC
tRAD
tAR
tCAH
tASC
tCAH
tASC
tCAH
tCP
tCAS
tRSH
tCP
tRP
tRASP
tCAS
tCP
tCAS
tRCD
tCSH
tPC
NOTE 1
tCRP
ROW
COLUMN
COLUMN
COLUMN
ROW
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OE#
WE#
tPRWC
tOEH
tOD
tOD
tOD
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
NOTE: 1.
t
PC is for LATE WRITE only.
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OD
0
12
0
15
ns
t
OE
12
15
ns
t
OEH
8
10
ns
t
PC
20
25
ns
t
PRWC
47
56
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWD
67
79
ns
t
RWL
13
15
ns
t
WP
5
5
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
AWD
42
49
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
CP
8
10
ns
t
CPA
28
35
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
CWD
28
35
ns
t
CWL
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
15
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
FAST-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
ROW
VALID
DATA
VALID DATA
OPEN
tCRP
tRCD
tCAS
tRSH
tRASP
tRP
tPC
tASC
tCAH
tAR
tASR
tRAD
tRAH
tWCS
tWP
tRWL
tRCS
tDH
tDS
tCAC
tOFF
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
RAS#
DQ
V
V
OH
OL
WE#
V
V
IH
IL
tCSH
COLUMN
tCP
tCP
tASC
tCAH
tCWL
tWCH
tCLZ
tAA
RAC
DON'T CARE
UNDEFINED
t
NOTE 1
ROW
COLUMN
tCAS
NOTE: 1. Do not drive data prior to tristate.
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OFF
0
12
0
15
ns
t
PC
20
25
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCS
0
0
ns
t
WP
5
5
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
CWL
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
16
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
RAS#-ONLY REFRESH CYCLE
(OE# and WE# = DON'T CARE)
ROW
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
RAS#
tRC
tRAS
tRP
tCRP
tASR
tRAH
ROW
OPEN
DQ
V
V
OH
OL
tRPC
CBR REFRESH CYCLE
(Addresses and OE# = DON'T CARE)
tRP
V
V
IH
IL
RAS#
tRAS
OPEN
tCHR
tCSR
V
V
IH
IL
V
V
OH
OL
CAS#
DQ
tRP
tRAS
tRPC
tCSR
tRPC
tCHR
tCP
V
V
IH
IL
tWRP
tWRH
tWRP
tWRH
WE#
DON'T CARE
UNDEFINED
NOTE 1
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ASR
0
0
ns
t
CHR
8
10
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSR
5
5
ns
t
RAH
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC
84
104
ns
t
RP
30
40
ns
t
RPC
5
5
ns
t
WRH
8
10
ns
t
WRP
8
10
ns
NOTE: 1. End of CBR REFRESH cycle.
17
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
DON'T CARE
UNDEFINED
tCLZ
tOFF
OPEN
VALID DATA
OPEN
COLUMN
ROW
tCAC
tRAC
tAA
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCRP
tRCD
tRSH
tRAS
tRP
tCHR
tRAS
DQx
V
V
IOH
IOL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
RAS#
tOE
tOD
CASL#/CASH#
V
V
IH
IL
OE#
t
ORD
HIDDEN REFRESH CYCLE
1
(WE# = HIGH; OE# = LOW)
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OE
12
15
ns
t
OFF
0
12
0
15
ns
t
ORD
0
0
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RCD
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CHR
8
10
ns
t
CLZ
0
0
ns
t
CRP
5
5
ns
t
OD
0
12
0
15
ns
NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.
18
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
SELF REFRESH CYCLE
(Addresses and OE# = DON'T CARE)
tRP
V
V
IH
IL
RAS#
tRAS
OPEN
tCHR
tCSR
V
V
IH
IL
CAS#
Q
tRP
tRAS
tRPC
tCSR
tRPC
tCHR
tCP
V
V
IH
IL
tWRP
tWRH
tWRP
tWRH
WE#
DON'T CARE
UNDEFINED
NOTE: 1. Once
t
RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.
2. Once
t
RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
CHD
15
15
ns
t
CP
8
10
ns
t
CSR
5
5
ns
t
RASS
100
100
s
t
RP
30
40
ns
t
RPC
5
5
ns
t
RPS
90
105
ns
t
WRH
8
10
ns
t
WRP
8
10
ns
19
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
24/26-PIN PLASTIC SOJ (300 mil)
R
.299 (7.59)
.305 (7.75)
.679 (17.25)
.673 (17.09)
.340 (8.64)
.330 (8.38)
.050 (1.27) TYP
.600 (15.24) TYP
PIN #1 INDEX
.020 (0.51)
.015 (0.38)
.132 (3.35)
.142 (3.61)
.105 (2.67)
.090 (2.29)
.260 (6.61)
.275 (6.99)
.030 (0.76)
.040 (1.02)
SEATING PLANE
.112 (2.84)
.102 (2.59)
.037 (0.94) MAX
DAMBAR PROTRUSION
.026 (0.66)
.032 (0.81)
NOTE:
1. All dimensions in inches (millimeters)
MAX
or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per
side.
20
4 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
24/26-PIN PLASTIC TSOP (300 mil)
.047 (1.20)
MAX
.367 (9.32)
.359 (9.12)
.302 (7.67)
.298 (7.57)
.050 (1.27)
TYP
1
26
13
.678 (17.23)
.672 (17.07)
.020 (0.50)
.012 (0.30)
PIN #1 INDEX
SEE DETAIL A
.007 (0.18)
.005 (0.13)
.004 (0.10)
.024 (0.60)
.016 (0.40)
.008 (0.20)
.002 (0.05)
DETAIL A
.010 (0.25)
.0315 (0.80)
TYP
GAGE PLANE
SEATING PLANE
NOTE:
1. All dimensions in inches (millimeters)
MAX
or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per
side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
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