Document Outline
- Features
- Options
- Key Timing Parameters
- General Description
- Pin Assignment (Front View)
- Part Numbers
- Fast Page Mode
- JEDEC-Defined Presence-Detect - MT2D(T)132(X) (4MB)
- EDO Page Mode
- Refresh
- x 16 Configuration
- JEDEC-Defined Presence-Detect - MT4D(T)232(X) (8MB)
- Functional Block Diagrams
- MT2D(T)132(X) (4MB)
- MT4D(T)232(X) (4MB)
- Absolute Maximum Ratings
- DC Electrical Characteristics and Operating Conditions
- ICC Specifications and Conditions
- Capacitance
- Fast Page Mode AC Electrical Characteristics
- Fast Page Mode AC Electrical Characteristics
- EDO Page Mode AC Electrical Characteristics
- Notes
- Read Cycle
- Early Write Cycle
- Fast-Page-Mode Read Cycle
- EDO-Page-Mode Read Cycle
- Fast/EDO-Page-Mode Early-Write Cycle
- EDO-Page-Mode Read-Early-Write Cycle
- Fast-Page-Mode Read-Early-Write Cycle
- EDO Read Cycle
- RAS#-Only Refresh Cycle
- CBR Refresh Cycle
- Hidden Refresh Cycle
- 72-Pin SIMM (4MB)
- 72-in SIMM (8MB)
- 72-Pin SIMM (4MB)
- 72-in SIMM (8MB)
1, 2 Meg x 32 SIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM57_2.p65 Rev. 9/98
1998, Micron Technology, Inc.
1
1, 2 MEG x 32
DRAM SIMMs
NOT RECOMMENDED FOR NEW DESIGNS
DRAM
MODULE
FEATURES
JEDEC- and industry-standard pinout in a 72-pin,
single in-line memory module (SIMM)
4MB (1 Meg x 32) and 8MB (2 Meg x 32)
High-performance CMOS silicon-gate process
Single +5V 10% power supply
All inputs, outputs and clocks are TTL-compatible
Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
Multiple RAS# lines allow x16 or x32 width
1,024-cycle refresh distributed across 16ms
FAST PAGE MODE (FPM) access or
Extended Data-Out (EDO) PAGE MODE access
OPTIONS
MARKING
Timing
50ns access
-5**
60ns access
-6
Components
SOJ
D
TSOP
D T
Packages
72-pin SIMM
M
72-pin SIMM (Gold)
G
Operating Modes
FAST PAGE MODE
None
EDO PAGE MODE
X
**EDO version only
PIN ASSIGNMENT (Front View)
72-Pin SIMM
1 Meg x 32 TSOP version (shown)
1 Meg x 32 SOJ version
2 Meg x 32 TSOP version
2 Meg x 32 SOJ version
1
36
37
72
PIN SYMBOL
PIN SYMBOL
PIN SYMBOL
PIN SYMBOL
1
V
SS
19
NC (
A10
)
37
NC
55
DQ12
2
DQ1
20
DQ5
38
NC
56
DQ28
3
DQ17
21
DQ21
39
V
SS
57
DQ13
4
DQ2
22
DQ6
40
CAS0#
58
DQ29
5
DQ18
23
DQ22
41
CAS2#
59
V
DD
6
DQ3
24
DQ7
42
CAS3#
60
DQ30
7
DQ19
25
DQ23
43
CAS1#
61
DQ14
8
DQ4
26
DQ8
44
RAS0#
62
DQ31
9
DQ20
27
DQ24
45
NC*/RAS1#
63
DQ15
10
V
DD
28
A7
46
NC
64
DQ32
11
NC
29
NC (
A11
)
47
WE#
65
DQ16
12
A0
30
V
DD
48
NC
66
NC
13
A1
31
A8
49
DQ9
67
PRD1
14
A2
32
A9
50
DQ25
68
PRD2
15
A3
33
NC*/RAS3#
51
DQ10
69
PRD3
16
A4
34
RAS2#
52
DQ26
70
PRD4
17
A5
35
NC
53
DQ11
71
NC
18
A6
36
NC
54
DQ27
72
V
SS
*4MB version only
MT2D(T)132(X)
MT4D(T)232D(X)
For the latest data sheet revisions, please refer to the
Micron Web site:
www.micron.com/datasheets
NOTE: Symbols in parentheses are not used on these
modules but may be used for other modules in
this product family. They are for reference only.
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
-5
84ns
50ns
20ns
25ns
15ns
8ns
-6
104ns
60ns
25ns
30ns
17ns
10ns
FPM Operating Mode
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
-6
110ns
60ns
35ns
30ns
15ns
40ns
GENERAL DESCRIPTION
The MT2D(T)132(X) and MT4D(T)232D(X) are ran-
domly accessed, 4MB and 8MB solid-state memories
organized in a x32 configuration. During READ or
WRITE cycles, each bit is uniquely addressed through
20 address bits that are entered 10 bits (A0-A9) at a
time. RAS# is used to latch the first 10 bits and CAS# the
latter 10 bits. A READ or WRITE cycle is selected with
the WE# input. A logic HIGH on WE# dictates read
mode, while a logic LOW on WE# dictates write mode.
During a WRITE cycle, data-in (D) is latched by the
falling edge of WE# or CAS#, whichever occurs last.
EARLY WRITE occurs when WE# goes LOW prior to CAS#
going LOW, and the output pin(s) remain open (High-
Z) until the next CAS# cycle.
1, 2 Meg x 32 SIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM57_2.p65 Rev. 9/98
1998, Micron Technology, Inc.
2
1, 2 MEG x 32
DRAM SIMMs
NOT RECOMMENDED FOR NEW DESIGNS
PART NUMBERS
EDO Operating Mode
PART NUMBER
CONFIGURATION PLATING
PACKAGING
MT2DT132G-x X
1 Meg x 32
Gold
TSOP
MT2D132G-x X
1 Meg x 32
Gold
SOJ
MT2DT132M-x X
1 Meg x 32
Tin/Lead
TSOP
MT2D132M-x X
1 Meg x 32
Tin/Lead
SOJ
MT4DT232DG-x X
2 Meg x 32
Gold
TSOP
MT4D232DG-x X
2 Meg x 32
Gold
SOJ
MT4DT232DM-x X
2 Meg x 32
Tin/Lead
TSOP
MT4D232DM-x X
2 Meg x 32
Tin/Lead
SOJ
x = speed
FPM Operating Mode
PART NUMBER
CONFIGURATION PLATING
PACKAGING
MT2DT132G-x
1 Meg x 32
Gold
TSOP
MT2D132G-x
1 Meg x 32
Gold
SOJ
MT2DT132M-x
1 Meg x 32
Tin/Lead
TSOP
MT2D132M-x
1 Meg x 32
Tin/Lead
SOJ
MT4DT232DG-x
2 Meg x 32
Gold
TSOP
MT4D232DG-x
2 Meg x 32
Gold
SOJ
MT4DT232DM-x
2 Meg x 32
Tin/Lead
TSOP
MT4D232DM-x
2 Meg x 32
Tin/Lead
SOJ
x = speed
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data
operations (READ or WRITE) within a row-address-de-
fined (A0-A9) page boundary. The FAST-PAGE-MODE
cycle is always initiated with a row address strobed in
by RAS# followed by a column address strobed in by
CAS#. Additional columns may be accessed by provid-
ing valid column addresses, strobing CAS# and hold-
ing RAS# LOW, thus executing faster memory cycles.
Returning RAS# HIGH terminates the FAST-PAGE-
MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the "X" version, is
an accelerated FAST-PAGE-MODE cycle. The primary
advantage of EDO is the availability of data-out even
after CAS# goes back HIGH. EDO provides for CAS#
precharge time (
t
CP) to occur without the output data
going invalid. This elimination of CAS# output control
provides for pipelined READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO operates as any DRAM READ or
FAST-PAGE-MODE READ, except data will be held valid
or become valid after CAS# goes HIGH, as long as RAS#
and OE# are held LOW. (Refer to the MT4LC1M16E5
DRAM data sheet for additional information on EDO
functionality.)
REFRESH
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining
power and executing anyRAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)
so that all 1,024 combination of RAS# addresses (A0-
A9) are executed at least every 16ms, regardless of se-
quence.
X16 CONFIGURATION
For x16 applications, the corresponding DQ and
CAS# pins must be connected together (DQ1 to DQ17,
DQ2 to DQ18 and so forth, and CAS0# to CAS2# and
CAS1# to CAS3#). Each RAS# is then a bank select for
the x16 memory organization.
JEDEC-DEFINED
PRESENCE-DETECT
MT2D(T)132(X) (4MB)
SYMBOL
PIN
-5*
-6
PRD1
67
V
SS
V
SS
PRD2
68
V
SS
V
SS
PRD3
69
V
SS
NC
PRD4
70
V
SS
NC
JEDEC-DEFINED
PRESENCE-DETECT
MT4D(T)232D(X) (8MB)
SYMBOL
PIN
-5*
-6
PRD1
67
NC
NC
PRD2
68
NC
NC
PRD3
69
V
SS
NC
PRD4
70
V
SS
NC
*EDO version only
1, 2 Meg x 32 SIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM57_2.p65 Rev. 9/98
1998, Micron Technology, Inc.
3
1, 2 MEG x 32
DRAM SIMMs
NOT RECOMMENDED FOR NEW DESIGNS
FUNCTIONAL BLOCK DIAGRAM
MT2D(T)132(X) (4MB)
U1-U2 = 1 Meg x 16 DRAMs
WE#
CASL#
CASH#
RAS#
OE#
A0-A9
U1
WE#
CASL#
CASH#
RAS#
OE#
DQ17-
DQ32
U2
CAS0#
CAS1#
RAS0#
CAS2#
CAS3#
RAS2#
WE#
A0-A9
10
10
10
16
16
32
DQ1-
DQ16
A0-A9
DQ1-DQ32
V
DD
V
SS
U1-U2
U1-U2
1, 2 Meg x 32 SIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM57_2.p65 Rev. 9/98
1998, Micron Technology, Inc.
4
1, 2 MEG x 32
DRAM SIMMs
NOT RECOMMENDED FOR NEW DESIGNS
FUNCTIONAL BLOCK DIAGRAM
MT4D(T)232D(X) (8MB)
U1-U4 = 1 Meg x 16 DRAMs
A0-A9
U3
DQ17-
DQ32
U4
RAS1#
RAS3#
10
10
16
16
32
DQ1-
DQ16
A0-A9
DQ1-DQ32
WE#
CASL#
CASH#
RAS#
OE#
A0-A9
U1
DQ17-
DQ32
U2
CAS0#
CAS1#
RAS0#
CAS2#
CAS3#
RAS2#
10
10
16
16
32
DQ1-
DQ16
A0-A9
DQ1-DQ32
A0-A9
10
WE#
WE#
CASL#
CASH#
RAS#
OE#
WE#
CASL#
CASH#
RAS#
OE#
WE#
CASL#
CASH#
RAS#
OE#
V
DD
V
SS
U1-U4
U1-U4
1, 2 Meg x 32 SIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM57_2.p65 Rev. 9/98
1998, Micron Technology, Inc.
5
1, 2 MEG x 32
DRAM SIMMs
NOT RECOMMENDED FOR NEW DESIGNS
Icc SPECIFICATIONS AND CONDITIONS
(Notes: 1, 5, 6) (V
DD
= +5V 10%)
PARAMETER/CONDITION
SYMBOL
SIZE
-5*
-6
UNITS NOTES
STANDBY CURRENT: (TTL)
I
CC
1
4MB
4
4
mA
(RAS# = CAS# = V
IH
)
8MB
8
8
STANDBY CURRENT: (CMOS)
I
CC
2
4MB
1
1
mA
(RAS# = CAS# = other inputs = V
DD
- 0.2V)
8MB
2
2
OPERATING CURRENT: Random READ/WRITE
4MB
380
360
mA
2, 22
Average power supply current
I
CC
3
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
8MB
384
364
OPERATING CURRENT: FAST PAGE MODE
4MB
220
mA
2, 22
Average power supply current
I
CC
4
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN]
8MB
224
OPERATING CURRENT: EDO PAGE MODE
I
CC
5
4MB
300
280
mA
2, 22
Average power supply current
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
(X only)
8MB
304
284
REFRESH CURRENT: RAS#-ONLY
4MB
380
360
Average power supply current
I
CC
6
mA
2
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
8MB
384
364
REFRESH CURRENT: CBR
4MB
360
340
Average power supply current
I
CC
7
mA
2, 17
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
8MB
364
344
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply Relative to V
SS
........... -1V to +7V
Operating Temperature, T
A
(ambient) ... 0C to +70C
Storage Temperature (plastic) ............ -55C to +125C
Power Dissipation ........................................................ 2W
Short Circuit Output Current ................................. 50mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 3, 6) (V
DD
= +5V 10%)
PARAMETER/CONDITION
SYMBOL MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
V
DD
4.5
5.5
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
2.4
V
DD
+ 1
V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-1.0
0.8
V
INPUT LEAKAGE CURRENT:
CAS0#-CAS3#
I
I
1
-4
4
A
23
Any input 0V
V
IN
5.5V
A0-A9, WE#
I
I
2
-8
8
A
23
(All other pins not under test = 0V)
RAS0#-RAS3#
I
I
3
-2
2
A
OUTPUT LEAKAGE CURRENT:
DQ1-DQ32
I
OZ
-10
10
A
23
(DQ is disabled; 0V
V
OUT
5.5V)
OUTPUT LEVELS:
V
OH
2.4
V
Output High Voltage (I
OUT
= -5mA)
Output Low Voltage (I
OUT
= 4.2mA)
V
OL
0.4
V
MAX
*EDO version only
PDF 
ZIP