16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

16 MEG x 4 EDO DRAM PART NUMBERS

REFRESH

PART NUMBER

ADDRESSING

PACKAGE

REFRESH

MT4LC16M4H9DJ-x

SOJ

Standard

MT4LC16M4H9DJ-x S

SOJ

Self

MT4LC16M4H9TG-x

TSOP

Standard

MT4LC16M4H9TG-x S

TSOP

Self

MT4LC16M4G3DJ-x

SOJ

Standard

MT4LC16M4G3DJ-x S

SOJ

Self

MT4LC16M4G3TG-x

TSOP

Standard

MT4LC16M4G3TG-x S

TSOP

Self

x = speed

FEATURES

· Single +3.3V ±0.3V power supply
· Industry-standard x4 pinout, timing, functions,

and packages

· 12 row, 12 column addresses (H9) or

13 row, 11 column addresses (G3)

· High-performance CMOS silicon-gate process
· All inputs, outputs and clocks are LVTTL-compat-

ible

· Extended Data-Out (EDO) PAGE MODE access
· Optional self refresh (S) for low-power data

retention

· 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH

distributed across 64ms

OPTIONS

MARKING

· Refresh Addressing

4,096 (4K) rows

8,192 (8K) rows

· Plastic Packages

32-pin SOJ (400 mil)

32-pin TSOP (400 mil)

· Timing

50ns access

-5

60ns access

-6

· Refresh Rates

Standard Refresh

None

Self Refresh (128ms period)

NOTE: 1. The 16 Meg x 4 EDO DRAM base number

differentiates the offerings in one place--
MT4LC16M4H9. The fifth field distinguishes the
address offerings: H9 designates 4K addresses and
G3 designates 8K addresses.

2. The "#" symbol indicates signal is active LOW.

*Contact factory for availability

Part Number Example:

MT4LC16M4H9DJ-6

PIN ASSIGNMENT (Top View)

DRAM

MT4LC16M4G3, MT4LC16M4H9

For the latest data sheet, please refer to the Micron Web
site:

www.micronsemi.com/mti/msp/html/datasheet.html

32-Pin SOJ

32-Pin TSOP

DQ0
DQ1

NC
NC
NC
NC

WE#

RAS#

A0
A1
A2
A3
A4
A5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

Vss

DQ3
DQ2

NC
NC
NC
CAS#
OE#
NC/

A12

A11
A10
A9
A8
A7
A6
Vss

DQ0
DQ1

NC
NC
NC
NC

WE#

RAS#

A0
A1
A2
A3
A4
A5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

Vss

DQ3
DQ2

NC
NC
NC
CAS#
OE#
NC/

A12

A11
A10
A9
A8
A7
A6

Vss

KEY TIMING PARAMETERS

SPEED

RAC

CAC

CAS

-5

84ns

50ns

20ns

25ns

13ns

8ns

-6

104ns

60ns

25ns

30ns

15ns

10ns

**NC on H9 version, A12 on G3 version

GENERAL DESCRIPTION

The 16 Meg x 4 DRAM is a high-speed CMOS,

dynamic random-access memory device containing
67,108,864 bits and designed to operate from 3V to
3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are
functionally organized as 16,777,216 locations con-
taining 4 bits each. The 16,777,216 memory locations
are arranged in 4,096 rows by 4,096 columns on the H9
version and 8,192 rows by 2,048 columns on the G3
version. During READ or WRITE cycles, each location is

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4G3 (13 row addresses)

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10
A11
A12

RAS#

NO. 2 CLOCK

GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR

WE#

CAS#

CONTROL

LOGIC

COLUMN-

ADDRESS

BUFFER(11)

ROW-

ADDRESS

BUFFERS (13)

8,192

2,048

COLUMN

DECODER

OE#

DQ0
DQ1
DQ2
DQ3

REFRESH

COUNTER

ROW SELECT

ROW

DECODER

2,048

SENSE AMPLIFIERS

I/O GATING

DATA-OUT

BUFFER

DATA-IN

BUFFER

8,192 x 2,048 x 4

MEMORY

ARRAY

COMPLEMENT

SELECT

8,192

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4H9 (12 row addresses)

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10
A11

RAS#

NO. 2 CLOCK

GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR

WE#

CAS#

CONTROL

LOGIC

COLUMN-

ADDRESS

BUFFER(12)

ROW-

ADDRESS

BUFFERS (12)

4,096

COLUMN

DECODER

OE#

DQ0
DQ1
DQ2
DQ3

REFRESH

COUNTER

ROW SELECT

ROW

DECODER

4,096

SENSE AMPLIFIERS

I/O GATING

DATA-OUT

BUFFER

DATA-IN

BUFFER

4,096 x 4,096 x 4

MEMORY

ARRAY

COMPLEMENT

SELECT

4,096

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

uniquely addressed via the address bits. First, the row
address is latched by the RAS# signal, then the column
address is latched by CAS#. The device provides EDO-
PAGE-MODE operation, allowing for fast successive
data operations (READ, WRITE, or READ-MODIFY-
WRITE) within a given row.

The 16 Meg x 4 DRAM must be refreshed periodically

in order to retain stored data.

DRAM ACCESS

Each location in the DRAM is uniquely addressable,

as mentioned in the General Description. The data for
each location is accessed via the four I/O pins (DQ0-
DQ3). A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to apply-
ing input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no WRITE
will occur, and the data outputs will drive read data
from the accessed location.

EDO PAGE MODE

DRAM READ cycles have traditionally turned the

output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 16 Meg x 4
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO and it allows CAS# precharge time (

CP) to

occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms).

EDO operates like any DRAM READ or FAST-PAGE-

MODE READ, except data is held valid after CAS# goes
HIGH, as long as RAS# and OE# are held LOW and WE#
is held HIGH. OE# can be brought LOW or HIGH while
CAS# and RAS# are LOW, and the DQs will transition
between valid data and High-Z. Using OE#, there are
two methods to disable the outputs and keep them
disabled during the CAS# HIGH time. The first method
is to have OE# HIGH when CAS# transitions HIGH and
keep OE# HIGH for

OEHC thereafter. This will disable

the DQs, and they will remain disabled (regardless of
the state of OE# after that point) until CAS# falls again.
The second method is to have OE# LOW when CAS#

transitions HIGH and then bring OE# HIGH for a
minimum of

OEP anytime during the CAS# HIGH

period. This will disable the DQs, and they will remain
disabled (regardless of the state of OE# after that point)
until CAS# falls again. (Please refer to Figure 1.) During
other cycles, the outputs are disabled at

OFF time after

RAS# and CAS# are HIGH or at

WHZ after WE# transi-

tions LOW. The

OFF time is referenced from the rising

edge of RAS# or CAS#, whichever occurs last. WE# can
also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.

EDO-PAGE-MODE operations are always initiated

with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the EDO-PAGE-MODE opera-
tion.

DRAM REFRESH

The supply voltage must be maintained at the speci-

fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all 8,192 rows (G3)
or all 4,096 rows (H9) in the DRAM array at least once
every 64ms. The recommended procedure is to execute
4,096 CBR REFRESH cycles, either uniformly spaced or
grouped in bursts, every 64ms. The MT4LC16M4G3
internally refreshes two rows for every CBR cycle,
whereas the MT4LC16M4H9 refreshes one row for
every CBR cycle. So with either device, executing 4,096
CBR cycles covers all rows. The CBR refresh will invoke
the internal refresh counter for automatic RAS# ad-
dressing. Alternatively, RAS#-ONLY REFRESH capabil-
ity is inherently provided. However, with this method,
some compatibility issues may become apparent. For
example, both G3 and H9 versions require 4,096 CBR
REFRESH cycles, yet each requires a different number of
RAS#-ONLY REFRESH cycles (G3 = 8,192 and H9 =
4,096). JEDEC strongly recommends the use of CBR
REFRESH for this device.

An optional self refresh mode is also available on the

"S" version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified

RASS. The "S" option allows for

an extended refresh period of 128ms, or 31.25µs per
row for a 4K refresh and 15.625µs per row for an 8K
refresh, when using a distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as
well as during a standby or battery backup mode.

GENERAL DESCRIPTION (Continued)

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

V
V

IH
IL

CAS#

V
V

IH
IL

RAS#

V
V

IH
IL

ADDR

ROW

COLUMN (A)

DON'T CARE

UNDEFINED

V
V

IH
IL

WE#

V
V

IOH
IOL

OPEN

tWPZ

The DQs go to High-Z if WE# falls and, if

WPZ is met,

will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).

V
V

IH
IL

OE#

VALID DATA (B)

WHZ

WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).

WHZ

COLUMN (D)

VALID DATA (A)

COLUMN (B)

COLUMN (C)

INPUT DATA (C)

Figure 2

WE# Control of DQs

V
V

IH
IL

CAS#

V
V

IH
IL

RAS#

V
V

IH
IL

ADDR

ROW

COLUMN (A)

COLUMN (B)

V
V

IH
IL

OE#

V
V

IOH
IOL

OPEN

tOD

VALID DATA (B)

VALID DATA (A)

COLUMN (C)

VALID DATA (A)

tOE

VALID DATA (C)

COLUMN (D)

VALID DATA (D)

tOD

tOEHC

tOD

tOEP

tOES

The DQs go back to
Low-Z if

OES is met.

The DQs remain High-Z
until the next CAS# cycle
if

OEHC is met.

The DQs remain High-Z
until the next CAS# cycle
if

OEP is met.

Figure 1

OE# Control of DQs

The self refresh mode is terminated by driving RAS#

HIGH for a minimum time of

RPS. This delay allows for

the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller uses RAS#-ONLY or burst CBR refresh, all rows

must be refreshed with a refresh rate of

RC minimum

prior to resuming normal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.

DRAM REFRESH (Continued)

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

Relative to V

................ -1V to +4.6V

Voltage on NC, Inputs or I/O Pins

Relative to V

....................................... -1V to +4.6V

Operating Temperature, T

(ambient) ... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 1W

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Note: 1) (V

= +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC

+ 0.3

INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC

-0.3

0.8

INPUT LEAKAGE CURRENT:
Any input at V

(0V

+ 0.3V);

-2

µA

All other pins not under test = 0V

OUTPUT HIGH VOLTAGE:
I

OUT

= -2mA

2.4

OUTPUT LOW VOLTAGE:
I

OUT

= 2mA

0.4

OUTPUT LEAKAGE CURRENT:
Any output at V

OUT

(0V

OUT

+ 0.3V);

-5

µA

DQ is disabled and in High-Z state

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6) (V

= +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

SPEED

REFRESH REFRESH UNITS NOTES

STANDBY CURRENT: TTL

ALL

(RAS# = CAS# = V

)

STANDBY CURRENT: CMOS
(RAS# = CAS#

- 0.2V; DQs may be left open;

ALL

500

µA

Other inputs: V

- 0.2V or V

0.2V)

OPERATING CURRENT: Random READ/WRITE

-5

170

130

Average power supply current

-6

160

120

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

OPERATING CURRENT: EDO PAGE MODE

-5

150

Average power supply current

-6

120

(RAS# = V

, CAS#, address cycling:

PC =

PC [MIN])

REFRESH CURRENT: RAS#-ONLY

-5

170

130

Average power supply current

-6

160

120

(RAS# cycling, CAS# = V

RC =

RC [MIN])

REFRESH CURRENT: CBR

-5

160

4, 7

Average power supply current

-6

150

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

REFRESH CURRENT: Extended ("S" version only)
Average power supply current: CAS# = 0.2V or CBR cycling;

ALL

400

µA

4, 7

RAS# =

RAS (MIN); WE# = V

- 0.2V; A0-A11, OE# and

= V

- 0.2V or 0.2V (D

may be left open)

REFRESH CURRENT: Self ("S" version only)
Average power supply current: CBR with
RAS#

RASS (MIN) and CAS# held LOW;

ALL

400

µA

4, 7

WE# = V

- 0.2V; A0-A11, OE# and D

= V

- 0.2V or 0.2V

may be left open)

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

CAPACITANCE

(Note: 2)

PARAMETER

SYMBOL

MAX

UNITS

Input Capacitance: Address pins

Input Capacitance: RAS#, CAS#, WE#, OE#

Input/Output Capacitance: DQ

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (V

= +3.3V ±0.3V)

AC CHARACTERISTICS

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access time from column address

Column-address setup to CAS# precharge

ACH

Column-address hold time (referenced to RAS#)

Column-address setup time

ASC

Row-address setup time

ASR

Column address to WE# delay time

AWD

Access time from CAS#

CAC

Column-address hold time

CAH

CAS# pulse width

CAS

10,000

CAS# LOW to "Don't Care" during Self Refresh

CHD

CAS# hold time (CBR Refresh)

CHR

CAS# to output in Low-Z

CLZ

Data output hold after CAS# LOW

COH

CAS# precharge time

Access time from CAS# precharge

CPA

CAS# to RAS# precharge time

CRP

CAS# hold time

CSH

CAS# setup time (CBR Refresh)

CSR

CAS# to WE# delay time

CWD

WRITE command to CAS# lead time

CWL

Data-in hold time

Data-in setup time

Output disable

23, 24

Output enable time

OE# hold time from WE# during

OEH

READ-MODIFY-WRITE cycle

OE# HIGH hold time from CAS# HIGH

OEHC

OE# HIGH pulse width

OEP

OE# LOW to CAS# HIGH setup time

OES

Output buffer turn-off delay

OFF

17, 23

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (V

= +3.3V ±0.3V)

AC CHARACTERISTICS

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

OE# setup prior to RAS# during

ORD

HIDDEN REFRESH cycle

EDO-PAGE-MODE READ or WRITE cycle time

EDO-PAGE-MODE READ-WRITE cycle time

PRWC

Access time from RAS#

RAC

RAS# to column-address delay time

RAD

Row-address hold time

RAH

RAS# pulse width

RAS

10,000

RAS# pulse width (EDO PAGE MODE)

RASP

125,000

RAS# pulse width during Self Refresh

RASS

100

µs

Random READ or WRITE cycle time

104

RAS# to CAS# delay time

RCD

READ command hold time (referenced to CAS#)

RCH

READ command setup time

RCS

Refresh period

REF

Refresh period (4,096 cycles) "S" version

REF

128

RAS# precharge time

RAS# to CAS# precharge time

RPC

RAS# precharge time exiting Self Refresh

RPS

105

READ command hold time (referenced to RAS#)

RRH

RAS# hold time

RSH

READ-WRITE cycle time

RWC

116

140

RAS# to WE# delay time

RWD

WRITE command to RAS# lead time

RWL

Transition time (rise or fall)

WRITE command hold time

WCH

WRITE command hold time (referenced to RAS#)

WCR

WE# command setup time

WCS

WE# to outputs in High-Z

WHZ

WRITE command pulse width

WE# pulse width to disable outputs

WPZ

WE# hold time (CBR Refresh)

WRH

4, 23

WE# setup time (CBR Refresh)

WRP

4, 23

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

NOTES

All voltages referenced to V

This parameter is sampled. V

= +3.3V; f = 1

MHz; T

= 25°C.

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time and the outputs open.

Enables on-chip refresh and address counters.

The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range is ensured.

An initial pause of 100µs is required after power-
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the

REF

refresh requirement is exceeded.

AC characteristics assume

T = 2.5ns.

(MIN) and V

(MAX) are reference levels for

measuring timing of input signals. Transition
times are measured between V

and V

(or

between V

and V

In addition to meeting the transition rate
specification, all input signals must transit
between V

and V

(or between V

and V

) in a

monotonic manner.

10. If CAS# and RAS# = V

, data output is High-Z.

11. If CAS# = V

, data output may contain data from

the last valid READ cycle.

12. Measured with a load equivalent to two TTL

gates and 100pF; and V

= 0.8V and V

= 2V.

13. If CAS# is LOW at the falling edge of RAS#,

output data will be maintained from the previous
cycle. To initiate a new cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for

CP.

14. The

RAD (MAX) limit is no longer specified.

RAD (MAX) was specified as a reference point

only. If

RAD was greater than the specified

RAD

(MAX) limit, then access time was controlled
exclusively by

AA (

RAC and

CAC no longer

applied). With or without the

RAD (MAX) limit,

AA,

RAC, and

CAC must always be met.

15. The

RCD (MAX) limit is no longer specified.

RCD (MAX) was specified as a reference point

only. If

RCD was greater than the specified

RCD

(MAX) limit, then access time was controlled
exclusively by

CAC (

RAC [MIN] no longer

applied). With or without the

RCD limit,

and

CAC must always be met.

16. Either

RCH or

RRH must be satisfied for a READ

cycle.

17.

OFF (MAX) defines the time at which the output

achieves the open circuit condition and is not
referenced to V

or V

18.

WCS,

RWD,

AWD,

and

CWD

are

not

restrictive

operating

parameters.

WCS

applies

EARLY

WRITE

cycles.

WCS

(MIN),

the

cycle

EARLY

WRITE

cycle

and

the

data

output

will

remain

open

circuit

throughout

the

entire

cycle.

RWD,

AWD,

and

CWD

define

READ-

MODIFY-WRITE

cycles.

Meeting

these

limits

allows

for

reading

and

disabling

output

data

and

then

applying

input

data.

OE#

held

HIGH

and

WE#

taken

LOW

after

CAS#

goes

LOW

results

LATE

WRITE

(OE#-controlled)

cycle.

WCS,

RWD,

CWD,

and

AWD

are

not

applicable

LATE

WRITE

cycle.

19. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.

20. If OE# is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not
possible.

21. A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.

22. RAS#-ONLY REFRESH requires that all rows be

refreshed at least once every 64ms (4,096 rows
for the H9 version and 8,192 rows for the G3
version). CBR REFRESH requires that at least
4,096 cycles be completed every 64ms.

23. The DQs open during READ cycles once

OD or

OFF occur. If CAS# stays LOW while OE# is

brought HIGH, the DQs will open. If OE# is
brought back LOW (CAS# still LOW), the DQs
will provide the previously read data.

24. LATE WRITE and READ-MODIFY-WRITE cycles

must have both

OD and

OEH met (OE# HIGH

during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. If OE# is taken back LOW while CAS#
remains LOW, the DQs will remain open.

25. Column address changed once each cycle.
26. V

overshoot: V

(MAX) = V

+ 2V for a pulse

width

10ns, and the pulse width cannot be

greater than one third of the cycle rate. V

undershoot: V

(MIN) = -2V for a pulse width

10ns, and the pulse width cannot be greater than
one third of the cycle rate.

27. NC pins are assumed to be left floating and are

not tested for leakage.

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

READ CYCLE

tRRH

tCLZ

tCAC

tRAC

tAA

VALID DATA

OPEN

tOFF

tRCH

ROW

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD

tCAS

tRSH

tCSH

tRP

tRC

tRAS

tCRP

tASR

ROW

OPEN

RAS#

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

tOD

tOE

OE#

V
V

IH
IL

COLUMN

CAS#

WE#

NOTE 1

tACH

DON'T CARE

UNDEFINED

NOTE: 1.

OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OFF

RAC

RAD

RAH

RAS

10,000

104

RCD

RCH

RCS

RRH

RSH

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CRP

CSH

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

EARLY WRITE CYCLE

DON'T CARE

UNDEFINED

V
V

IH
IL

VALID DATA

ROW

COLUMN

ROW

tDS

tWP

tWCH

tWCS

tWCR

tRWL

tCWL

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCAS

tRSH

tCSH

tRCD

tCRP

tRAS

tRC

tRP

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

tDH

WE#

CAS#

tACH

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAH

RAS

10,000

104

RCD

RSH

RWL

WCH

WCR

WCS

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAH

CAS

10,000

CRP

CSH

CWL

RAD

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

VALID D

OUT

VALID D

ROW

COLUMN

ROW

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OPEN

tOE

tOD

tCAC

tRAC

tAA

tCLZ

tDS

tDH

tAWD

tWP

tRWL

tCWL

tCWD

tRWD

tRCS

tASC

tCAH

tAR

tASR

tRAD

tCRP

tRCD

tCAS

tRSH

tCSH

tRAS

tRWC

tRP

tRAH

OE#

tOEH

WE#

tACH

CAS#

DON' T CARE

UNDEFINED

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OEH

RAC

RAD

RAH

RAS

10,000

RCD

RCS

RSH

RWC

116

140

RWD

RWL

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

AWD

CAC

CAH

CAS

10,000

CLZ

CRP

CSH

CWD

CWL

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE READ CYCLE

VALID

DATA

VALID

DATA

VALID

DATA

COLUMN

ROW

DON'T CARE

UNDEFINED

tOD

tCAH

tASC

tCP

tRSH

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

tCAH

tASC

tCAH

tASC

tAR

tRAH

tRAD

tASR

tRCS

tRRH

tRCH

tOFF

tCAC

tCPA

tAA

tCLZ

tCAC

tCPA

tAA

tCAC

tRAC

tAA

tCLZ

tOE

tOD

tOE

tOD

OPEN

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

RAS#

OE#

tCAS

CAS#

WE#

tCOH

tOEP

tOEHC

tOES

tACH

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OEHC

OEP

OES

OFF

RAC

RAD

RAH

RASP

125,000

RCH

RCD

RCS

RRH

RSH

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

COH

CPA

CRP

CSH

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

tDS

tDH

tDS

tDH

tDS

tDH

tWCR

VALID DATA

tRWL

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tCAH

tASC

tCAH

tASC

tCAH

tASC

tRAH

tASR

tRAD

tACH

tAR

COLUMN

ROW

tCP

tCAS

tRSH

tCP

tCAS

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

t RP

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

V
V

IH
IL

V
V

IOH
IOL

RAS#

DON'T CARE

UNDEFINED

EDO-PAGE-MODE EARLY WRITE CYCLE

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAD

RAH

RASP

125,000

RCD

RSH

RWL

WCH

WCR

WCS

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAH

CAS

10,000

CRP

CSH

CWL

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

VALID D

OUT

VALID D

ROW

COLUMN

ROW

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OPEN

tOE

tOD

tCAC

tRAC

tAA

tCLZ

tDS

tDH

tAWD

tWP

tRWL

tCWL

tCWD

tRWD

tRCS

tASC

tCAH

tAR

tASR

tRAD

tCRP

tRCD

tCAS

tRSH

tCSH

tRAS

tRWC

tRP

tRAH

OE#

tOEH

WE#

tACH

CAS#

DON'T CARE

UNDEFINED

NOTE: 1.

PC is for LATE WRITE cycles only.

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OEH

PRWC

RAC

RAD

RAH

RASP

125,000

RCD

RCS

RSH

RWD

RWL

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

AWD

CAC

CAH

CAS

10,000

CLZ

CPA

CRP

CSH

CWD

CWL

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

V
V

IH
IL

V
V

IH
IL

RAS#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

tRASP

tRP

ROW

COLUMN (A)

COLUMN (N)

ROW

V
V

IH
IL

OE#

V
V

IOH
IOL

tCRP

tCSH

tCAS

tRCD

tASR

tRAH

tRAD

tASC

tAR

tCAH

tASC

tCAH

tASC

tCAH

tCP

tRSH

VALID DATA

tRCS

tRCH

tWCS

tOE

VALID

DATA (B)

VALID DATA (A)

tWHZ

tCAC

tCPA

tAA

tCAC

tAA

OPEN

tPC

RAC

tCOH

tWCH

tDS

tDH

tPC

COLUMN (B)

tACH

CAS#

tCAS

tCP

DON'T CARE

UNDEFINED

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RSH

WCH

WCS

WHZ

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAC

CAH

CAS

10,000

COH

CPA

CRP

CSH

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

READ CYCLE

(With WE#-controlled disable)

tCLZ

tCAC

tRAC

tAA

VALID DATA

OPEN

tRCH

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD

tCAS

tCSH

tCRP

tASR

ROW

OPEN

RAS#

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

tOD

tOE

OE#

V
V

IH
IL

COLUMN

WE#

tWHZ

tWPZ

tCP

tASC

tRCS

COLUMN

tCLZ

DON'T CARE

UNDEFINED

CAS#

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAC

RAD

RAH

RCD

RCH

RCS

WHZ

WPZ

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CRP

CSH

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 Rev. 5/00

16 MEG x 4

EDO DRAM

HIDDEN REFRESH CYCLE

(WE# = HIGH; OE# = LOW)

DON'T CARE

UNDEFINED

tCLZ

tOFF

OPEN

VALID DATA

OPEN

COLUMN

ROW

tCAC

tRAC

tAA

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCRP

tRCD

tRSH

tRAS

tRP

tCHR

tRAS

V
V

OH
OL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

RAS#

V
V

IH
IL

tOE

tOD

OE#

tORD

CAS#

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OFF

ORD

RAC

RAD

RAH

RAS

10,000

RCD

RSH

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CHR

CLZ

CRP

NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT4LC16M4G3DJ-5

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT4LC16M4G3DJ-5