PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev. 10/02

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

9Mb QDR

SRAM

2-WORD BURST

MT54V512H18A

Features

· 9Mb Density (512K x 18)
· Separate independent read and write data ports

with concurrent transactions

· 100 percent bus utilization DDR READ and WRITE

operation

· High-frequency operation with future migration to

higher clock frequencies

· Fast clock to valid data times
· Full data coherency, providing most current data
· Two-tick burst counter for low DDR transaction size
· Double data rate operation on read and write ports
· Two input clocks (K and K#) for precise DDR timing

at clock rising edges only

· Two output clocks (C and C#) for precise flight time

and clock skew matching--clock and data delivered
together to receiving device

· Single address bus
· Simple control logic for easy depth expansion
· Internally self-timed, registered writes
· +2.5V core and HSTL I/O
· Clock-stop capability
· 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

package

· User-programmable impedence output
· JTAG boundary scan

General Description

The Micron

QDRTM (Quad Data RateTM) synchro-

nous, pipelined burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS
process. The QDR architecture consists of two separate
DDR (double data rate) ports to access the memory
array. The read port has dedicated data outputs to sup-
port READ operations. The write port has dedicated
data inputs to support WRITE operations. This archi-
tecture eliminates the need for high-speed bus turn-
around. Access to each port is accomplished using a
common address bus. Addresses for reads and writes
are latched on rising edges of the K and K# input
clocks, respectively. Each address location is associ-
ated with two 18-bit words that burst sequentially into
or out of the device. Because data can be transferred
into and out of the device on every rising edge of both
clocks (K, K#, C and C#), memory bandwidth is maxi-
mized and system design is simplified by eliminating
bus turnarounds.

OPTIONS

MARKING

NOTE:

1. A

Part Marking Guide for the FBGA devices can be found on

Micron's Web site--

http://www.micron.com/numberguide

· Clock Cycle Timing

6ns (167 MHz)

-6

7.5ns (133 MHz)

-7.5

10ns (100 MHz)

-10

· Configurations

512K x 18

MT54V512H18A

· Package

165-ball, 13mm x 15mm FBGA

Table 1:

Valid Part Numbers

PART NUMBER

DESCRIPTION

MT54V512H18AF-xx

512K x 18, QDRb2 FBGA

Figure 1:

165-Ball FBGA

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Depth expansion is accomplished with port selects

for each port (read R#, write W#) which are received at
K rising edge. Port selects permit independent port

operation. All synchronous inputs pass through regis-

ters controlled by the K or K# input clock rising edges.
Active LOW byte writes (BW0#, BW1#) permit byte
write selection. Write data and byte writes are regis-
tered on the rising edges of both K and K#. The
addressing within each burst of two is fixed and
sequential, beginning with the lowest address and
ending with the highest one. All synchronous data out-
puts pass through output registers controlled by the
rising edges of the output clocks (C and C# if provided,
otherwise K and K#).

Four balls are used to implement JTAG test capabili-

ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.

The SRAM operates from a +2.5V power supply, and

all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.

Please refer to Micron's Web site (

www.micron.com/

sramds

) for the latest data sheet.

READ/WRITE Operations

All bus transactions operate on an uninterruptable

burst of two data, requiring one full clock cycle of bus
utilization. The resulting benefit is that short data

transactions can remain in operation on both buses
providing that the address rate can be maintained by
the system (2x the clock frequency).

READ cycles are pipelined. The request is initiated

by asserting R# LOW at K rising edge. Data is delivered
after the next rising edge of K using C and C# as the
output timing references, or using K and K#, if C and
C# are tied HIGH. If C and C# are tied HIGH, they may
not be toggled during device operation. Output tri-
stating is automatically controlled such that the bus is
released if no data is being delivered. This permits
banked SRAM systems with no complex OE timing
generation. Back-to-back READ cycles are initiated
every K rising edge.

WRITE cycles are initiated by W# LOW at K rising

edge. The address for the WRITE cycle is provided at
the following K# rising edge. Data is expected at the
rising edge of K and K#, beginning at the same K which
initiated the cycle. Write registers are incorporated to
facilitate pipelined, self-timed WRITE cycles and to
provide fully coherent data for all combinations of
READs and WRITEs. A READ can immediately follow a
WRITE even if they are to the same address. Although
the WRITE data has not been written to the memory
array, the SRAM will deliver the data from the write
register instead of using the older data from the mem-
ory array. The latest data is always utilized for all bus
transactions. WRITE cycles can be initiated on every K
rising edge.

Figure 2:

Functional Block Diagram: 512K x 18

NOTE:

1. The functional block diagram illustrates simplified device operation. See truth tables, ball descriptions, and timing

diagramsfor detailed information.

2. n = 18

ADDRESS

D (Data In)

BW0#
BW1#

2 x 36

MEMORY

ARRAY

ADDRESS

REGISTRY

& LOGIC

DATA

REGISTRY

& LOGIC

C,C#

(Data Out)

R
E

T
E

MUX

E
R

T
E

O
U

T
P

O
U

T
P

R
E

F
F
E

P
S

S
E

O
U

T
P

S
E
L
E

C
T

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

BYTE WRITE Operations

BYTE WRITE operations are supported. The active

LOW byte write controls, BW0# and BW1#, are regis-
tered coincident with their corresponding data. This
feature can eliminate the need for some READ/MOD-
IFY/WRITE cycles, collapsing it to a single BYTE
WRITE operation in some instances.

Programmable Impedance Output

Buffer

The QDR SRAM is equipped with programmable

impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V

. The value of the

resistor must be five times the desired impedance. For
example, a 350

W resistor is required for an output

impedance of 70

W . To ensure that output impedance

is one fifth the value of RQ (within 10 percent), the
range of RQ is 175

W to 350W . Alternately, the ZQ ball

can be connected directly to V

Q, which will place

the device in a minimum impedance mode.

Output impedance updates may be required

because, over time, variations may occur in supply
voltage and temperature. The device samples the value
of RQ. Impedance updates are transparent to the sys-
tem; they do not affect device operation, and all data
sheet timing and current specifications are met during
an update.

The device will power up with an output impedance

set at 50

W . To guarantee optimum output driver

impedance after power-up, the SRAM needs 1,024

cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.

Clock Considerations

The device does not utilize internal phase-locked

loops and can therefore be placed into a stopped-clock
state to minimize power without lengthy restart times.
It is strongly recommended that the clocks operate for
a number of cycles prior to initiating commands to the
SRAM. This delay permits transmission line charging
effects to be overcome and allows the clock timing to
be nearer to its steady-state value.

Single Clock Mode

The SRAM can be used with the single K, K# clock

pair by tying C and C# HIGH. In this mode, the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.

Depth Expansion

Port select inputs are provided for the read and

write ports. This allows for easy depth expansion. Both
port selects are sampled on the rising edge of K only.
Each port can be independently selected and dese-
lected and do not affect the operation of the opposite
port. All pending transactions are completed prior to a
port deselecting.

Figure 3:

Application Example

Vt = V

REF

C C#

D
SA

C C#

D
SA

BUS

MASTER

(CPU

ASIC)

SRAM #1

SRAM #4

DATA IN

DATA OUT

Addresses

Read#

Write#

BWn#

Return CLK

Source CLK

Return CLK#

Source CLK#

R = 50

R = 250

R
#

n
#

R
#

n
#

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Table 2:

Ball Assignment (Top View)

165-Ball FBGA

DNU

NC/

BW1#

NC/

DNU

BW0#

D10

D11

Q10

Q11

Q12

D12

D13

Q13

REF

D14

Q14

Q15

D15

D16

D17

Q16

Q17

TDO

TCK

TMS

TDI

NOTE:

1. Expansion address: 2A for 144Mb
2. Expansion address: 3A for 36Mb
3. Expansion address: 9A for 18Mb
4. Expansion address: 10A for 72Mb

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Table 3:

Ball Descriptions

SYMBOL

TYPE

DESCRIPTION

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K for READ cycles and must meet the setup and hold times
around the rising edge of K# for WRITE cycles. See Ball Assignment figures for address
expansion inputs. All transactions operate on a burst of two 18-bit data (one clock period of
bus activity). These inputs are ignored when both ports are deselected.

Input

Synchronous Read: When LOW, this input causes the address inputs to be registered and a
READ cycle to be initiated. This input must meet setup and hold times around the rising edge
of K.

Input

Synchronous Write: When LOW, this input causes the address inputs to be registered and a
WRITE cycle to be initiated. This input must meet setup and hold times around the rising
edge of K.

BW0#
BW1#

Input

Synchronous Byte Writes: When LOW, these inputs cause their respective bytes to be
registered and written if W# had initiated a WRITE cycle. These signals must meet setup and
hold times around the rising edges of K and K# for each of the two rising edges comprising
the WRITE cycle. BW0# controls D0:D8, and BW1# controls D9:D17. See Ball Assignment
figures for signal to data relationships.

Input

Input Clock: This input clock pair registers address and control inputs on the rising edge of K,
and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees
out of phase with K. All synchronous inputs must meet setup and hold times around the clock
rising edges.

Input

Output Clock: This clock pair provides a user-controlled means of tuning device output data.
The rising edge of C is used as the output timing reference for the first output data. The
rising edge of C# is used as the output reference for second output data. Ideally, C# is 180
degrees out of phase with C. C and C# may be tied HIGH to force the use of K and K# as the
output reference clocks instead of having to provide C and C# clocks. If tied HIGH, these
inputs may not be allowed to toggle during device operation.

TMS

TDI

Input

IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These balls may be left as No Connects
if the JTAG function is not used in the circuit.

TCK

Input

IEEE 1149.1 Clock Input: JEDEC-standard 2.5V I/O levels. This ball must be tied to V

if the

JTAG function is not used in the circuit.

REF

Input

HSTL Input Reference Voltage: Nominally V

Q/2, but may be adjusted to improve system

noise margin. Provides a reference voltage for the HSTL input buffer trip point.

Input

Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor
from this ball to ground. Alternately, this ball can be connected directly to V

Q, which

enables the minimum impedance mode. This ball cannot be connected directly to GND or left
unconnected.

Input

Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges
of K and K# during WRITE operations. See Ball Assignment figures for ball site location of
individual signals.

TDO

Output

IEEE 1149.1 Test Output: 1.8V I/0 level.

DNU

Output

Do Not Use: These balls should not be used.

Output

Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. This bus operates in response to R# commands.
See Ball Assignment figures for ball site location of individual signals.

Supply

Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for
range.

Supply

Power Supply: Isolated Output Buffer Supply. Nominally 2.5V. See DC Electrical Characteristics
and Operating Conditions for range.

Supply

Power Supply: GND.

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Figure 4:

Bus Cycle State Diagram

NOTE:

1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is

always fixed as xxx . . . xxx + 0, xxx . . . xxx + 1. Bus cycle is terminated at the end of this sequence (burst count = 2).

2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be simultaneously active.
4. State machine, control timing sequence is controlled by K.

LOAD NEW

READ ADDRESS

READ DOUBLE

POWER-UP

Supply voltage

provided

READ PORT NOP

R_Init=0

always

/RD

LOAD NEW

WRITE ADDRESS

AT K#

WRITE DOUBLE

AT K#

Supply voltage

provided

WRITE PORT NOP

always

/WT

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

NOTE:

1. X means "Don't Care." H means logic HIGH. L means logic LOW.

means rising edge; ¯ means falling edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C

and C# are HIGH, then data outputs are delivered at K and K# rising edges.

3. R# and W# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at the rising

edge of K.

4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by

overcoming transmission line charging symmetrically.

7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation

provided that the setup and hold requirements are satisfied.

Table 4:

Truth Table

Notes 1-6

OPERATION

D or Q

WRITE Cycle:
Load address, input write data on
consecutive K and K# rising edges

®H

(A + 0)

K(t)

(A + 1)

#(t)

READ Cycle:
Load address, output data on
consecutive C and C# rising edges

®H

(A + 0)

C(t + 1)

(A + 1)

C#(t + 1)

NOP: No operation

®H

D = X

Q = High-Z

D = X

Q = High-Z

STANDBY: Clock stopped

Stopped

State

Table 5:

BYTE WRITE Operation

Note 7

OPERATION

BW0#

BW1#

WRITE D0-17 at K rising edge

WRITE D0-17 at K# rising edge

WRITE D0-8 at K rising edge

WRITE D0-8 at K# rising edge

WRITE D9-17 at K rising edge

WRITE D9-17 at K# rising edge

WRITE nothing at K rising edge

WRITE nothing at K# rising edge

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Stresses greater than those listed under Absolute

Maximum Ratings may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.

Maximum junction temperature depends upon

package type, cycle time, loading, ambient tempera-
ture, and airflow. See Micron Technical Note TN-05-14
for more information.

Absolute Maximum Ratings

Voltage on V

Supply

Relative to V

........................................-0.5V to +3.6V

Voltage on V

Q Supply

Relative to V

........................................ -0.5V to +V

..................................................... -0.5V to V

+ 0.5V

Storage Temperature ............................. -55ºC to +125ºC
Junction Temperature .......................................... +125ºC
Short Circuit Output Current .............................. ±70mA

Table 6:

DC Electrical Characteristics And Operating Conditions

Notes appear following parameter tables; 0°C

£ T

£ +70°C; +2.4V £ V

£ +2.6V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.1

Q + 0.3

3, 4

Input Low (Logic 0) Voltage

(

DC)

-0.3

REF

- 0.1

3, 4

Clock Input Signal Voltage

-0.3

Q + 0.3

3, 4

Input Leakage Current

£ V

-5

µA

Output Leakage Current

Output(s) disabled,

£ V

Q (Q)

-5

µA

Output High Voltage

£ 0.1mA

(

LOW

)

Q - 0.2

3, 5, 7

Note 1

Q/2 - 0.12

Q/2 + 0.12

3, 5, 7

Output Low Voltage

£ 0.1mA

(

LOW

)

0.2

3, 5, 7

Note 2

Q/2 - 0.12

Q/2 + 0.12

3, 5, 7

Supply Voltage

2.4

2.6

Isolated Output Buffer Supply

1.4

1.6

3, 6

Reference Voltage

REF

0.68

0.9

Table 7:

AC Electrical Characteristics And Operating Conditions

Notes appear following parameter tables; 0°C

£ T

£ +70°C; +2.4V £ V

£ +2.6V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.2

3, 4, 8

Input Low (Logic 0) Voltage

(

)

REF

- 0.2

3, 4, 8

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Table 9:

Capacitance

Note 14

Table 10: Thermal Resistance

Note 14; notes appear following parameter tables

Table 8:

Operating Conditions and Maximum Limits

Notes appear following parameter tables

;

0°C

£ T

£ +70°C; V

= MAX unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

TYP

-6

-7.5

-10

UNITS

NOTES

Operating Supply Current:

DDR

All inputs

£ V

³ V

; Cycle

time

KHKH (MIN); Outputs

open

585

825

700

550

9, 10, 11

Standby Supply Current:

NOP

KHKH =

KHKH (MIN);

Device in NOP state;

All addresses/data static

150

250

225

175

10, 12

Output Supply

Cycle Time = 0; Input Static

TBD

Current: DDR

(For information only)

= 15pF

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

Address/Control Input Capacitance

= 25ºC; f = 1 MHz

Output Capacitance (D,Q)

Clock Capacitance

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

NOTES

Junction to Ambient

(Airflow of 1m/s)

Soldered on a 4.25 x 1.125 inch, 4-layer,

printed circuit board

ºC/W

Junction to Case (Top)

ºC/W

Junction to Balls (Bottom)

ºC/W

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Table 11: AC Electrical Characteristics And Recommended

Operating Conditions

Notes 14, 17-19; notes appear following parameter tables; 0°C

£ T

£ +70°C; +2.4V £ V

£ +2.6V

DESCRIPTION

SYMBOL

-6

-7.5

-10

UNITS NOTES

MIN

MAX

MIN

MAX

MIN

MAX

Clock
Clock cycle time (K, K#, C, C#)

KHKH

6.0

7.5

Clock HIGH time (K, K#, C, C#)

KHKL

2.4

3.0

3.5

Clock LOW time (K, K#, C, C#)

KLKH

2.4

3.0

3.5

Clock to clock# (K

®K#, C®C#) at

KHKH minimum

KHK#H

2.7

3.4

4.6

Clock# to clock (K#

®K, C#®C)at

KHKH minimum

K#HKH

2.7

3.4

4.6

Clock to data clock (K

®C

®C#)

KHCH

0.0

2.0

0.0

2.5

0.0

3.0

Output Times
C, C# HIGH to output valid

CHQV

2.5

3.0

C, C# HIGH to output hold

CHQX

1.2

C HIGH to output HIGH-Z

CHQZ

2.5

3.0

20, 21

C HIGH to output LOW-Z

CHQX1

1.2

20, 21

Setup Times
Address valid to K rising edge

AVKH

0.7

0.8

1.0

Control inputs valid to K rising edge

IVKH

0.7

0.8

1.0

Data-in valid to K, K# rising edge

DVKH

0.7

0.8

1.0

Hold Times
K rising edge to address hold

KHAX

0.7

0.8

1.0

K rising edge to control inputs hold

KHIX

0.7

0.8

1.0

K, K# rising edge to data-in hold

KHDX

0.7

0.8

1.0

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Notes

1. Outputs are impedance-controlled. |I

| =

Q/2)/(RQ/5) for values of 175

W £ RQ £ 350W.

2. Outputs are impedance-controlled. I

= (V

2)/(RQ/5) for values of 175

W £ RQ £ 350W.

3. All voltages referenced to V

(GND).

4. Overshoot: V

(

)

£ V

+ 0.7V for t

KHKH/2

Undershoot: V

(

)

³ -0.5V for t £

KHKH/2

Power-up: V

£ V

Q + 0.3V and V

£ 2.4V

and V

£ 1.4V for t £ 200ms

During normal operation, V

Q must not exceed

. R# and W# signals may not have pulse

widths less than

KHKL (MIN) or operate at cycle

rates less than

KHKH (MIN).

5. AC load current is higher than the shown DC val-

ues. AC I/O curves are available upon request.

6. For higher V

Q voltages, contact factory for

product information.

7. HSTL outputs meet JEDEC HSTL Class I and Class

II standard.s

8. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current AC
level through the target AC level, V

(

) or V

(

)

b. Reach at least the target AC level

c. After the AC target level is reached, continue to
maintain at least the target DC level, V

(

) or

(

)

9. I

is specified with no output current and

increases with faster cycle times. I

Q increases

with faster cycle times and greater output loading.
Typical value is measured at 7.5ns cycle time.

10. Typical values are measured at V

=2.5V, V

Q =

1.5V, and temperature = 25°C.

11. Operating supply currents and burst mode cur-

rents are calculated with 50 percent READ cycles
and 50 percent WRITE cycles.

12. NOP currents are valid when entering NOP after

all pending READ and WRITE cycles are com-
pleted.

13. Average I/O current and power is provided for

informational purposes only and is not tested.
Calculation assumes that all outputs are loaded
with C

(in farads), f = input clock frequency, half

of outputs toggle at each transition (for example,
n = 18 for x36), C

= 6pF, V

Q = 1.5V and uses the

equations: Average I/O Power as dissipated by the
SRAM is:

P = 0.5 × n x f x V

x (C

+ 2C

). Average I

Q =

n x f x V

Q x (C

+ C

14. This parameter is sampled.
15. Average thermal resistance between the die and

the case top surface per MIL SPEC 883 Method
1012.1.

16. Junction temperature is a function of total device

power dissipation and device mounting environ-
ment. Measured per SEMI G38-87.

17. Control input signals may not be operated with

pulse widths less than

KHKL (MIN).

18. Test conditions as specified with the output load-

ing as shown in Figure 5, unless otherwise noted.

19. If C, C# are tied HIGH, then K, K# become the ref-

erences for C, C# timing parameters.

20. Transition is measured ±100mV from steady state

voltage.

21.

CHQXI is greater than

CHQZ at any given voltage

and temperature.

22. This is a synchronous device. All addresses, data,

and control lines must meet the specified setup
and hold times for all latching clock edges.

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Figure 6:

READ/WRITE Timing

NOTE:

1. Q00 refers to output from address A0 + 0. Q01 refers to output from the next internal burst address following A0,

i.e., A0 + 1.

2. Outputs are disabled (High-Z) one clock cycle after a NOP.
3. In this example, if address A0 =

A1, data Q00 = D10, Q01 = D11. Write data is forwarded immediately as read results.

READ

WRITE

NOP

READ

WRITE

NOP

D10

tKHKL

tKHK#H

tKHCH

tCHQV

tKLKH

tKHKH

tKHIX

AVKH

KHAX

DVKH

KHDX

tKHCH

DON'T CARE

UNDEFINED

tCHQX1

tCHQZ

tIVKH

tKHKL

tKLKH

AVKH

KHAX

D11

D30

D31

D50

D51

D60

D61

DVKH

KHDX

Q00

Q21

Q01

Q20

Q40

Q41

tCHQV

tCHQX

tKHK#H

tKHKH

(Note 1)

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

IEEE 1149.1 Serial Boundary Scan

(JTAG)

The SRAM incorporates a serial boundary scan test

access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-2001 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are
excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 2.5V I/O logic levels.

The SRAM contains a TAP controller, instruction

Disabling the JTAG Feature

It is possible to operate the SRAM without using the

JTAG feature. To disable the TAP controller, TCK must
be tied LOW (Vss) to prevent clocking of the device.
TDI and TMS are internally pulled up and may be
unconnected. They may alternately be connected to
V

through a pull-up resistor. TDO should be left

unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the opera-
tion of the device

Test Access Port (TAP)
Test Clock (TCK)

The test clock is used only with the TAP controller.

All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.

Figure 7:

TAP Controller State Diagram

NOTE:

The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.

Test Data-In (TDI)

The TDI ball is used to serially input information

into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 7. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most-signifi-
cant bit (MSB) of any register, as illustrated in Figure 8.

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-

out from the registers. The output is active depending
upon the current state of the TAP state machine. (See
Figure 7.) The output changes on the falling edge of
TCK. TDO is connected to the least-significant bit
(LSB) of any register, as depicted in Figure 8.

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Figure 8:

TAP Controller Block Diagram

NOTE:

X = 69 for all configurations.

Performing a TAP RESET

A RESET is performed by forcing TMS HIGH (V

)

for five rising edges of TCK. This RESET does not affect
the operation of the SRAM and may be performed
while the SRAM is operating.

At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO

balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is seri-
ally loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.

Instruction Register

Three-bit instructions can be serially loaded into

the instruction register. This register is loaded when it
is placed between the TDI and TDO balls as shown in
Figure 8. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.

When the TAP controller is in the Capture-IR state,

the two LSBs are loaded with a binary "01" pattern to
allow for fault isolation of the board-level serial test
data path.

Bypass Register

To save time when serially shifting data through reg-

isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with mini-
mal delay. The bypass register is set LOW (V

) when

the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the

input and bidirectional balls on the SRAM. Several no
connect (NC) balls are also included in the scan regis-
ter to reserve balls. The SRAM has a 69-bit-long regis-
ter.

The boundary scan register is loaded with the con-

tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state. The EXTEST, SAMPLE/PRELOAD and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.

The Boundary Scan Order tables show the order in

which the bits are connected. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-

bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.

TAP Instruction Set
Overview

Eight different instructions are possible with the

three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.

The TAP controller used in this SRAM is not fully

compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not

Bypass Register

Instruction Register

Identification Register

Boundary Scan Register

Selection

Circuitry

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI

TDO

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.

Instructions are loaded into the TAP controller dur-

ing the Shift-IR state when the instruction register is
placed between the TDI and TDO balls. During this
state, instructions are shifted through the instruction
register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is

to be executed whenever the instruction register is

loaded with all 0s. EXTEST is not implemented in the

TAP controller, hence, this device is not IEEE 1149.1

compliant.

The TAP controller does recognize an all-0 instruc-

tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a SAM-
PLE/PRELOAD instruction has been loaded. EXTEST
does not place the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary

scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruc-

tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant

When the SAMPLE/PRELOAD instruction is loaded

into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bidirectional balls is captured in the boundary
scan register.

The user must be aware that the TAP controller

clock can only operate at a frequency up to 10 MHz,
while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in
the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not
harm the device, but there is no guarantee as to the
value that will be captured. Repeatable results may not
be possible.

To guarantee that the boundary scan register will

capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP con-
troller's capture setup plus hold time (tCS plus tCH).
The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the C and C# and the K and
K# captured in the boundary scan register.

Once the data is captured, it is possible to shift out

the data by putting the TAP into the Shift-DR state.
This places the boundary scan register between the
TDI and TDO balls.

Note that since the PRELOAD part of the command

is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruc-
tion will have the same effect as the Pause-DR com-
mand.

BYPASS

When the BYPASS instruction is loaded in the

instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and
TDO. The advantage of the BYPASS instruction is that
it shortens the boundary scan path when multiple
devices are connected together on a board.

RESERVED

These instructions are not implemented but are

reserved for future use. Do not use these instructions.

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Figure 9:

TAP Timing

NOTE:

CS and

CH refer to the setup and hold time requirements of latching data from the boundary scan register.

2. Test conditions are specified using the load in Figure 10.

TLTH

Test Clock

(TCK)

Test Mode Select

(TMS)

tTHTL

Test Data-Out

(TDO)

tTHTH

Test Data-In

(TDI)

tTHMX

tMVTH

tTHDX

tDVTH

tTLOX

tTLOV

DON'T CARE

UNDEFINED

Table 12: TAP DC Electrical Characteristics

Notes 1, 2; 0°C

£ T

£ +70°C; +2.4V £ V

£ +2.6V

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Clock

Clock cycle time

THTH

100

Clock frequency

MHz

Clock HIGH time

THTL

Clock LOW time

TLTH

Output Times

TCK LOW to TDO unknown

TLOX

TCK LOW to TDO valid

TLOV

TDI valid to TCK HIGH

DVTH

TCK HIGH to TDI invalid

THDX

Setup Times

TMS setup

MVTH

Capture setup

Hold Times

TMS hold

THMX

Capture hold

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

TAP AC Test Conditions

Input pulse levels . . . . . . . . . . . . . . . . . . . . . V

to 2.5V

Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . 1ns
Input timing reference levels . . . . . . . . . . . . . . . . 1.25V
Output reference levels . . . . . . . . . . . . . . . . . . . . . 1.25V
Test load termination supply voltage . . . . . . . . . 1.25V

Figure 10:

TAP AC Output Load Equivalent

NOTE:

1. All voltages referenced to V

(GND)

2. Overshoot: V

(

)

£ V

+ 0.7V for t

KHKH/2

Undershoot: V

(

)

³ -0.5V for t £

KHKH/2

Power-up: V

£ +2.6 and V

£ +2.4V and V

£ 1.4V for t £ 200ms

During normal operation, V

Q must not exceed V

. Control input signals (LD#, R/W#, etc.) may not have pulse

widths less than

KHKL (MIN) or operate at frequencies exceeding

KF (MAX).

TDO

1.25V

20pF

Z = 50

Table 13: TAP DC Electrical Characteristics And Operating Conditions

0°C

£ T

£ +70°C; +2.4V £ V

£ +2.6V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

1.7

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.7

1, 2

Input Leakage Current

£ V

-5.0

5.0

µA

Output Leakage Current

Output(s) disabled,

£ V

Q (DQx)

-5.0

5.0

µA

Output Low Voltage

OLC

= 100µA

0.2

Output Low Voltage

OLT

= 2mA

0.7

Output High Voltage

OHC

= -100µA

2.1

Output High Voltage

OHT

= -2mA

1.7

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Table 14: Identification Register Definitions

INSTRUCTION FIELD

512K X 18

DESCRIPTION

REVISION NUMBER (31:28)

000

Version number.

DEVICE ID (28:12)

00011000001000000

512K x 18 QDR 2-word burst.

MICRON JEDEC ID CODE
(11:1)

00000101100

Allows unique identification of SRAM vendor.

ID Register Presence
Indicator (0)

Indicates the presence of an ID register.

Table 15: Scan Register Sizes

BIT SIZE (x18)

Instruction

Bypass

Boundary Scan

Table 16: Instruction Codes

INSTRUCTION

CODE

DESCRIPTION

EXTEST

000

Captures I/O ring contents. Places the boundary scan register
between TDI and TDO. This operation does not affect SRAM
operations. This instruction is not 1149.1-compliant.

IDCODE

001

Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM
operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z
state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures I/O ring contents. Places the boundary scan register
between TDI and TDO.Does not affect SRAM operation. This
instruction does not implement 1149.1 preload function and is
therefore not 1149.1-compliant.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does
not affect SRAM operations.

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V512H18A_16_A.fm - Rev 10/02

Table 17: Boundary Scan (Exit) Order

BIT#

SIGNAL NAME

BALL ID

BIT#

SIGNAL NAME

BALL ID

BW0#

BW1#

NC/

SA19

3A; reads as 1

GND/

SA21

2A; reads as 0

10P

Reserved

1A; reads as X

11P

11N

10M

D10

11M

Q10

11L

D11

10K

Q11

11K

D12

11J

Q12

11H

D13

10J

Q13

11G

D14

11F

Q14

10E

D15

11E

Q15

11D

D16

10C

Q16

11C

D17

11B

Q17

Reserved

11A; reads as X

GND/

SA20

10A; reads as 0

NC/

SA18

9A; reads as 1

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. QDR RAMs and Quad Data

Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, Micron Technology, Inc., NEC, and Samsung.

512K x 18

2.5V V

, HSTL, QDRb2 SRAM

0.16µm Process

ADVANCE

512K x 18 2.5V V

, HSTL, QDRb2 SRAM (Footer Desc variable)

MT54V512H18A_16_A.fm - Rev 10/02

Figure 11:

165-Ball FBGA

NOTE:

1. All dimensions are in millimeters.

DATA SHEET DESIGNATION

Advance: This data sheet contains initial descriptions of products still under development.

10.00

14.00

15.00 ±0.10

1.00

TYP

1.00

TYP

5.00 ±0.05

13.00 ±0.10

PIN A1 ID

BALL A1

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 ±0.05

7.00 ±0.05

7.50 ±0.05

1.20 MAX

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb
SOLDER BALL PAD: Ø .33mm

SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40

SEATING PLANE

0.85 ±0.075

0.12 C

165X Ø 0.45

BALL A11

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