Document Outline
- Features
- Options
- General Description
- Dual Voltage I/O
- Functional Block Diagrams
- TQFP Pin Assignment Table
- Pin Assignment 100-Pin TQFP
- TQFP Pin Descriptions
- Pin Layout 165-Pin FBGA
- FBGA Pin Descriptions
- Pin Layout 119-Pin BGA
- BGA Pin Descriptions
- Interleaved Burst Address Table (Mode = NC or HIGH)
- Linear Burst Address Table (Mode = Low)
- Partial Truth Table for Read/Write Commands (x18)
- Partial Truth Table for Read/Write Commands (x32/x36)
- State Diagrams for ZBT SRAM
- Truth Table
- 3.3V VDD, Absolute Maximum Ratings
- 2.5V VDD, Absolute Maximum Ratings
- 3.3V VDD, 3.3V I/O DC Electrical Characteristics and Operating Conditions
- 3.3V VDD, 3.3V, 2.5V I/O DC Electrical Characteristics and Operating Conditions
- 2.5V VDD, 3.3V, 2.5V I/O DC Electrical Characteristics and Operating Conditions
- TQFP Capacitance
- BGA Capacitance
- FBGA Capacitance
- TQFP Thermal Resistance
- BGA Thermal Resistance
- FBGA Thermal Resistance
- 3.3V VDD, IDD Operating Conditions and Maximum Limits (512K x 32/36)
- 2.5V VDD, IDD Operating Conditions and Maximum Limits (512K x 32/36)
- 3.3V VDD, IDD Operating Conditions and Maximum Limits (1 Meg x 18)
- 2.5V VDD, IDD Operating Conditions and Maximum Limits (1 Meg x 18)
- AC Electrical Characteristics
- 3.3V VDD, 3.3V I/O AC Test Conditions
- 3.3V VDD, 2.5V I/O AC Test Conditions
- 2.5V VDD, 2.5V I/O AC Test Conditions
- Load Derating Curves
- 3.3V I/O Output Load Equivalents
- 2.5V I/O Output Load Equivalents
- Snooze Mode
- Snooze Mode Electrical Characteristics
- Snooze Mode Waveform
- Read/Write Timing
- NOP, Stall, and Deselect Styles
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- Disabling the JTAG Feature
- Test Access Port (TAP)
- Test Clock (TCK)
- Test Mode Select (TMS)
- Test Data-In (TDI)
- Test Data-Out (TDO)
- Performing a TAP Reset
- Figure 5 TAP Controller State Diagram
- TAP Registers
- Instruction Register
- Bypass Register
- Boundary Scan Register
- Identification (ID) Register
- Figure 6 TAP Controller Block Diagram
- TAP Instruction Set
- Overview
- EXTEST
- IDCODE
- SAMPLE Z
- SAMPLE/PRELOAD
- BYPASS
- Reserved
- TAP Timing
- TAP AC Electrical Characteristics
- TAP AC Test Conditions
- Figure 7 TAP AC Output Load Equivalent
- 3.3V VDD TAP DC Electrical Characteristics and Operating Conditions
- 2.5V VDD TAP DC Electrical Characteristics and Operating Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- 165-Pin FBGA Boundary Scan Order (x18)
- 165-Pin FBGA Boundary Scan Order (x32)
- 165-Pin FBGA Boundary Scan Order (x36)
- 119-Pin BGA Boundary Scan Order (x18)
- 119-Pin BGA Boundary Scan Order (x32)
- 119-Pin BGA Boundary Scan Order (x36)
- 100-Pin Plastic TQFP (JEDEC LQFP)
- 119-Pin BGA
- 165-Pin FBGA
- Revision History
1
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
2001, Micron Technology, Inc.
MT55L1MY18P_C.p65 Rev. 9/01
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
ADVANCE
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
18Mb
ZBT
SRAM
FEATURES
High frequency and 100 percent bus utilization
Fast cycle times: 6ns, 7.5ns, and 10ns
Single +3.3V 5% or +2.5V 5% power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
Advanced control logic for minimum control signal
interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os, and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to eliminate
the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 4Mb, and 8Mb
ZBT SRAM
OPTIONS
TQFP MARKING
Timing (Access/Cycle/MHz)
3.3V V
DD
, 3.3V or 2.5V I/O
4.2ns/7.5ns/133 MHz
-7.5
5ns/10ns/100 MHz
-10
2.5V V
DD
, 2.5V I/O
3.5ns/6ns/166 MHz
-6
4.2ns/7.5ns/133 MHz
-7.5
5ns/10ns/100 MHz
-10
Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
MT55L1MY18P
512K x 32
MT55L512Y32P
512K x 36
MT55L512Y36P
2.5V V
DD
, 2.5V I/O
1 Meg x 18
MT55V1MV18P
512K x 32
MT55V512V32P
512K x 36
MT55V512V36P
Packages
100-pin TQFP
T
165-pin FBGA
F*
119-pin BGA
B
MT55L1MY18P, MT55V1MV18P,
MT55L512Y32P, MT55V512V32P,
MT55L512Y36P, MT55V512V36P
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
2.5V I/O
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA (PBGA).
119-Pin BGA
2
165-Pin FBGA
100-Pin TQFP
1
* A Part Marking Guide for the FBGA devices can be found on Micron's
Web site--
http://www.micron.com/support/index.html.
Operating Temperature Range
Commercial (0C to +70C)
None
Part Number Example:
MT55L512Y32PT-7.5
2
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
allowable to give an address for each individual READ
and WRITE cycle. BURST cycles wrap around after the
fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
cycle. For example, if a WRITE cycle begins in clock cycle
one, the address is present on rising edge one. BYTE
WRITEs need to be asserted on the same cycle as the
address. The data associated with the address is required
two cycles later, or on the rising edge of clock cycle three.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During a BYTE WRITE cycle, BWa# controls
DQa pins; BWb# controls DQb pins; BWc# controls DQc
pins; and BWd# controls DQd pins. Cycle types can only
be defined when an address is loaded, i.e., when ADV/
LD# is LOW. Parity/ECC bits are only available on the x36
versions.
The device is ideally suited for systems requiring high
bandwidth and zero bus turnaround delays.
Please refer to Micron's Web site (
www.micron.com/
sram
) for the latest data sheet.
DUAL VOLTAGE I/O
The 3.3V V
DD
device is tested for 3.3V and 2.5V I/O
function. The 2.5V V
DD
device is tested for only 2.5V
I/O function.
GENERAL DESCRIPTION
The Micron
Zero Bus Turnaround
TM
(ZBT
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron's 18Mb ZBT SRAMs integrate a 1 Meg x 18,
512K x 32, or 512K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
These SRAMs are optimized for 100 percent bus utiliza-
tion, eliminating any turnaround cycles for READ to
WRITE, or WRITE to READ, transitions. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single clock input (CLK). The synchro-
nous inputs include all addresses, all data inputs, chip
enable (CE#), two additional chip enables for easy depth
expansion (CE2, CE2#), cycle start input (ADV/LD#), syn-
chronous clock enable (CKE#), byte write enables (BWa#,
BWb#, BWc# and BWd#), and read/write (R/W#).
Asynchronous inputs include the output enable (OE#,
which may be tied LOW for control signal minimization),
clock (CLK) and snooze enable (ZZ, which may be tied
LOW if unused). There is also a burst mode pin (MODE)
that selects between interleaved and linear burst modes.
MODE may be tied HIGH, LOW or left unconnected if
burst is unused. The data-out (Q), enabled by OE#, is
registered by the rising edge of CLK. WRITE cycles can be
from one to four bytes wide as controlled by the write
control inputs.
All READ, WRITE, and DESELECT cycles are initiated
by the ADV/LD# input. Subsequent burst addresses can
be internally generated as controlled by the burst ad-
vance pin (ADV/LD#). Use of burst mode is optional. It is
3
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
DQs
DQPa
DQPb
DQPc
DQPd
36
36
36
36
36
36
36
36
K
MODE
19
BWa#
BWb#
BWc#
BWd#
R/W#
CE#
CE2
CE2#
OE#
READ LOGIC
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
512K x 8 x 4
(x32)
512K x 9 x 4
(x36)
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
19
19
17
19
BURST
LOGIC
SA0'
SA1'
D1
D0
Q1
Q0
SA0
SA1
K
19
ADV/LD#
ADV/LD#
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CKE#
WRITE
DRIVERS
SA0, SA1, SA
NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams
for detailed information.
FUNCTIONAL BLOCK DIAGRAM
512K x 32/36
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
18
18
18
18
18
18
18
18
SA0, SA1, SA
K
MODE
20
BWa#
BWb#
R/W#
CE#
CE2
CE2#
OE#
READ LOGIC
DQs
DQPa
DQPb
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
1 Meg x 9 x 2
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
20
20
18
20
BURST
LOGIC
SA0'
SA1'
D1
D0
Q1
Q0
SA0
SA1
K
20
ADV/LD#
ADV/LD#
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CKE#
WRITE
DRIVERS
4
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
PIN #
x18
x32
x36
51
NC
NF
DQPa
1
52
NC
DQa
DQa
53
NC
DQa
DQa
54
V
DD
Q
55
V
SS
56
NC
DQa
DQa
57
NC
DQa
DQa
58
DQa
59
DQa
60
V
SS
61
V
DD
Q
62
DQa
63
DQa
64
ZZ
65
V
DD
66
V
DD
2
67
V
SS
68
DQa
DQb
DQb
69
DQa
DQb
DQb
70
V
DD
Q
71
V
SS
72
DQa
DQb
DQb
73
DQa
DQb
DQb
74
DQa
DQb
DQb
75
NC
DQb
DQb
PIN #
x18
x32
x36
76
V
SS
77
V
DD
Q
78
NC
DQb
DQb
79
NC
DQb
DQb
80
SA
NF
DQPb
1
81
SA
82
SA
83
SA
84
SA
85
ADV/LD#
86
OE# (G#)
87
CKE#
88
R/W#
89
CLK
90
V
SS
91
V
DD
92
CE2#
93
BWa#
94
BWb#
95
NC
BWc# BWc#
96
NC
BWd# BWd#
97
CE2
98
CE#
99
SA
100
SA
PIN #
x18
x32
x36
TQFP PIN ASSIGNMENT TABLE
26
V
SS
27
V
DD
Q
28
NC
DQd
DQd
29
NC
DQd
DQd
30
NC
NF
DQPd
1
31
MODE (LBO#)
32
SA
33
SA
34
SA
35
SA
36
SA1
37
SA0
38
DNU
39
DNU
40
V
SS
41
V
DD
42
DNU
43
DNU
44
SA
45
SA
46
SA
47
SA
48
SA
49
SA
50
SA
PIN #
x18
x32
x36
1
NC
NF
DQPc
1
2
NC
DQc
DQc
3
NC
DQc
DQc
4
V
DD
Q
5
V
SS
6
NC
DQc
DQc
7
NC
DQc
DQc
8
DQb
DQc
DQc
9
DQb
DQc
DQc
10
V
SS
11
V
DD
Q
12
DQb
DQc
DQc
13
DQb
DQc
DQc
14
V
DD
15
V
DD
16
V
DD
2
17
V
SS
18
DQb
DQd
DQd
19
DQb
DQd
DQd
20
V
DD
Q
21
V
SS
22
DQb
DQd
DQd
23
DQb
DQd
DQd
24
DQb
DQd
DQd
25
NC
DQd
DQd
NOTE: 1. NF for x32 version, DQPx for x36 version.
2. Pins 16 and 66 do not have to be connected directly to V
DD
if the input voltage is
V
IH
.
5
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP
NOTE: 1. NF for x32 version, DQx for x36 version.
2. Pins 16 and 66 do not have to be connected directly to V
DD
if the input voltage is
V
IH
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
NC
NC
V
DD
Q
V
SS
NC
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
V
DD
2
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
DD
V
DD
V
DD
2
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
NC
V
SS
V
DD
Q
NC
NC
NC
x18
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NF/
DQP
1
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
V
DD
2
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NF/
DQPa
1
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NF/
DQPc
1
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
DD
V
DD
V
DD
2
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NF/
DQPd
1
x32/x36
6
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS
x18
x32/36
SYMBOL TYPE
DESCRIPTION
37
37
SA0
Input
Synchronous Address Inputs: These inputs are registered
36
36
SA1
and must meet the setup and hold times around the
32-35, 44-50,
32-35, 44-50,
SA
rising edge of CLK. SA0 and SA1 are the two least
80-84, 99, 100
81-84, 99, 100
significant bits (LSB) of the address field and set the
internal burst counter if burst is desired.
93
93
BWa#
Input
Synchronous Byte Write Enables: These active LOW
94
94
BWb#
inputs allow individual bytes to be written when a
95
BWc#
WRITE cycle is active and must meet the setup and hold
96
BWd#
times around the rising edge of CLK. BYTE WRITEs need
to be asserted on the same cycle as the address. BWs are
associated with addresses and apply to subsequent data.
BWa# controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; BWd# controls DQd pins.
89
89
CLK
Input
Clock: This signal registers the address, data, chip
enables, byte write enables, and burst control inputs on
its rising edge. All synchronous inputs must meet setup
and hold times around the clock's rising edge.
98
98
CE#
Input
Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW).
92
92
CE2#
Input
Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.
97
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.
86
86
OE#
Input
Output Enable: This
active LOW, asynchronous input
(G#)
enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.
85
85
ADV/LD# Input
Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is
loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW
on ADV/LD# clocks a new address at the CLK rising edge.
87
87
CKE#
Input
Synchronous Clock Enable: This active LOW input
permits CLK to propagate throughout the device. When
CKE# is HIGH, the device ignores the CLK input and
effectively internally extends the previous CLK cycle. This
input must meet setup and hold times around the rising
edge of CLK.
64
64
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ
is active, all other inputs are ignored. This pin has an
internal pull-down and can be floating.
(continued on next page)
7
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS (continued)
x18
x32/36
SYMBOL TYPE
DESCRIPTION
88
88
R/W#
Input
Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a
new address. A LOW on this pin permits BYTE WRITE
operations and must meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs
occur if all byte write enables are LOW.
31
31
MODE
Input
Mode: This input selects the burst sequence. A LOW on
(LBO#)
this pin selects linear burst. NC or HIGH on this pin
selects interleaved burst. Do not alter input state while
device is operating. LBO# is the JEDEC-standard term for
MODE.
(a)
58, 59, 62, 63,
(a)
52, 53, 56-59,
DQa
Input/
SRAM Data I/Os: Byte "a" associated with is DQa pins;
68, 69, 72-74
62, 63
Output Byte "b" is associated with DQb pins; Byte "c" is
(b)
8, 9, 12, 13,
(b)
68, 69, 72-75,
DQb
associated with DQc pins; Byte "d" is associated with
18, 19, 22-24
78, 79
DQd pins. Input data must meet setup and hold times
(c)
2, 3, 6-9,
DQc
around the rising edge of CLK.
12, 13
(d)
18, 19, 22-25,
DQd
28, 29
51
NF/
DQPa
NF/
No Function/Data Bits: On the x32 version, these pins are
80
NF/
DQPb
I/O
no function (NF) and can be left floating or connected
1
NF/
DQPc
to GND to minimize thermal impedance. On the x36
30
NF/
DQPd
version, these bits are DQs.
No function pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to
leave these pins unconnected or driven by signals.
14, 15, 16, 41, 65, 14, 15, 16, 41, 65,
V
DD
Supply
Power Supply:
See DC Electrical Characteristics and
66, 91
66, 91
Operating Conditions for range.
4, 11, 20, 27,
4, 11, 20, 27,
V
DD
Q
Supply
Isolated Output Buffer Supply:
See DC Electrical
54, 61, 70, 77
54, 61, 70, 77
Characteristics and Operating Conditions for range.
5, 10, 17, 21,
5, 10, 17, 21,
V
SS
Supply
Ground:
GND.
26, 40, 55, 60,
26, 40, 55, 60,
67, 71, 76, 90
67, 71, 76, 90
1-3, 6, 7, 25,
n/a
NC
No Connect: These pins can be left floating or connected
28-30, 51-53, 56,
to GND to minimize thermal impedance.
57, 75, 78, 79,
95, 96
38, 39, 42, 43
38, 39, 42, 43
DNU
Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
8
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
PIN LAYOUT (TOP VIEW)
165-PIN FBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
DQb
DQb
DQb
DQb
DQPb
NC
MODE
(LBO#)
BWb#
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
NC
BWa#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CE2#
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
SA1
SA0
CKE#
R/W#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
TDO
TCK
ADV/L D#
OE# (G#)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
SA
SA
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
SA
SA
SA
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
SA
TOP VIEW
3
4
5
6
7
8
9
10
11
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NC
NC
NC
NC
NC
NF/
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NF/
DQPd
NC
MODE
(LBO#)
BWc#
BWd#
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
BWb#
BWa#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CE2#
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
SA1
SA0
CKE#
R/W#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
TDO
TCK
ADV/LD#
OE# (G#)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
SA
SA
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
SA
SA
NC
NC
NF/
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NF/
DQPa
NC
SA
TOP VIEW
3
4
5
6
7
8
9
10
11
1
x18
x32/x36
*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
9
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
6R
6R
SA0
Input
Synchronous Address Inputs: These inputs are registered and
6P
6P
SA1
must meet the setup and hold times around the rising edge of
2A, 9A, 10A, 2A, 9A, 10A,
SA
CLK.
11A, 2B, 9B,
2B, 9B, 10B,
10B, 3P, 4P,
3P, 4P, 8P,
8P, 9P, 10P,
9P, 10P, 3R,
3R, 4R, 8R,
4R, 8R, 9R,
9R, 10R, 11R
10R, 11R
5B
5B
BWa#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
4A
5A
BWb#
individual bytes to be written and must meet the setup and hold
4A
BWc#
times around the rising edge of CLK. A byte write enable is LOW
4B
BWd#
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc
pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
7A
7A
CKE#
Input
Synchronous Clock Enable: This active LOW input permits CLK to
propogate throughout the device. When CKE# is HIGH, the
device ignores the CLK input and effectively internally extends
the previous CLK cycle. This input must meet the setup and hold
times around the rising edge of CLK.
7B
7B
R/W#
Input
Read/Write: This input determines the cycle type when ADV/LD#
is LOW and is the only means for determining READs and
WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on this pin
permits BYTE WRITE operations to meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs occur if all
byte write enables are LOW.
6B
6B
CLK
Input
Clock: This signal registers the address, data, chip enable, byte
write enables, and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock's rising edge.
3A
3A
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is
sampled only when a new external address is loaded.
6A
6A
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
11H
11H
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in
the memory array is retained. When ZZ is active, all other inputs
are ignored.
3B
3B
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new external
address is loaded.
(continued on next page)
10
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
8B
8B
OE#
Input
Output Enable: This
active LOW, asynchronous input enables the
(G#)
data I/O output drivers.
8A
8A
ADV/LD#
Input
Synchronous Address Advance/Load: When HIGH, this input is used
to advance the internal burst counter, controlling burst access after
the external address is loaded. When ADV/LD# is HIGH, R/W# is
ignored. A LOW on ADV/LD# clocks a new address at the CLK rising
edge.
1R
1R
MODE
Input
Mode: This input selects the burst sequence. A LOW on this input
(LBO#)
selects "linear burst." NC or HIGH on this input selects "interleaved
burst." Do not alter input state while device is operating.
5R
5R
TMS
Input
IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels.
5P
5P
TDI
These pins may be left not connected if the JTAG
7R
7R
TCK
function is not used in the circuit.
7P
7P
TDO
Output IEEE 1149.1 Test Output: JEDEC-standard 2.5V I/O level.
(a)
10J, 10K,
(a)
10J, 10K,
DQa
Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated with
10L, 10M, 11D 10L, 10M, 11J,
Output DQa pins; Byte "b" is associated with DQb pins. For the x32 and x36
11E, 11F, 11G 11K, 11L, 11M
versions, Byte "a" is associated with DQa pins; Byte "b" is
(b)
2D, 2E, 2F,
(b)
10D, 10E,
DQb
associated with DQb pins; Byte "c" is associated with DQc pins;
2G, 1J, 1K,
10F, 10G, 11D,
Byte "d" is associated with DQd pins. Input data must meet setup
1L, 1M
11E, 11F, 11G
and hold times around the rising edge of CLK.
(c)
1D, 1E, 1F,
DQc
1G, 2D, 2E,
2F, 2G,
(d)
1J, 1K, 1L,
DQd
1M, 2J, 2K,
2L, 2M
11C
11N
NF/
DQPa
NF/
No Function/Parity Data I/Os: On the x32 version, these are no
1N
11C
NF/
DQPb
I/O
function (NF). On the x18 version, Byte "a" parity is DQPa; Byte
1C
NF/
DQPc
"b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa;
1N
NF/
DQPd
Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is
DQPd.
No function pins are internally connected to the die and have the
capacitance of an input pin. It is allowable to leave these pins
unconnected or driven by signals.
1H, 2H, 4D,
1H, 2H, 4D,
V
DD
Supply Power Supply:
See DC Electrical Characteristics and Operating
4E, 4F, 4G, 4H, 4E, 4F, 4G, 4H,
Conditions for range.
4J, 4K, 4L, 4M, 4J, 4K, 4L, 4M,
7N, 8D, 8E, 8F, 7N, 8D, 8E, 8F,
8G,8H, 8J,
8G,8H, 8J,
8K, 8L, 8M
8K, 8L, 8M
3C, 3D, 3E, 3F, 3C, 3D, 3E, 3F,
V
DD
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
3G, 3J, 3K, 3L, 3G, 3J, 3K, 3L,
and Operating Conditions for range.
3M, 3N, 9C,
3M, 3N, 9C,
9D, 9E, 9F,
9D, 9E, 9F,
9G, 9J, 9K,
9G, 9J, 9K,
9L, 9M, 9N
9L, 9M, 9N
FBGA PIN DESCRIPTIONS (continued)
(continued on next page)
11
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
4C, 4N, 5C,
4C, 4N, 5C,
V
SS
Supply Ground:
GND.
5D, 5E, 5F, 5G, 5D, 5E, 5F, 5G,
5H, 5J, 5K, 5L, 5H, 5J, 5K, 5L,
5M, 6C, 6D,
5M, 6C, 6D,
6E, 6F, 6G, 6H, 6E, 6F, 6G, 6H,
6J, 6K, 6L, 6M, 6J, 6K, 6L, 6M,
7C, 7D, 7E, 7F, 7C, 7D, 7E, 7F,
7G, 7H, 7J, 7K, 7G, 7H, 7J, 7K,
7L, 7M, 8C, 8N 7L, 7M, 8C, 8N
1A, 1B, 1C,
1A, 1B, 1P,
NC
No Connect: These signals are not internally connected and may be
1D, 1E, 1F, 1G,
2C, 2N, 2P,
connected to ground to improve package heat dissipation.
1P, 2C, 2J, 2K,
2R, 3H, 5N,
2L, 2M, 2N,
6N, 9H, 10C,
2P, 2R, 3H,
10H, 10N,
4B, 5A, 5N,
11A, 11B, 11P
6N, 9H, 10C,
10D, 10E, 10F,
10G, 10H, 10N,
11B, 11J, 11K,
11L, 11M,
11N, 11P
FBGA PIN DESCRIPTIONS (continued)
12
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
x18
x32/36
PIN LAYOUT (TOP VIEW)
119-PIN BGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
V
DD
Q
NC
NC
DQb
NC
V
DD
Q
NC
DQb
V
DD
Q
NC
DQb
V
DD
Q
DQb
NC
NC
NC
V
DD
Q
SA
CE2
SA
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQb
SA
SA
TMS
SA
SA
SA
V
SS
V
SS
V
SS
BWb#
V
SS
V
DD2
V
SS
V
SS
V
SS
V
SS
V
SS
MODE (LBO#)
SA
TDI
SA
ADV/LD#
V
DD
NC
CE#
OE# (G#)
SA
R/W#
V
DD
CLK
NC
CKE#
SA1
SA0
V
DD
NC
TCK
SA
SA
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD2
V
SS
BWa#
V
SS
V
SS
V
SS
MS#
SA
TDO
SA
CE2#
SA
DQa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
SA
SA
NC
V
DD
Q
NC
NC
NC
DQa
V
DD
Q
DQa
NC
V
DD
Q
DQa
NC
V
DD
Q
NC
DQa
NC
ZZ
V
DD
Q
TOP VIEW
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
V
DD
Q
NC
NC
DQc
DQc
V
DD
Q
DQc
DQc
V
DD
Q
DQd
DQd
V
DD
Q
DQd
DQd
NC
NC
V
DD
Q
SA
CE2
SA
NF/
DQPc
1
DQc
DQc
DQc
DQc
V
DD
DQb
DQd
DQd
DQd
NF/
DQPd
1
SA
NC
TMS
SA
SA
SA
V
SS
V
SS
V
SS
BWc#
V
SS
V
DD2
V
SS
BWd#
V
SS
V
SS
V
SS
MODE (LBO#)
SA
TDI
SA
ADV/LD#
V
DD
NC
CE#
OE# (G#)
SA
R/W#
V
DD
CLK
NC
CKE#
SA1
SA0
V
DD
SA
TCK
SA
SA
SA
V
SS
V
SS
V
SS
BWb#
V
SS
V
DD2
V
SS
BWa#
V
SS
V
SS
V
SS
MS#
SA
TDO
SA
CE2#
SA
NF/
DQPb
1
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
NF/
DQPa
1
SA
NC
NC
V
DD
Q
NC
NC
DQb
DQb
V
DD
Q
DQb
DQb
V
DD
Q
DQa
DQa
V
DD
Q
DQa
DQa
NC
ZZ
V
DD
Q
TOP VIEW
2
3
4
5
6
7
NOTE: 1. NF for x32 version, DQPx for x36 version.
2. 3J and 5J do not have to be connected directly to V
DD
if the input voltage is
V
IH
.
13
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
BGA PIN DESCRIPTIONS
x18
x32/36
SYMBOL TYPE
DESCRIPTION
4P
4P
SA0
Input
Synchronous Address Inputs: These inputs are registered
4N
4N
SA1
and must meet the setup and hold times around the rising
2A-6A, 3B, 5B,
2A-6A, 3B, 5B,
SA
edge of CLK. SA0 and SA1 are the two least significant bits
2C, 3C, 5C, 6C,
2C, 3C, 5C, 6C,
(LSB) of the address field and set the internal burst counter
4G, 2R, 6R,
4G, 2R, 6R,
if burst is desired.
2T, 3T, 5T, 6T
3T, 4T, 5T
5L
5L
BWa#
Input
Synchronous Byte Write Enables: These active LOW
3G
5G
BWb#
inputs allow individual bytes to be written when a WRITE
3G
BWc#
cycle is active and must meet the setup and hold times
3L
BWd#
around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWa# controls
DQa pins; BWb# controls DQb pins; BWc# controls DQc
pins; BWd# controls DQd pins.
4K
4K
CLK
Input
Clock: This signal registers the address, data, chip enables,
byte write enables, and burst control inputs on its rising
edge. All synchronous inputs must meet setup and hold
times around the clock's rising edge.
4E
4E
CE#
Input
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD# LOW).
2B
2B
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new external
address is loaded.
6B
6B
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new external
address is loaded.
4F
4F
OE#
Input
Output Enable: This
active LOW, asynchronous input
(G#)
enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.
4B
4B
ADV/LD# Input
Synchronous Address Advance/Load: When HIGH, this input
is used to advance the internal burst counter, controlling
burst access after the external address is loaded. When
ADV/LD# is HIGH, R/W# is ignored. A LOW on ADV/LD#
clocks a new address at the CLK rising edge.
4M
4M
CKE#
Input
Synchronous Clock Enable: This active LOW input permits
CLK to propagate throughout the device. When CKE is
HIGH, the device ignores the CLK input and effectively
internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
7T
7T
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ is
active, all other inputs are ignored.
(continued on next page)
14
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
BGA PIN DESCRIPTIONS (continued)
x18
x32/36
SYMBOL TYPE
DESCRIPTION
4H
4H
R/W#
Input
Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted into
WRITEs (and vice versa) other than by loading a new
address. A LOW on this pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising
edge of CLK. Full bus-width WRITEs occur if all byte write
enables are LOW.
3R
3R
MODE
Input
Mode: This input selects the burst sequence. A LOW on
(LBO#)
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
2U
2U
TMS
Input
IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels.
3U
3U
TDI
These pins may be left Not Connected if the JTAG
4U
4U
TCK
function is not used in the circuit.
(a)
7E, 6F, 7G, 6H,
(a)
6K-6N, 7K, 7L,
DQa
Input/
SRAM Data I/Os: Byte "a" is associated with DQa pins; Byte
6D, 7K, 6L, 6N, 7P
7N, 7P
Output
"b" is associated with DQb pins; Byte "c" is associated with
(b)
1D, 2E, 2G, 1H,
(b)
6E-6H, 7D, 7E,
DQb
DQc pins; Byte "d" is associated with DQd pins. Input data
2K, 1L, 2M, 1N, 2P
7G, 7H
must meet setup and hold times around the rising edge
(c)
1D, 1E, 1G, 1H,
DQc
CLK.
2E-2H
(d)
1K, 1L, 1N, 1P,
DQd
2K-2N
5U
5U
TDO
Output
IEEE 1149.1 Test Output: JEDEC-standard 2.5V I/O level.
6P
NF/
DQPa
NF/
No Function/Data Bits: On the x32 version, these pins are
6D
NF/
DQPb
I/O
no function (NC) and can be left floating or connected to
2D
NF/
DQPc
GND to minimize thermal impedance. On the x36 version,
2P
NF/
DQPd
these bits are DQs.
No function pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to
leave these pins unconnected or driven by signals.
4C, 2J-6J
4C, 2J-6J
V
DD
Supply
Power Supply:
See DC Electrical Characteristics and
Operating Conditions for range.
1A, 1F, 1J, 1M, 1U, 1A, 1F, 1J, 1M, 1U,
V
DD
Q
Supply
Isolated Output Buffer Supply:
See DC Electrical
7A, 7F, 7J, 7M, 7U
7A, 7F, 7J, 7M, 7U
Characteristics and Operating Conditions for range.
3D, 3E, 3F, 3H,
3D, 3E, 3F, 3H, 3K,
V
SS
Supply
Ground:
GND.
3K-3P, 5D-5H, 5K, 3M, 3N, 3P, 5D-5F,
5M-5P
5H, 5K, 5M-5P
1B, 1C, 1E, 1G, 1K,
1B, 1C, 1R, 1T, 2T,
NC
No Connect: These pins can be left floating or connected
1P, 1R, 1T, 2D, 2F,
4D, 4L, 6T, 6U,
to GND to minimize thermal impedance.
2H, 2L, 2N, 4D, 4L,
7B, 7C, 7R
4T, 6E, 6G, 6K, 6M,
6P, 6U, 7B-7D, 7H,
7L, 7R, 7N
15
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
FUNCTION
R/W#
BWa#
BWb#
BWc#
BWd#
READ
H
X
X
X
X
WRITE Byte "a"
L
L
H
H
H
WRITE Byte "b"
L
H
L
H
H
WRITE Byte "c"
L
H
H
L
H
WRITE Byte "d"
L
H
H
H
L
WRITE All Bytes
L
L
L
L
L
WRITE ABORT/NOP
L
H
H
H
H
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)
NOTE: Using R/W# and byte write(s), any one or more bytes may be written.
FUNCTION
R/W#
BWa#
BWb#
READ
H
X
X
WRITE Byte "a"
L
L
H
WRITE Byte "b"
L
H
L
WRITE All Bytes
L
L
L
WRITE ABORT/NOP
L
H
H
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)
NOTE: Using R/W# and byte write(s), any one or more bytes may be
written.
16
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
STATE DIAGRAM FOR ZBT SRAM
NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the
clock (CLK) input and does not change the state of the device.
2. States change on the rising edge of the clock (CLK).
DESELECT
BEGIN
READ
BURST
READ
BEGIN
WRITE
DS
DS
DS
BURST
WRITE
READ
DS
WRITE
WRITE
BURST
READ
WRITE
READ
BURST
BURST
READ
BURST
DS
WRITE
KEY:
COMMAND
DS
READ
WRITE
BURST
OPERATION
DESELECT
New READ
New WRITE
BURST READ,
BURST WRITE or
CONTINUE DESELECT
BURST
READ
WRITE
17
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
TRUTH TABLE
(Notes 5-10)
ADDRESS
ADV/
OPERATION
USED
CE# CE2# CE2 ZZ
LD#
R/W# BWx OE# CKE#
CLK
DQ
NOTES
DESELECT Cycle
None
H
X
X
L
L
X
X
X
L
L
H High-Z
DESELECT Cycle
None
X
H
X
L
L
X
X
X
L
L
H High-Z
DESELECT Cycle
None
X
X
L
L
L
X
X
X
L
L
H High-Z
CONTINUE DESELECT Cycle
None
X
X
X
L
H
X
X
X
L
L
H High-Z
1
READ Cycle
External
L
L
H
L
L
H
X
L
L
L
H
Q
(Begin Burst)
READ Cycle
Next
X
X
X
L
H
X
X
L
L
L
H
Q
1, 11
(Continue Burst)
NOP/DUMMY READ
External
L
L
H
L
L
H
X
H
L
L
H High-Z
2
(Begin Burst)
DUMMY READ
Next
X
X
X
L
H
X
X
H
L
L
H High-Z 1, 2,
(Continue Burst)
11
WRITE Cycle
External
L
L
H
L
L
L
L
X
L
L
H
D
3
(Begin Burst)
WRITE Cycle
Next
X
X
X
L
H
X
L
X
L
L
H
D
1, 3,
(Continue Burst)
11
NOP/WRITE ABORT
None
L
L
H
L
L
L
H
X
L
L
H High-Z
2, 3
(Begin Burst)
WRITE ABORT
Next
X
X
X
L
H
X
H
X
L
L
H High-Z 1, 2,
(Continue Burst)
3, 11
IGNORE CLOCK EDGE
Current
X
X
X
L
X
X
X
X
H
L
H
4
(Stall)
SNOOZE MODE
None
X
X
X
H
X
X
X
X
X
X
High-Z
NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle
is executed first.
2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.
A WRITE ABORT means a WRITE command is given, but no operation is performed.
3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off
the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet an
application's requirements.
4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it
occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE
CLOCK EDGE cycle.
5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,
BWc#, and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.
6. BWa# enables WRITEs to Byte "a" (DQa pins); BWb# enables WRITEs to Byte "b" (DQb pins); BWc# enables WRITEs to
Byte "c" (DQc pins); BWd# enables WRITEs to Byte "d" (DQd pins).
7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.
18
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
3.3V V
DD
, ABSOLUTE MAXIMUM
RATINGS*
Voltage on V
DD
Supply Relative
to V
SS
........................................................ -0.5V to +4.6V
Voltage on V
DD
Q Supply Relative
to V
SS
........................................................... -0.5V to V
DD
V
IN
(Inputs) .......................................... -0.5V to V
DD
+ 0.5V
V
IN
(DQs) .......................................... -0.5V to V
DD
Q + 0.5V
Storage Temperature (TQFP) ................ -55C to +150C
Storage Temperature (FBGA) ................ -55C to +125C
Junction Temperature** ........................................ +150C
Short Circuit Output Current ................................ 100mA
2.5V V
DD
, ABSOLUTE MAXIMUM
RATINGS*
Voltage on V
DD
Supply Relative
to V
SS
........................................................ -0.3V to +3.6V
Voltage on V
DD
Q Supply Relative
to V
SS
........................................................ -0.3V to +3.6V
V
IN
(Inputs) .......................................... -0.5V to V
DD
+ 0.5V
V
IN
(DQs) .......................................... -0.5V to V
DD
Q + 0.5V
Storage Temperature (plastic) ............... -55C to +150C
Storage Temperature (FBGA) ................ -55C to +125C
Junction Temperature** ........................................ +150C
Short Circuit Output Current ................................ 100mA
*Stresses greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only, and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
**Junction temperature depends upon package type, cycle
time, loading, ambient temperature, and airflow. See
Micron Technical Note TN-05-14 for more information.
3.3V V
DD
, 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C
T
A
+70C; V
DD
= +3.3V 0.165V, V
DD
Q = +3.3V 0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
2.0
V
DD
+ 0.3
V
1, 2
Input High (Logic 1) Voltage
DQ pins
V
IH
2.0
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.8
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-1.0
1.0
A
3, 6
Output Leakage Current
Output(s) disabled,
IL
O
-1.0
1.0
A
0V
V
IN
V
DD
Output High Voltage
I
OH
= -4.0mA
V
OH
2.4
V
1, 4
Output Low Voltage
I
OL
= 8.0mA
V
OL
0.4
V
1, 4
Supply Voltage
V
DD
3.135
3.465
V
1
Isolated Output Buffer Supply
V
DD
Q
3.135
V
DD
V
1, 5
NOTE: 1. All voltages referenced to V
SS
(GND).
2. For 3.3V V
DD
:
Overshoot:
V
IH
+4.6V for t
t
KHKH/2 for I
20mA
Undershoot: V
IL
-0.7V for t
t
KHKH/2 for I
20mA
Power-up:
V
IH
+3.6V and V
DD
3.135V for t 200ms
For 2.5V V
DD
:
Overshoot:
V
IH
+3.6V for t
t
KHKH/2 for I
20mA
Undershoot: V
IL
-0.5V for t
t
KHKH/2 for I
20mA
Power-up:
V
IH
+2.65V and V
DD
2.375V for t 200ms
3. MODE pin has an internal pull-up, and input leakage = 10A.
4. The load used for V
OH
, V
OL
testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O
curves are available upon request.
5. V
DD
Q should never exceed V
DD
. V
DD
and V
DD
Q can be externally wired together to the same power supply.
6. Ms# pin has an internal pull-down , and input leakage = 10A.
19
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
3.3V V
DD
, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C
T
A
+70C; V
DD
= +3.3V 0.165V; V
DD
Q = 0.125V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
Data bus (DQx)
V
IH
Q
1.7
V
DD
Q + 0.3
V
1, 2
Inputs
V
IH
1.7
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.7
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-1.0
1.0
A
3
Output Leakage Current
Output(s) disabled,
IL
O
-1.0
1.0
A
0V
V
IN
V
DD
Q (DQx)
Output High Voltage
I
OH
= -2.0mA
V
OH
1.7
V
1
I
OH
= -1.0mA
V
OH
2.0
V
1
Output Low Voltage
I
OL
= 2.0mA
V
OL
0.7
V
1
I
OL
= 1.0mA
V
OL
0.4
V
1
Supply Voltage
V
DD
3.135
3.465
V
1
Isolated Output Buffer Supply
V
DD
Q
2.375
2.625
V
1
2.5V V
DD
, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C
T
A
+70C; V
DD
= +3.3V 0.165V; V
DD
Q = +2.5V 0.125V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
Data bus (DQx)
V
IH
Q
1.7
V
DD
Q + 0.3
V
1, 2
Inputs
V
IH
1.7
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.7
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-1.0
1.0
A
3
Output Leakage Current
Output(s) disabled,
IL
O
-1.0
1.0
A
0V
V
IN
V
DD
Q (DQx)
Output High Voltage
I
OH
= -2.0mA
V
OH
1.7
V
1
I
OH
= -1.0mA
V
OH
2.0
V
1
Output Low Voltage
I
OL
= 2.0mA
V
OL
0.7
V
1
I
OL
= 1.0mA
V
OL
0.4
V
1
Supply Voltage
V
DD
2.375
2.625
V
1
Isolated Output Buffer Supply
V
DD
Q
2.375
2.625
V
1
NOTE: 1. All voltages referenced to V
SS
(GND).
2. For 3.3V V
DD
:
Overshoot:
V
IH
+4.6V for t
t
KHKH/2 for I
20mA
Undershoot: V
IL
-0.7V for t
t
KHKH/2 for I
20mA
Power-up:
V
IH
+3.6V and V
DD
3.135V for t 200ms
For 2.5V V
DD
:
Overshoot:
V
IH
+3.6V for t
t
KHKH/2 for I
20mA
Undershoot: V
IL
-0.5V for t
t
KHKH/2 for I
20mA
Power-up:
V
IH
+2.65V and V
DD
2.375V for t 200ms
3. MODE pin has an internal pull-up, and input leakage = 10A.
20
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
NOTE: 1. This parameter is sampled.
TQFP CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Control Input Capacitance
T
A
= 25C; f = 1 MHz
C
I
3
4
pF
1
Input/Output Capacitance (DQ)
V
DD
= 3.3V
C
O
4
5
pF
1
Address Capacitance
C
A
3
3.5
pF
1
Clock Capacitance
C
CK
3
3.5
pF
1
FBGA CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Address/Control Input Capacitance
C
I
2.5
3.5
pF
1
Output Capacitance (Q)
T
A
= 25C; f = 1 MHz
C
O
4
5
pF
1
Clock Capacitance
C
CK
2.5
3.5
pF
1
BGA CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Control Input Capacitance
T
A
= 25C; f = 1 MHz
C
I
4
7
pF
1
Input/Output Capacitance (DQ)
V
DD
= 3.3V
C
O
4.5
5.5
pF
1
Address Capacitance
C
A
4
7
pF
1
Clock Capacitance
C
CK
4.5
5.5
pF
1
21
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS
NOTES
Thermal Resistance
Test conditions follow standard test methods
JA
46
C/W
1
(Junction to Ambient)
and procedures for measuring thermal
Thermal Resistance
impedance, per EIA/JESD51.
JC
2.8
C/W
1
(Junction to Top of Case)
NOTE: 1. This parameter is sampled.
FBGA THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Junction to Ambient
Test conditions follow standard test methods
JA
40
C/W
1
(Airflow of 1m/s)
and procedures for measuring thermal
Junction to Case (Top)
impedance, per EIA/JESD51.
JC
9
C/W
1
Junction to Pins
JB
17
C/W
1
(Bottom)
BGA THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS
NOTES
Thermal Resistance
Test conditions follow standard test methods
JA
40
C/W
1
(Junction to Ambient)
and procedures for measuring thermal
Thermal Resistance
impedance, per EIA/JESD51.
JC
9
C/W
1
(Junction to Top of Case)
Thermal Resistance
JC
17
C/W
1
(Junction to Pins)
22
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
3.3V V
DD
, I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS (512K x 32/36)
(Note 1) (0C
T
A
+70C)
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-7.5
-10
UNITS NOTES
Power Supply
Device selected; All inputs
V
IL
Current:
or
V
IH
; Cycle time
t
KC (MIN);
I
DD
TBD
675
525
mA
2, 3, 4
Operating
V
DD
= MAX; Outputs open
Power Supply
Device selected; V
DD
= MAX;
Current: Idle
CKE#
V
IH
;
I
DD
1
TBD
225
175
mA
2, 3, 4
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC (MIN)
CMOS Standby
Device deselected; V
DD
= MAX;
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
I
SB
2
TBD
30
30
mA
3, 4
All inputs static; CLK frequency = 0
TTL Standby
Device deselected; V
DD
= MAX;
All inputs
V
IL
or
V
IH
;
I
SB
3
TBD
100
100
mA
3, 4
All inputs static; CLK frequency = 0
Clock Running
Device deselected; V
DD
= MAX;
ADV/LD#
V
IH
; All inputs
V
SS
+ 0.2
I
SB
4
TBD
225
175
mA
3, 4
or
V
DD
- 0.2; Cycle time
t
KC (MIN)
Snooze Mode
ZZ
V
IH
I
SB
2Z
TBD
10
10
mA
4
MAX
NOTE: 1. V
DD
Q = +3.3V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of V
DD
and V
DD
Q.
2. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times and
greater output loading.
3. "Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device
is active (not in deselected mode).
4. Typical values are measured at 3.3V, 25C and 10ns cycle time.
23
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
2.5V V
DD
, I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS (512K x 32/36)
(Note 1) (0C
T
A
+70C)
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-6
-7.5
-10
UNITS NOTES
Power Supply
Device selected; All inputs
V
IL
Current:
or
V
IH
; Cycle time
t
KC (MIN);
I
DD
TBD
625
515
400
mA
2, 3, 4
Operating
V
DD
= MAX; Outputs open
Power Supply
Device selected; V
DD
= MAX;
Current: Idle
CKE#
V
IH
;
I
DD
1
TBD
210
175
135
mA
2, 3, 4
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC (MIN)
CMOS Standby
Device deselected; V
DD
= MAX;
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
I
SB
2
TBD
25
25
25
mA
3, 4
All inputs static; CLK frequency = 0
TTL Standby
Device deselected; V
DD
= MAX;
All inputs
V
IL
or
V
IH
;
I
SB
3
TBD
80
80
80
mA
3, 4
All inputs static; CLK frequency = 0
Clock Running
Device deselected; V
DD
= MAX;
ADV/LD#
V
IH
; All inputs
V
SS
+ 0.2
I
SB
4
TBD
210
175
135
mA
3, 4
or
V
DD
- 0.2; Cycle time
t
KC (MIN)
Snooze Mode
ZZ
V
IH
I
SB
2Z
TBD
10
10
10
mA
4
MAX
NOTE: 1. V
DD
Q = +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of V
DD
and V
DD
Q.
2. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times and
greater output loading.
3. "Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device
is active (not in deselected mode).
4. Typical values are measured at2.5V, 25C and 10ns cycle time.
24
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
MAX
3.3V V
DD
, I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS (1 MEG x 18)
(Note 1) (0C
T
A
+70C)
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-7.5
-10
UNITS NOTES
Power Supply
Device selected; All inputs
V
IL
Current:
or
V
IH
; Cycle time
t
KC (MIN);
I
DD
TBD
510
395
mA
2, 3, 4
Operating
V
DD
= MAX; Outputs open
Power Supply
Device selected; V
DD
= MAX;
Current: Idle
CKE#
V
IH
;
I
DD
1
TBD
170
135
mA
2, 3, 4
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC (MIN)
CMOS Standby
Device deselected; V
DD
= MAX;
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
I
SB
2
TBD
25
25
mA
3, 4
All inputs static; CLK frequency = 0
TTL Standby
Device deselected; V
DD
= MAX;
All inputs
V
IL
or
V
IH
;
I
SB
3
TBD
75
75
mA
3, 4
All inputs static; CLK frequency = 0
Clock Running
Device deselected; V
DD
= MAX;
ADV/LD#
V
IH
; All inputs
V
SS
+ 0.2
I
SB
4
TBD
170
135
mA
3, 4
or
V
DD
- 0.2; Cycle time
t
KC (MIN)
Snooze Mode
ZZ
V
IH
I
SB
2Z
TBD
10
10
mA
4
NOTE: 1. V
DD
Q = +3.3V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of V
DD
and V
DD
Q.
2. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times and
greater output loading.
3. "Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device
is active (not in deselected mode).
4. Typical values are measured at 3.3V, 25C and 10ns cycle time.
25
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
2.5V V
DD
, I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS (1 MEG x 18)
(Note 1) (0C
T
A
+70C)
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-6
-7.5
-10
UNITS NOTES
Power Supply
Device selected; All inputs
V
IL
Current:
or
V
IH
; Cycle time
t
KC (MIN);
I
DD
TBD
470
390
305
mA
2, 3, 4
Operating
V
DD
= MAX; Outputs open
Power Supply
Device selected; V
DD
= MAX;
Current: Idle
CKE#
V
IH
;
I
DD
1
TBD
160
130
110
mA
2, 3, 4
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC (MIN)
CMOS Standby
Device deselected; V
DD
= MAX;
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
I
SB
2
TBD
20
20
20
mA
3, 4
All inputs static; CLK frequency = 0
TTL Standby
Device deselected; V
DD
= MAX;
All inputs
V
IL
or
V
IH
;
I
SB
3
TBD
60
60
60
mA
3, 4
All inputs static; CLK frequency = 0
Clock Running
Device deselected; V
DD
= MAX;
ADV/LD#
V
IH
; All inputs
V
SS
+ 0.2
I
SB
4
TBD
160
130
110
mA
3, 4
or
V
DD
- 0.2; Cycle time
t
KC (MIN)
Snooze Mode
ZZ
V
IH
I
SB
2Z
TBD
10
10
10
mA
4
MAX
NOTE: 1. V
DD
Q = +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of V
DD
and V
DD
Q.
2. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times and
greater output loading.
3. "Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device
is active (not in deselected mode).
4. Typical values are measured at2.5V, 25C and 10ns cycle time.
26
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
NOTE: 1. OE# can be considered a "Don't Care" during WRITEs; however, controlling OE# can help fine-tune a system for
turnaround timing.
2. Test conditions as specified with output loading as shown in Figure 1 for 3.3V I/O (V
DD
Q = +3.3V 0.165V) and
Figure 3 for 2.5V I/O (V
DD
Q = +2.5V +0.4V/-0.125V).
3. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
4. If V
DD
= +3.3V, then V
DD
Q = +3.3V or +2.5V. If V
DD
= +2.5V, then V
DD
Q = +2.5V.
Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of V
DD
and V
DD
Q.
5. The -6 speed grade is available in the 2.5V V
DD
and I/O only.
6. Measured as HIGH above V
IH
and LOW below V
IL
.
7. Refer to Technical Note TN-55-01, "Designing with ZBT SRAMs," for a more thorough discussion of these parameters.
8. This parameter is sampled.
9. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
10. Transition is measured 200mV from steady state voltage.
11. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times
with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK when ADV/LD# is LOW to remain enabled.
AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2, 3, 4) (0C
T
A
+70C)
-6
5
-7.5
-10
DESCRIPTION
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
Clock
Clock cycle time
t
KHKH
6.0
7.5
10
ns
Clock frequency
f
KF
166
133
100
MHz
Clock HIGH time
t
KHKL
1.8
2.2
3.2
ns
6
Clock LOW time
t
KLKH
1.8
2.2
3.2
ns
6
Output Times
Clock to output valid
t
KHQV
3.5
4.2
5.0
ns
Clock to output invalid
t
KHQX
1.5
1.5
1.5
ns
7
Clock to output in Low-Z
t
KHQX1
1.5
1.5
1.5
ns
7, 8, 9, 10
Clock to output in High-Z
t
KHQZ
1.5
3.0
1.5
3.0
1.5
3.3
ns
7, 8, 9, 10
OE# to output valid
t
GLQV
3.5
4.2
5.0
ns
1
OE# to output in Low-Z
t
GLQX
0
0
0
ns
7, 8, 9, 10
OE# to output in High-Z
t
GHQZ
3.5
4.2
5.0
ns
7, 8, 9, 10
Setup Times
Address
t
AVKH
1.5
1.7
2.0
ns
11
Clock enable (CKE#)
t
EVKH
1.5
1.7
2.0
ns
11
Control signals
t
CVKH
1.5
1.7
2.0
ns
11
Data-in
t
DVKH
1.5
1.7
2.0
ns
11
Hold Times
Address
t
KHAX
0.5
0.5
0.5
ns
11
Clock enable (CKE#)
t
KHEX
0.5
0.5
0.5
ns
11
Control signals
t
KHCX
0.5
0.5
0.5
ns
11
Data-in
t
KHDX
0.5
0.5
0.5
ns
11
27
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Q
50
V = 1.5V
Z = 50
O
T
Figure 1
Q
351
317
5pF
+3.3V
Figure 2
3.3V V
DD
, 3.3V I/O AC TEST CONDITIONS
Input pulse levels ................. V
IH
= (V
DD
/2.2) + 1.5V
.................... V
IL
= (V
DD
/2.2) - 1.5V
Input rise and fall times ..................................... 1ns
Input timing reference levels ..................... V
DD
/2.2
Output reference levels ............................ V
DD
Q/2.2
Output load ............................. See Figures 1 and 2
LOAD DERATING CURVES
Micron 1 Meg x 18, 512K x 32, and 512K x 36 ZBT SRAM
timing is dependent upon the capacitive loading on the
outputs.
Consult the factory for copies of I/O current versus
voltage curves.
Q
50
V = 1.25V
Z = 50
O
T
Figure 3
Q
225
225
5pF
+2.5V
Figure 4
3.3V V
DD
, 2.5V I/O AC TEST CONDITIONS
Input pulse levels ............. V
IH
= (V
DD
/2.64) + 1.25V
................ V
IL
= (V
DD
/2.64) - 1.25V
Input rise and fall times ..................................... 1ns
Input timing reference levels ................... V
DD
/2.64
Output reference levels ............................... V
DD
Q/2
Output load ............................. See Figures 3 and 4
3.3V I/O Output Load Equivalents
2.5V I/O Output Load Equivalents
2.5V V
DD
, 2.5V I/O AC TEST CONDITIONS
Input pulse levels .................. V
IH
= (V
DD
/2) + 1.25V
..................... V
IL
= (V
DD
/2) - 1.25V
Input rise and fall times ..................................... 1ns
Input timing reference levels ........................ V
DD
/2
Output reference levels ............................... V
DD
Q/2
Output load ............................. See Figures 3 and 4
28
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, "power-down" mode
in which the device is deselected and current is reduced
to I
SB
2Z
. The duration of SNOOZE MODE is dictated by
the length of time the ZZ pin is in a HIGH state. After the
device enters SNOOZE MODE, all inputs except ZZ be-
come disabled and all outputs go to High-Z.
The ZZ pin is an asynchronous, active HIGH input
that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic HIGH, I
SB
2Z
is guaran-
teed after the time
t
ZZI is met. Any READ or WRITE
operation pending when the device enters SNOOZE
MODE is not guaranteed to complete successfully. There-
fore, SNOOZE MODE must not be initiated until valid
pending operations are completed. Similarly, when exit-
ing SNOOZE MODE during
t
RZZ, only a DESELECT or
READ cycle should be given.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Current during SNOOZE MODE
ZZ
V
IH
I
SB
2Z
10
mA
ZZ active to input ignored
t
ZZ
0
2(
t
KHKH)
ns
1
ZZ inactive to input sampled
t
RZZ
0
2(
t
KHKH)
ns
1
ZZ active to snooze current
t
ZZI
2(
t
KHKH)
ns
1
ZZ inactive to exit snooze current
t
RZZI
0
ns
1
SNOOZE MODE WAVEFORM
t
ZZ
I
SUPPLY
CLK
ZZ
t
RZZ
ALL INPUTS
(except ZZ)
DON'T CARE
I
ISB2Z
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
NOTE: 1. This parameter is sampled.
29
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
READ/WRITE TIMING
WRITE
D(A1)
1
2
3
4
5
6
7
8
9
CLK
t KHKH
t
KLKH
t
KHKL
10
CE#
t
KHCX
t
CVKH
R/W#
CKE#
t
KHEX
t
EVKH
BWx#
ADV/LD#
t
KHAX
t
AVKH
ADDRESS
A1
A2
A3
A4
A5
A6
A7
t
KHDX
t
DVKH
DQ
COMMAND
t
KHQX1
D(A1)
D(A2)
D(A5)
Q(A4)
Q(A3)
D(A2+1)
t
KHQX
t
KHQZ
t
KHQV
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE#
t
GLQV
t
GLQX
t
GHQZ
t
KHQX
DON'T CARE
UNDEFINED
Q(A6)
Q(A4+1)
NOTE: 1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
-6*
-7.5
-10
SYMBOL
MIN MAX
MIN MAX
MIN MAX UNITS
t
GHQZ
3.5
4.2
5.0
ns
t
AVKH
1.5
1.7
2.0
ns
t
EVKH
1.5
1.7
2.0
ns
t
CVKH
1.5
1.7
2.0
ns
t
DVKH
1.5
1.7
2.0
ns
t
KHAX
0.5
0.5
0.5
ns
t
KHEX
0.5
0.5
0.5
ns
t
KHCX
0.5
0.5
0.5
ns
t
KHDX
0.5
0.5
0.5
ns
READ/WRITE TIMING PARAMETERS
-6*
-7.5
-10
SYMBOL
MIN MAX
MIN MAX
MIN MAX UNITS
t
KHKH
6.0
7.5
10
ns
f
KF
166
133
100
MHz
t
KHKL
1.7
2.0
3.2
ns
t
KLKH
1.7
2.0
3.2
ns
t
KHQV
3.5
4.2
5.0
ns
t
KHQX
1.5
1.5
1.5
ns
t
KHQX1
1.5
1.5
1.5
ns
t
KHQZ
1.5
3.5
1.5
3.5
1.5
3.5
ns
t
GLQV
3.5
4.2
5.0
ns
t
GLQX
0
0
0
ns
*The -6 speed grade available in 2.5V V
DD
and I/O only.
30
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
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MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
NOP, STALL, AND DESELECT CYCLES
READ
Q(A3)
4
5
6
7
8
9
10
CLK
CE#
R/W#
CKE#
BWx#
ADV/LD#
ADDRESS
A3
A4
A5
D(A4)
DQ
COMMAND
A1
Q(A5)
WRITE
D(A4)
STALL
WRITE
D(A1)
1
2
3
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON'T CARE
UNDEFINED
t
KHQZ
t
KHQX
A2
D(A1)
Q(A2)
Q(A3)
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a "pause." A WRITE is not
performed during this cycle.
2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
NOP, STALL, AND DESELECT TIMING PARAMETERS
-6*
-7.5
-10
SYMBOL
MIN MAX
MIN MAX
MIN MAX UNITS
t
KHQX
1.5
1.5
1.5
ns
t
KHQZ
1.5
3.5
1.5
3.5
1.5
3.5
ns
*The -6 speed grade available in 2.5V V
DD
and I/O only.
31
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
IEEE 1149.1 SERIAL BOUNDARY SCAN
(JTAG)
The 18Mb SRAM incorporates a serial boundary scan
test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set
of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded be-
cause their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the
operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 2.5V I/O
logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID
register.
DISABLING THE JTAG FEATURE
These pins can be left floating (unconnected), if the
JTAG function is not to be implemented. Upon power-
up, the device will come up in a reset state which will not
interfere with the operation of the device.
TEST ACCESS PORT (TAP)
TEST CLOCK (TCK)
The test clock is used only with the TAP controller. All
inputs are captured on the rising edge of TCK. All outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It is
allowable to leave this pin unconnected if the TAP is not
used. The pin is pulled up internally, resulting in a logic
HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information into
the registers and can be connected to the input of any of
the registers. The register between TDI and TDO is cho-
sen by the instruction that is loaded into the TAP instruc-
tion register. For information on loading the instruction
register, see Figure 5. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application.
TDI is connected to the most significant bit (MSB) of any
register. (See Figure 6.)
Figure 5
TAP Controller State Diagram
NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
32
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
TEST DATA-OUT (TDO)
The TDO output pin is used to serially clock data-out
from the registers. The output is active depending upon
the current state of the TAP state machine. (See Figure 5.)
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
(See Figure 6.)
PERFORMING A TAP RESET
A RESET is performed by forcing TMS HIGH (V
DD
) for
five rising edges of TCK. This RESET does not affect the
operation of the SRAM and may be performed while the
SRAM is operating.
At power-up, the TAP is reset internally to ensure that
TDO comes up in a High-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO
pins and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected at
a time through the instruction register. Data is serially
loaded into the TDI pin on the rising edge of TCK. Data is
output on the TDO pin on the falling edge of TCK.
INSTRUCTION REGISTER
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in Figure
5. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Bypass Register
0
Instruction Register
0
1
2
Identification Register
0
1
2
29
30
31
.
.
.
Boundary Scan Register*
0
1
2
.
.
x
.
.
.
Selection
Circuitry
Selection
Circuitry
TCK
TMS
TAP CONTROLLER
TDI
TDO
*x = 52 for the x18 configuration, x = 67 for the x32 configuration,
x = 71 for the x36 configuration.
Figure 6
TAP Controller Block Diagram
When the TAP controller is in the Capture-IR state, the
two least significant bits are loaded with a binary "01"
pattern to allow for fault isolation of the board-level
serial test data path.
BYPASS REGISTER
To save time when serially shifting data through reg-
isters, it is sometimes advantageous to skip certain chips.
The bypass register is a single-bit register that can be
placed between the TDI and TDO pins. This allows data
to be shifted through the SRAM with minimal delay. The
bypass register is set LOW (V
SS
) when the BYPASS in-
struction is executed.
BOUNDARY SCAN REGISTER
The boundary scan register is connected to all the
input and bidirectional pins on the SRAM. The x36 con-
figuration has a 71-bit-long register, the x32 configura-
tion has a 67-bit-long register, and the x18 configuration
has a 52-bit-long register.
The boundary scan register is loaded with the con-
tents of the RAM I/O ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI
and TDO pins when the controller is moved to the Shift-
DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE
Z instructions can be used to capture the contents of the
I/O ring.
The Boundary Scan Order tables show the order in
which the bits are connected. Each bit corresponds to
one of the pins on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected to
TDO.
33
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
TDO pins and allows the IDCODE to be shifted out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction
register upon power-up or whenever the TAP controller
is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bidirectional pins is captured in the boundary scan
register.
The user must be aware that the TAP controller clock
can only operate at a frequency up to 10 MHz, while the
SRAM clock operates more than an order of magnitude
faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR
state, an input or output will undergo a transition. The
TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP
controller's capture setup plus hold time (
t
CS plus
t
CH).
The SRAM clock input might not be captured correctly if
there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the
data by putting the TAP into the Shift-DR state. This
places the boundary scan register between the TDI and
TDO pins.
Note that since the PRELOAD part of the command is
not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
IDENTIFICATION (ID) REGISTER
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE
command is loaded in the instruction register. The
IDCODE is hardwired into the SRAM and can be shifted
out when the TAP controller is in the Shift-DR state. The
ID register has a vendor code and other information
described in the Identification Register Definitions table.
TAP INSTRUCTION SET
OVERVIEW
Eight different instructions are possible with the three-
bit instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are
listed as RESERVED and should not be used. The other
five instructions are described in detail below.
The TAP controller used in this SRAM is not fully
compliant to the 1149.1 convention because some of the
mandatory 1149.1 instructions are not fully implemented.
The TAP controller cannot be used to load address, data
or control signals into the SRAM and cannot preload the
I/O buffers. The SRAM does not implement the 1149.1
commands EXTEST or INTEST or the PRELOAD portion
of SAMPLE/PRELOAD; rather, it performs a capture of
the I/O ring when these instructions are executed.
Instructions are loaded into the TAP controller during
the Shift-IR state when the instruction register is placed
between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI
and TDO pins. To execute the instruction once it is shifted
in, the TAP controller needs to be moved into the Update-
IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to
be executed whenever the instruction register is loaded
with all 0s. EXTEST is not implemented in this SRAM TAP
controller, and therefore this device is not compliant to
1149.1.
The TAP controller does recognize an all-0 instruc-
tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a SAMPLE/
PRELOAD instruction has been loaded. There is one dif-
ference between the two instructions. Unlike the
SAMPLE/PRELOAD instruction, EXTEST places the SRAM
outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI and
34
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
t
TLTH
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTHTL
Test Data-Out
(TDO)
tTHTH
Test Data-In
(TDI)
tTHMX
tMVTH
tTHDX
tDVTH
tTLOX
tTLOV
DON'T CARE
UNDEFINED
TAP TIMING
TAP AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2) (+20C
T
J
+100C; +2.4V V
DD
+2.6V)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Clock
Clock cycle time
t
THTH
100
ns
Clock frequency
f
TF
10
MHz
Clock HIGH time
t
THTL
40
ns
Clock LOW time
t
TLTH
40
ns
Output Times
TCK LOW to TDO unknown
t
TLOX
0
ns
TCK LOW to TDO valid
t
TLOV
20
ns
TDI valid to TCK HIGH
t
DVTH
10
ns
TCK HIGH to TDI invalid
t
THDX
10
ns
Setup Times
TMS setup
t
MVTH
10
ns
Capture setup
t
CS
10
ns
Hold Times
TMS hold
t
THMX
10
ns
Capture hold
t
CH
10
ns
NOTE: 1.
t
CS and
t
CH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in Figure 7.
BYPASS
When the BYPASS instruction is loaded in the instruc-
tion register and the TAP is placed in a Shift-DR state, the
bypass register is placed between TDI and TDO. The
advantage of the BYPASS instruction is that it shortens
the boundary scan path when multiple devices are con-
nected together on a board.
RESERVED
These instruction are not implemented but are re-
served for future use. Do not use these instructions.
35
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
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MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
TAP AC TEST CONDITIONS
Input pulse levels ...................................... V
SS
to 2.5V
Input rise and fall times ....................................... 1ns
Input timing reference levels ........................... 1.25V
Output reference levels .................................... 1.25V
Test load termination supply voltage .............. 1.25V
TDO
1.25V
20pF
Z = 50
O
50
Figure 7
TAP AC Output Load Equivalent
3.3V V
DD
TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(+20C
T
J
+110C; +3.135V V
DD
+3.465V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
2.0
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.8
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-5.0
5.0
A
Output Leakage Current
Output(s) disabled,
IL
O
-5.0
5.0
A
0V
V
IN
V
DD
Q (DQx)
Output Low Voltage
I
OLC
= 100A
V
OL
1
0.7
V
1
Output Low Voltage
I
OLT
= 2mA
V
OL
2
0.8
V
1
Output High Voltage
I
OHC
= 100A
V
OH
1
2.9
V
1
Output High Voltage
I
OHT
= 2mA
V
OH
2
2.0
V
1
NOTE: 1. All voltages referenced to V
SS
(GND).
2. Overshoot:
V
IH
(AC)
V
DD
+ 1.5V for t
t
KHKH/2
Undershoot:
V
IL
(AC)
-0.5V for t
t
KHKH/2
Power-up:
V
IH
+2.6V and V
DD
2.4V and V
DD
Q
1.4V for t 200ms
During normal operation, V
DD
Q must not exceed V
DD
. Control input signals (such as LD#, R/W#, etc.) may not have
pulse widths less than
t
KHKL (MIN) or operate at frequencies exceeding
f
KF (MAX).
2.5V V
DD
TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(+20C
T
J
+110C; +2.4V V
DD
+2.6V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
1.7
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.7
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-5.0
5.0
A
Output Leakage Current
Output(s) disabled,
IL
O
-5.0
5.0
A
0V
V
IN
V
DD
Q (DQx)
Output Low Voltage
I
OLC
= 100A
V
OL
1
0.2
V
1
Output Low Voltage
I
OLT
= 2mA
V
OL
2
0.7
V
1
Output High Voltage
I
OHC
= 100A
V
OH
1
2.1
V
1
Output High Voltage
I
OHT
= 2mA
V
OH
2
1.7
V
1
36
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD
512K x 18
DESCRIPTION
REVISION NUMBER
xxxx
Reserved for version number.
(31:28)
DEVICE DEPTH
00111
Defines depth of 512K or 1Mb words.
(27:23)
DEVICE WIDTH
00011
Defines width of x18, x32, or x36 bits.
(22:18)
MICRON DEVICE ID
xxxxxx
Reserved for future use.
(17:12)
MICRON JEDEC ID
00000101100
Allows unique identification of SRAM vendor.
CODE (11:1)
ID Register Presence
1
Indicates the presence of an ID register.
Indicator (0)
INSTRUCTION CODES
INSTRUCTION
CODE
DESCRIPTION
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.
SCAN REGISTER SIZES
REGISTER NAME
BIT SIZE
Instruction
3
Bypass
1
ID
32
Boundary Scan
x18: 52
x32: 67
x36: 71
37
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
35
DQb
2D
36
DQb
2E
37
DQb
2F
38
DQb
2G
39
V
DD
1H
40
DQb
1J
41
DQb
1K
42
DQb
1L
43
DQb
1M
44
DQPb
1N
45
MODE (LBO#)
1R
46
SA
3P
47
SA
3R
48
SA
4P
49
SA
4R
50
SA1
6P
51
SA0
6R
FBGA BIT# SIGNAL NAME
FBGA PIN ID
1
SA
8P
2
SA
9R
3
SA
9P
4
SA
10R
5
SA
10P
6
SA
11R
7
SA
8R
8
DQa
10M
9
DQa
10L
10
DQa
10K
11
DQa
10J
12
ZZ
11H
13
DQa
11G
14
DQa
11F
15
DQa
11E
16
DQa
11D
17
DQPa
11C
18
SA
11A
19
SA
10B
20
SA
10A
21
SA
9A
22
SA
9B
23
ADV/LD#
8A
24
OE# (G#)
8B
25
CKE#
7A
26
R/W#
7B
27
CLK
6B
28
CE2#
6A
29
BWa#
5B
30
BWb#
4A
31
CE2
3B
32
CE#
3A
33
SA
2A
34
SA
2B
165-PIN FBGA BOUNDARY SCAN ORDER (x18)
FBGA BIT# SIGNAL NAME
FBGA PIN ID
38
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
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MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
FBGA BIT# SIGNAL NAME
FBGA PIN ID
1
SA
8P
2
SA
9R
3
SA
9P
4
SA
10R
5
SA
10P
6
SA
11R
7
SA
8R
8
DQa
11M
9
DQa
11L
10
DQa
11K
11
DQa
11J
12
DQa
10M
13
DQa
10L
14
DQa
10K
15
DQa
10J
16
ZZ
11H
17
DQb
11G
18
DQb
11F
19
DQb
11E
20
DQb
11D
21
DQb
10G
22
DQb
10F
23
DQb
10E
24
DQb
10D
25
SA
10B
26
SA
10A
27
SA
9A
28
SA
9B
29
ADV/LD#
8A
30
OE# (G#)
8B
31
CKE#
7A
32
R/W#
7B
33
CLK
6B
165-PIN FBGA BOUNDARY SCAN ORDER (x32)
FBGA BIT# SIGNAL NAME
FBGA PIN ID
34
CE2#
6A
35
BWa#
5B
36
BWb#
5A
37
BWc#
4A
38
BWd#
4B
39
CE2
3B
40
CE#
3A
41
SA
2A
42
SA
2B
43
DQc
1D
44
DQc
1E
45
DQc
1F
46
DQc
1G
47
DQc
2D
48
DQc
2E
49
DQc
2F
50
DQc
2G
51
V
DD
1H
52
DQd
1J
53
DQd
1K
54
DQd
1L
55
DQd
1M
56
DQd
2J
57
DQd
2K
58
DQd
2L
59
DQd
2M
60
MODE (LBO#)
1R
61
SA
3P
62
SA
3R
63
SA
4P
64
SA
4R
65
SA1
6P
66
SA0
6R
39
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
FBGA BIT# SIGNAL NAME
FBGA PIN ID
1
SA
8P
2
SA
9R
3
SA
9P
4
SA
10R
5
SA
10P
6
SA
11R
7
SA
8R
8
NF/
DQPa
11N
9
DQa
11M
10
DQa
11L
11
DQa
11K
12
DQa
11J
13
DQa
10M
14
DQa
10L
15
DQa
10K
16
DQa
10J
17
ZZ
11H
18
DQb
11G
19
DQb
11F
20
DQb
11E
21
DQb
11D
22
DQb
10G
23
DQb
10F
24
DQb
10E
25
DQb
10D
26
NF/
DQPb
11C
27
SA
10B
28
SA
10A
29
SA
9A
30
SA
9B
31
ADV/LD#
8A
32
OE# (G#)
8B
33
CKE#
7A
34
R/W#
7B
35
CLK
6B
36
CE2#
6A
165-PIN FBGA BOUNDARY SCAN ORDER (x36)
FBGA BIT# SIGNAL NAME
FBGA PIN ID
37
BWa#
5B
38
BWb#
5A
39
BWc#
4A
40
BWd#
4B
41
CE2
3B
42
CE#
3A
43
SA
2A
44
SA
2B
45
NF/
DQPc
1C
46
DQc
1D
47
DQc
1E
48
DQc
1F
49
DQc
1G
50
DQc
2D
51
DQc
2E
52
DQc
2F
53
DQc
2G
54
V
DD
1H
55
DQd
1J
56
DQd
1K
57
DQd
1L
58
DQd
1M
59
DQd
2J
60
DQd
2K
61
DQd
2L
62
DQd
2M
63
NF/
DQPd
1N
64
MODE (LBO#)
1R
65
SA
3P
66
SA
3R
67
SA
4P
68
SA
4R
69
SA1
6P
70
SA0
6R
40
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
35
DQb
1D
36
DQb
2E
37
DQb
2G
38
DQb
1H
39
V
DD
5R
40
DQb
2K
41
DQb
1L
42
DQb
2M
43
DQb
1N
44
DQPb
2P
45
MODE (LBO#)
3R
46
SA
2C
47
SA
3C
48
SA
2R
49
SA
3T
50
SA1
4N
51
SA0
4P
BGA BIT#
SIGNAL NAME
BGA PIN ID
1
SA
2T
2
SA
6R
3
SA
5T
4
SA
3B
5
SA
5B
6
SA
5C
7
SA
6C
8
DQa
7P
9
DQa
6N
10
DQa
6L
11
DQa
7K
12
ZZ
7T
13
DQa
6H
14
DQa
7G
15
DQa
6F
16
DQa
7E
17
DQPa
6D
18
SA
6T
19
SA
6A
20
SA
5A
21
SA
4G
22
SA
4A
23
ADV/LD#
4B
24
OE# (G#)
4F
25
CKE#
4M
26
R/W#
4H
27
CLK
4K
28
CE2#
6B
29
BWa#
5L
30
BWb#
3G
31
CE2
2B
32
CE#
4E
33
SA
3A
34
SA
2A
119-PBGA BOUNDARY SCAN ORDER (x18)
BGA BIT#
SIGNAL NAME
BGA PIN ID
41
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
FBGA BIT# SIGNAL NAME
FBGA PIN ID
1
SA
4T
2
SA
6R
3
SA
5T
4
SA
3B
5
SA
5B
6
SA
5C
7
SA
6C
8
DQa
7N
9
DQa
6M
10
DQa
7L
11
DQa
6K
12
DQa
7P
13
DQa
6N
14
DQa
6L
15
DQa
7K
16
ZZ
7T
17
DQb
6H
18
DQb
7G
19
DQb
6F
20
DQb
7E
21
DQb
6E
22
DQb
7H
23
DQb
7D
24
DQb
6G
25
SA
6A
26
SA
5A
27
SA
4G
28
SA
4A
29
ADV/LD#
4B
30
OE# (G#)
4F
31
CKE#
4M
32
R/W#
4H
33
CLK
4K
FBGA BIT# SIGNAL NAME
FBGA PIN ID
34
CE2#
6B
35
BWa#
5L
36
BWb#
5G
37
BWc#
3G
38
BWd#
3L
39
CE2
2B
40
CE#
4E
41
SA
3A
42
SA
2A
43
DQc
1E
44
DQc
2F
45
DQc
1G
46
DQc
2H
47
DQc
1D
48
DQc
2E
49
DQc
2G
50
DQc
1H
51
V
DD
5R
52
DQd
2K
53
DQd
1L
54
DQd
2M
55
DQd
1N
56
DQd
1P
57
DQd
1K
58
DQd
2L
59
DQd
2N
60
MODE (LBO#)
3R
61
SA
2C
62
SA
3C
63
SA
2R
64
SA
3T
65
SA1
4N
66
SA0
4P
119-PBGA BOUNDARY SCAN ORDER (x32)
42
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
BGA BIT#
SIGNAL NAME
BGA PIN ID
1
SA
4T
2
SA
6R
3
SA
5T
4
SA
3B
5
SA
5B
6
SA
5C
7
SA
6C
8
NF/
DQPa
6P
9
DQa
7N
10
DQa
6M
11
DQa
7L
12
DQa
6K
13
DQa
7P
14
DQa
6N
15
DQa
6L
16
DQa
7K
17
ZZ
7T
18
DQb
6H
19
DQb
7G
20
DQb
6F
21
DQb
7E
22
DQb
6E
23
DQb
7H
24
DQb
7D
25
DQb
6G
26
NF/
DQPb
6D
27
SA
6A
28
SA
5A
29
SA
4G
30
SA
4A
31
ADV/LD#
4B
32
OE# (G#)
4F
33
CKE#
4M
34
R/W#
4H
35
CLK
4K
36
CE2#
6B
119-PBGA BOUNDARY SCAN ORDER (x36)
BGA BIT#
SIGNAL NAME
BGA PIN ID
37
BWa#
5L
38
BWb#
5G
39
BWc#
3G
40
BWd#
3L
41
CE2
2B
42
CE#
4E
43
SA
3A
44
SA
2A
45
NF/
DQPc
2D
46
DQc
1E
47
DQc
2F
48
DQc
1G
49
DQc
2H
50
DQc
1D
51
DQc
2E
52
DQc
2G
53
DQc
1H
54
V
DD
5R
55
DQd
2K
56
DQd
1L
57
DQd
2M
58
DQd
1N
59
DQd
1P
60
DQd
1K
61
DQd
2L
62
DQd
2N
63
NF/
DQPd
2P
64
MODE (LBO#)
3R
65
SA
2C
66
SA
3C
67
SA
2R
68
SA
3T
69
SA1
4N
70
SA0
4P
43
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
100-PIN PLASTIC TQFP
(JEDEC LQFP)
14.00 0.10
1.40 0.05
16.00 0.20
0.10
+0.10
-0.05
0.15
+0.03
-0.02
22.10
+0.10
-0.20
0.32
+0.06
-0.10
20.10 0.10
0.65 TYP
0.62
1.60 MAX
DETAIL A
SEE DETAIL A
0.60 0.15
0.60 0.15
1.00 TYP
GAGE PLANE
0.10
0.10
PIN #1 ID
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
44
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
119-PIN BGA
7.62
20.32
19.94 0.10
11.94 0.10
1.27 (TYP)
1.27 (TYP)
0.60 0.10
2.40 MAX
0.90 0.10
14.00 0.10
22.00 0.20
A1 CORNER
A1 CORNER
(dimension applies to a
noncollapsed solder ball)
Substrate material:
BT resin laminate
0.15
SEATING PLANE
0.75 0.15
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Solder ball land pad is 0.6mm.
45
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
165-PIN FBGA
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
10.00
14.00
15.00 0.10
1.00
TYP
1.00
TYP
5.00 0.05
13.00 0.10
PIN A1 ID
PIN A1 ID
BALL A1
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
6.50 0.05
7.00 0.05
7.50 0.05
1.20 MAX
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb
SOLDER BALL PAD: .33mm
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS 0.40
SEATING PLANE
0.85 0.075
0.12 C
C
165X 0.45
BALL A11
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc.,
and the architecture is supported by Micron Technology, Inc., and Motorola Inc.
46
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L1MY18P_C.p65 Rev. 9/01
2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
REVISION HISTORY
Rev. C, Pub. 9/01 ................................................................................................................................................................ Sept/01
Removed Industrial Temperature references
Removed -5 speed grade
Changed I
DD
tables by splitting x18 and x32/36 configuration
Changed NC references to NF
Removed note "Not Recommended for New Design" from 119-pin FBGA
Changed boundary scan order, 165-pin FBGA, x18 and x32/36
8P (SA) moved to bit #7 from bit #1
Increased I
DD
table values
Rev. 3/01 ..................................................................................................................................................................... March/19/01
Added Industrial Temperature note and references
Changed 16Mb references to 18Mb
Added new -5 speed grade
Rev. 1/01 .......................................................................................................................................................................... Jan/10/01
Added 165-pin FBGA Boundary Scan
Added 119-pin PBGA package and references
Rev. 8/00, ADVANCE .................................................................................................................................................... Aug/22/00
Removed FBGA Part Marking Guide
Rev. 7/00, ADVANCE ...................................................................................................................................................... Aug/8/00
Changed FBGA capacitance values
C
I
; TYP 2.5 pF from 4 pF; MAX 3.5 pF from 5 pF
C
O
; TYP 4 pF from 6 pF; MAX 5 pF from 7 pF
C
CK
; TYP 2.5 pF from 5 pF; MAX 3.5 pF from 6 pF
Rev. 7/00, ADVANCE ..................................................................................................................................................... Jun/28/00
Added 165-Pin FBGA Package
Added FBGA Part Marking References
Removed 119-Pin PBGA and references
Removed Smart ZBT and references
Rev. 4/00, ADVANCE ..................................................................................................................................................... Apr/13/00
Added note: ZZ has internal pull-down
Rev. 3/00, ADVANCE ....................................................................................................................................................... Apr/6/00
Updated Boundary Scan Order
Rev. 1/00, ADVANCE ..................................................................................................................................................... Jan/18/00
Added BGA JTAG functionality
Added 119-pin PBGA package
Added SMART ZBT functionality
Added ADVANCE status
Original document, Rev. 11/99, DRAFT ..................................................................................................................... Nov/11/99
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