32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

SYNCHRONOUS DRAM
MODULE

MT5LSDT472A -32MB

MT5LSDT872A(I) - 64MB
MT5LSDT1672A(I) - 128MB

For the latest data sheet, please refer to the Micron Web
site:

www.micron.com/moduleds

Features

· PC100- and PC133-compliant
· JEDEC-standard, 168-pin, dual in-line memory

module (DIMM)

· Unbuffered
· 32MB (4 Meg x 72), 64MB (8 Meg x 72), 128MB (16

Meg x 72)

· ECC-Optimized Pinout
· Single +3.3V ±0.3V power supply
· Fully synchronous; all signals registered on positive

edge of system clock

· Internal pipelined operation; column address can

be changed every clock cycle

· Internal SDRAM banks for hiding row access/precharge
· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge, including CONCURRENT AUTO

PRECHARGE, and Auto Refresh Modes

· Self Refresh Mode
· 32/64MB: 64ms, 4,096-cycle refresh; 128MB: 64ms,

8,192-cycle refresh

· LVTTL-compatible inputs and outputs
· Serial Presence-Detect (SPD)

Figure 1: 168-Pin DIMM MO-161

OPTIONS

MARKING

· Package

168-pin DIMM (gold)

· Operating Temperature Range

Commercial (0°C to +70°C)

None

Industrial (-40°C to +85°C)

NOTE:

1. Consult Micron for availability; Industrial Temperature

option available in -133 speed only.

· Frequency / CAS Latency

7.5ns (133 MHz) / CL = 2

-13E

7.5ns (133 MHz) / CL = 3

-133

8ns (100 MHz) / CL = 2

-10E

Table 1:

Address Table

32MB

MODULE

64MB

MODULE

128MB

MODULE

Refresh Count

Device Banks

4 (BA0, BA1)

Device Conf.

4 Meg x 16

8 Meg x 16 16 Meg x 16

Row Addressing 4K (A0-A11) 4K (A0-A11) 8K (A0-A12)
Column Addr.

256 (A0-A7) 512 (A0-A8) 512 (A0-A8)

Module Banks

1 (S0, S2)

Table 2:

Timing Parameters

MODULE

MARKING

PC100

(CL -

RCD -

RP)

PC133

(CL -

RCD -

RP)

-13E

2 - 2 - 2

-133

2 - 2 - 2

3 - 3 - 3

-10E

2 - 2 - 2

n/a

Table 3:

Part Numbers

PART NUMBER

CONFIGURATION

SYSTEM

BUS SPEED

MT5LSDT472AG-13E_

4 Meg x 72

133 MHz

MT5LSDT472AG-133_

4 Meg x 72

133 MHz

MT5LSDT472AG-10E_

4 Meg x 72

100 MHz

MT5LSDT872AG-13E_

8 Meg x 72

133 MHz

MT5LSDT872A(I)G-133_

8Meg x 72

133 MHz

MT5LSDT872AG-10E_

8 Meg x 72

100 MHz

MT5LSDT1672AG-13E_

16 Meg x 72

133 MHz

MT5LSDT1672A(I)G-133_

16 Meg x 72

133 MHz

MT5LSDT1672AG-10E_

16 Meg x 72

100 MHz

NOTE:

The designators for component and PCB revision are the last
two characters of each part number. Consult factory for cur-
rent revision codes. Example: MT5LSDT1672AG-133B1.

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

NOTE:

Pin 126 is NC for 32MB and 64MB modules, or A12 for the 128MB module.

Figure 2: Pin Locations (168-Pin DIMM)

Table 4:

Pin Assignment

(168-Pin DIMM Front)

PIN SYMBOL PIN

SYMBOL

CB1

DQ0

DQ21

DQ1

S2#

DQ22

DQ2

DQM2

DQ23

DQ3

DQM3

WE#

DQ24

DQ4

DQM0

DQ25

DQ5

DQM1

DQ26

DQ6

S0#

DQ27

DQ7

CB2

DQ8

CB3

DQ28

DQ29

DQ9

DQ16

DQ30

DQ10

DQ17

DQ31

DQ11

DQ18

DQ12

DQ19

CK2

DQ13

A10

BA1

DQ20

DQ14

SDA

DQ15

SCL

CB0

CKO

CKE1

Table 5:

Pin Assignment

(168-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN

SYMBOL

106

CB5

127

148

DQ32

107

128

CKE0

149

DQ53

DQ33

108

129

DNU

150

DQ54

DQ34

109

130

DQM6

151

DQ55

DQ35

110

131

DQM7

152

111

CAS#

132

DNU

153

DQ56

DQ36

112

DQM4

133

154

DQ57

DQ37

113

DQM5

134

155

DQ58

DQ38

114

DNU

135

156

DQ59

DQ39

115

RAS#

136

CB6

157

DQ40

116

137

CB7

158

DQ60

117

138

159

DQ61

DQ41

118

139

DQ48

160

DQ62

DQ42

119

140

DQ49

161

DQ63

DQ43

120

141

DQ50

162

100

DQ44

121

142

DQ51

163

DNU

101

DQ45

122

BA0

143

164

102

123

A11

144

DQ52

165

SA0

103

DQ46

124

145

166

SA1

104

DQ47

125

DNU

146

167

SA2

105

CB4

126 NC/A12*

147

168

Back View

PIN 1

PIN 84

PIN 85

PIN 168

No Components on This Side of Module

Front View

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Table 6:

PIN Descriptions

Pins are listed in module pinout order and do not necessarily correlate with symbols.

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

27, 111, 115

RAS#, CAS#,

WE#,

Input

Command Inputs: RAS#, CAS#, and WE# (along with S0#, S2#)
define the command being entered.

42, 79

CK0, CK2

Input

Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.

128

CKE0

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in
progress). CKE is synchronous except after the device enters
power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input
buffers, including CK, are disabled during power-down and
self refresh modes, providing low standby power.

30, 45

S0#, S2#

Input

Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.

28, 29, 46, 47, 112, 113,

130, 131

DQM0-DQM7

Input

Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.

39, 122

BA0, BA1

Input

Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.

33-38, 117-121, 123,

126

(128MB)*

A0-A11

(32MB/64MB)

A0-A12

(128MB)

Input

Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto prcharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory arrary in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW
device bank selected by BA0, BA1) or all device banks (A10
HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command.

Input

Write Protect: Serial presence-detect hardware write protect.

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.

165-167

SA0-SA2

Input

Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.

SDA

Input/Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.

2-5, 7-11, 13-17, 19-20,

55-58, 60, 65-67, 69-72,
74-77, 86-89, 91-95, 97-

101, 103-104, 139-142,
144, 149-151, 153-156,

158-161*

DQ0-DQ63

Input/Output

Data I/Os: Data bus.

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Figure 3: Functional Block Diagram

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQMH

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM4

S2#

RAS#

CAS#

CKE0

WE#

RAS#: SDRAMs

CAS#: SDRAMs

CKE: SDRAMs

WE#: SDRAMs

A0-A11: SDRAMs

A0-A12: SDRAMs

BA0-1: SDRAMs

A0-A11(32MB/64MB)

A0-A12(128MB)

BA0-1

SDRAMs U1-U5

DQML CS#

DQM0

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQMH

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQM5

DQM1

DQML CS#

DQM1

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQMH

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQM6

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQML CS#

DQM2

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQMH

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQM7

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQML CS#

DQM3

S0#

10pF

CK1, CK3

CK0

6.6pF

SA0

SPD

SDA

SA1

SA2

SCL

U1
U2
U3

CK2

13.6pF

DQMH

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

DQML CS#

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

Note:
1. All resistor values are 10

W unless otherwise specified.

2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at

www.micron.com/numberguide

U1-U5 = MT48LC4M16A2TG SDRAMs for 32MB Comm. Temp.
U1-U5 = MT48LC8M16A2TG SDRAMs for 64MB Comm. Temp.
U1-U5 = MT48LC16M16A2TG SDRAMs for 128MB Comm. Temp.
U1-U5 = MT48LC8M16A2TG-75 IT SDRAMs for 64MB Ind. Temp.
U1-U5 = MT48LC16M16A2TG-75 IT SDRAMs for 128MB Ind. Temp.

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

General Description

The Micron

MT5LSDT472A, MT5LSDT872A(I), and

MT5LSDT1672A(I) are a high-speed CMOS, dynamic
random-access, 32MB, 64MB, and 128MB memory
modules organized in a x72, ECC configuration. ECC
functions to detect and correct one-bit memory errors.
These module use SDRAM devices which are internally
configured as quad-bank DRAMs with a synchronous
interface (all signals are registered on the positive edge
of the clock signals CK0, CK2). The four banks of the
x16 configured devices used for these modules are
configured as 4,096 bit-rows by 256 bit-columns, by 16
input/output bits for the 32MB module; 4,096 bit-rows
by 512 bit-columns, by 16 input/output bits for the
64MB; module and 8,192 bit-rows by 512 bit-columns,
by 16 input/output bits for the 128MB module.

Read and write accesses to the SDRAM module are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank, A0-A11 for
32MB/64MB; A0-A12 for 128MB select the device row).
The address bits registered coincident with the READ
or WRITE command(A0-A7 32MB; A0-A8 64/128MB)
are used to select the starting device column location
for the burst access.

These modules provide for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst

sequence. These modules use an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device
bank while accessing one of the other three device
banks will hide the PRECHARGE cycles and provide
seamless, high-speed, random access operation.

These modules are designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs, outputs, and clocks are LVTTL-compatible.

SDRAM modules offer substantial advances in

DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between internal banks in order to hide

precharge time, and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 64Mb, 128Mb, or 256Mb SDRAM
component data sheets.

Serial Presence-Detect Operation

These modules incorporate serial presence-detect

(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus
using the DIMM's SCL (clock) and SDA (data) signals.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V

and V

Q (simulta-

neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP. Starting at some point during
this 100µs period and continuing at least through the
end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode, and a write burst
mode, as shown in the Mode Register Definition Dia-
gram. The mode register is programmed via the LOAD

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.

Mode register bits M0M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-
leaved), M4M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. For the 128MB module, Address A12 (M12) is
undefined but should be driven LOW during loading of
the mode register.

The mode register must be loaded when all device

banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as
shown in Figure 4, Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4, or 8
locations are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is used
in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Burst
Definition Table. The block is uniquely selected by A1
A7 (32MB) or A1-A8 (64MB/128MB) when the burst
length is set to two; by A2A7 or A2-A8 when the burst
length is set to four; and by A3A7 or A3-A8 when the
burst length is set to eight. The remaining (least signif-
icant) address bit(s) is (are) used to select the starting
location within the block. Full-page bursts wrap within
the page if the boundary is reached, as shown in
Table 7, Burst Definition Table, on page 8.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7, Burst
Definition Table, on page 8.

Figure 4: Mode Register Definition

Diagram

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

128MB Module

32MB Module, 64MB Module

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

A10

A11

Reserved*

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = "0, 0, 0"

to ensure compatibility

with future devices.

*Should program

M11 and M10 = "0, 0, 0"

to ensure compatibility

with future devices.

A12

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

Op Mode

A10

A11

Reserved* WB

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

NOTE:

1. For full-page accesses: y = 256 (32MB); y = 512 (64MB/

128MB).

2. For a burst length of two, A1-Ai select the block-of-two

burst; A0 selects the starting column within the block.

3. For a burst length of four, A2-Ai select the block-of-four

burst; A0-A1 select the starting column within the block.

4. For a burst length of eight, A3-Ai select the block-of-eight

burst; A0-A2 select the starting column within the block.

5. For a full-page burst, the full row is selected and

A0-Ai select the starting column.

6. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps within
the block.

7. For a burst length of one, A0-Ai select the unique column

to be accessed, and mode register bit M3 is ignored.

CAS Latency

The CAS latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 5, CAS Latency
Diagram. The CAS Latency Table indicates the operat-
ing frequencies at which each CAS latency setting can
be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Figure 5: CAS Latency Diagram

Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.

Table 7:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WTHIN A

BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1 A0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-4-5-6-7-0-1-2-

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

Page (y)

n = A0-Ai*

(location

0-y)

Cn, Cn + 1,

Cn + 2, Cn + 3,

Cn + 4. . . Cn - 1,

Cn . . .

Not supported

* i = 7 for 32MB module
i = 8 for 64MB and 128MB modules

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Commands

This Truth Table provides a general reference of

available commands. For a more detailed description

of commands and operations, refer to the 64Mb,
128Mb, or 256Mb SDRAM component data sheet.

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register, and for the 128MB module, A12 should be driven LOW.
3. A0-A11 (32MB/64MB) or A0-A12 (128MB) provide device row address, and BA0, BA1 determine which device bank is made active.
4. A0-A7 (32MB) or A0-A8 (64MB/128MB) provide device column address; A10 HIGH enables the auto precharge feature (nonpersis-

tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the device bank being precharged. A10 HIGH: All device banks precharged and BA0, BA1 are "Don't

Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls device row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

Table 9:

Truth Table Commands and DQMB Operation

Note: 1

NAME (FUNCTION)

CS#

RAS# CAS# WE#

DQMB

ADDR

DQS

NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ
burst)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE
burst)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH

(Enter self refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

Write Enable/Output enable

Active

Write Inhibit/Output High-Z

High-Z

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Absolute Maximum Ratings*

Voltage on V

, V

Q Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Operating Temperature

(Commercial) . . . . . . . . . . . . . . . . . .0°C to +70°C

(Industrial). . . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature (plastic) . . . . . .-55°C to +150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5W

*Stresses greater than those listed under "Absolute

Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1, 5, 6; notes appear following the parameter tables; V

, V

Q = +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

0.8

INPUT LEAKAGE CURRENT: Any input 0V
£ V

£ V

(All other pins not under

test = 0V)

Command/
Address, CKE0

-25

µA

CK0, S0

-15

CK2, S2

-10

DQ, DQM

-5

OUTPUT LEAKAGE CURRENT: DQs are disabled;

£ V

OUT

£ V

-5

µA

OUTPUT LEVELS: Output High Voltage
(I

OUT

= -4mA)

2.4

Output Low Voltage (I

OUT

= 4mA)

0.4

Table 11: I

Specifications and Conditions 32MB Module

Notes: 1, 5, 6, 11, 13; notes appear following the parameter tables; V

, V

Q = +3.3V ±0.3V; DRAM components only

MAX

PARAMETER/CONDITION

SYMBOL

-13E

-133

-10E

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or

WRITE;

RC =

RC (MIN)

625

575

475

3, 18, 19, 29

STANDBY CURRENT: Power-Down Mode; All device banks
idle; CKE = LOW

STANDBY CURRENT: Active Mode; CKE = HIGH; CS# =

HIGH; All device banks active after

RCD met; No accesses

in progress

225

175

3, 12, 19, 29

OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; All device banks active

750

700

600

3, 18, 19, 29

AUTO REFRESH CURRENT

CS# = HIGH; CKE = HIGH

RFC =

RFC (MIN)

1,150

1,050

950

3, 12, 18, 19,

29, 30

RFC = 15.62µs

SELF REFRESH CURRENT: CKE

£ 0.2V

32MB / 64MB / 128MB (x72)

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32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Table 12: I

Specifications and Conditions 64MB Module

Notes: 1, 5, 6, 11, 13; notes appear following the parameter tables; V

, V

Q = +3.3V ±0.3V; DRAM components only

MAX

PARAMETER/CONDITION

SYMBOL

-13E

-133

-10E

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or

WRITE;

RC =

RC (MIN)

800

750

700

3, 18, 19, 29

STANDBY CURRENT: Power-Down Mode; All device banks
idle; CKE = LOW

STANDBY CURRENT: Active Mode; CKE = HIGH; CS# =

HIGH; All device banks active after

RCD met; No accesses

in progress

250

200

3, 12, 19, 29

OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; All device banks active

825

750

700

3, 18, 19, 29

AUTO REFRESH CURRENT

CS# = HIGH; CKE = HIGH

RFC =

RFC (MIN)

1,650

1,550

1,350

3, 12, 18, 19,

29, 30

RFC = 15.62µs

SELF REFRESH CURRENT: CKE

£ 0.2V

Table 13: I

Specifications and Conditions 128MB Module

Notes: 1, 5, 6, 11, 13; notes appear following the parameter tables; V

, V

Q = +3.3V ±0.3V; DRAM components only

MAX

PARAMETER/CONDITION

SYMBOL

-13E

-133

-10E

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or

WRITE;

RC =

RC (MIN)

625

3, 18, 19, 29

STANDBY CURRENT: Power-Down Mode; All device banks
idle; CKE = LOW

STANDBY CURRENT: Active Mode; CKE = HIGH; CS# =

HIGH; All device banks active after

RCD met; No accesses

in progress

200

3, 12, 19, 29

OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; All device banks active

675

3, 18, 19, 29

AUTO REFRESH CURRENT

CS# = HIGH; CKE = HIGH

RFC =

RFC (MIN)

1,425

1,350

3, 12, 18, 19,

29, 30

RFC = 7.81µs

17.5

SELF REFRESH CURRENT: CKE

£ 0.2V

12.5

Table 14: Capacitance

Notes 1, 2; notes appear following parameter table

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Capacitance: A0-A12, BA0, BA1, RAS, CAS, WE, CKE0

12.5

Input Capacitance: S0

7.5

11.4

Input Capacitance: S2

7.6

Input Capacitance: CK0

14.1

17.1

Input Capacitance: CK2

18.6

20.6

Input Capacitance: DQMB0-DQMB7

2.5

3.8

Inuput/Output Capacitance: DQ0-DQ63

32MB / 64MB / 128MB (x72)

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32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Table 15: Electrical Characteristics and Recommended AC Operating Conditions

Notes: 5, 6, 8, 9, 11, 31; notes appear following the parameter tables; V

, V

Q = +3.3V ±0.3V

AC CHARACTERISTICS

-13E

-133

-10E

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS NOTES

Access time from CLK

(pos. edge)

CL = 3

AC(3)

5.4

CL = 2

AC(2)

5.4

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time

CL = 3

CK(3)

7.5

CL = 2

CK(2)

7.5

CKE hold time

CKH

0.8

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold
time

CMH

0.8

CS#, RAS#, CAS#, WE#, DQM setup
time

CMS

1.5

Data-in hold time

0.8

Data-in setup time

1.5

Data-out high-impedance
time

CL = 3

HZ(3)

5.4

CL = 2

HZ(2)

5.4

Data-out low-impedance time

Data-out hold time (load)

Data-out hold time (no load)

1.8

ACTIVE to PRECHARGEcommand

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period (8,192 rows)

REF

AUTO REFRESH period

RFC

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b
command

RRD

Transition time

0.3

1.2

0.3

1.2

0.3

1.2

WRITE recovery time

1 CLK +

7ns

1 CLK +

7.5ns

1 CLK +

7ns

Exit SELF REFRESH to ACTIVE
command

XSR

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SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Table 16: AC Functional Characteristics

Notes: 5, 6, 8, 9, 11, 31; notes appear following the parameter tables

PARAMETER

SYMBOL

-13E

-133

-10E

UNITS NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVE command

DAL

15, 21

Data-into PRECHARGE command

DPL

16, 21

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH command

MRD

Data-out to high-impedance from PRECHARGE
command

CL =3

ROH(3)

CL = 2

ROH(2)

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SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Notes

1. All voltages referenced to V

2. This parameter is sampled. V

, V

Q = +3.3V;

f = 1 MHz; T

= 25°C; pin under test biased at 1.4V.

3. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to

indicate cycle time at which proper operation
over the full temperature range is ensured (0°C

£ +70°C for Commercial, -40°C £ T

£ +85°C for

Industrial).

6. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V

and V

Q must be powered up simultaneously.

and V

Q must be at same potential.) The two

AUTO REFRESH command wake-ups should be

repeated any time the

REF refresh requirement is

exceeded.

7. AC characteristics assume

T = 1ns.

8. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between
V

and V

(or between V

and V

) in a mono-

tonic manner.

9. Outputs measured at 1.5V with equivalent load:

10.

HZ defines the time at which the output achieves

the open circuit condition; it is not a reference to
V

or V

. The last valid data element will meet

OH before going High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V,

with timing referenced to 1.5V crossover point. If the
input transition time is longer than 1ns, then the
timing is referenced at V

(MAX) and V

(MIN) and

no longer at the ISV crossover point.

12. Other input signals are allowed to transition no

more than once every two clocks and are other-
wise at valid V

or V

levels.

13. I

specifications are tested after the device is

properly initialized.

14. Timing actually specified by

CKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

15. Timing actually specified by

WR plus

RP; clock(s)

specified as a reference only at minimum cycle
rate.

16. Timing actually specified by

WR.

17. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-
eter.

18. The I

current will increase or decrease propor-

tionally according to the amount of frequency
alteration for the test condition.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on

CK = 10ns for -10E;

CK = 7.5ns for -133

and -13E.

22. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

£ 3ns, and the pulse width cannot be

greater than one-third of the cycle rate. V

under-

shoot: V

(MIN) = -2V for a pulse width

£ 3ns.

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing

WR and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing

budget (

RP) begins 7ns for -13E; 7.5ns for -133;

and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.

25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.

AC for -133/-13E at CL = 3 with no load is 4.6ns

and is guaranteed by design.

28. Parameter guaranteed by design.
29. For -13E, CL = 2 and

CK = 7.5ns; for -133, CL = 3

and

CK = 7.5ns; for -10E, CL=2 and

CK = 10ns.

30. CKE is HIGH during refresh command period

RFC (MIN), else CKE is LOW. The I

6 limit is

actually a nominal value and does not result in a
fail value.

31. Refer to device data sheet for timing waveforms.
32. The value of

RAS used in -13E speed grade mod-

ules is calculated from

RC -

RP.

33. Leakage number reflects the worst-case leakage

possible through the module pin, not what each
memory device contributes.

50pF

32MB / 64MB / 128MB (x72)

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SD5C4_8_16X72AG_B.fm - Rev. B 9/02

SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions, as
indicated in Figure 6, Data Validity, and Figure 7, Defi-
nition of Start and Stop.

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data as indicated in
Figure Figure 8, Acknowledge Response from Receiver.

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode, the SPD device

will transmit eight bits of data, release the SDA line,
and monitor the line for an acknowledge. If an
acknowledge is detected and no stop condition is gen-
erated by the master, the slave will continue to trans-
mit data. If an acknowledge is not detected, the slave
will terminate further data transmissions and await
the stop condition to return to standby power mode.

Figure 6: Data Validity

Figure 7: Definition of Start and Stop

Figure 8: Acknowledge Response from Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

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SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Table 17: EEPROM Device Select Code

The most significant bit (b7) is sent first

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 18: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

or V

START, Device Select, RW = `1'

Random Address Read

or V

START, Device Select, RW = `0', Address

or V

reSTART, Device Select, RW = `1'

Sequential Read

or V

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = `0'

Page Write

£ 16

START, Device Select, RW = `0'

Table 19: Serial Presence-Detect EEPROM DC Operating Conditions

= +3.3V ±0.3V; all voltages referenced to V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

x 0.7

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

x 0.3

OUTPUT LOW VOLTAGE: I

OUTL

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

µA

STANDBY CURRENT: SCL = SDA = V

- 0.3V;

All other inputs = GND or 3.3V ±10%

µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz

32MB / 64MB / 128MB (x72)

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SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Figure 9: SPD EEPROM Timing Diagram

NOTE:

1. Timing actually specified ty

WR.

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

Table 20: Serial Presence-Detect EEPROM AC Operating Conditions

= +3.3V ±0.3V; all voltages referenced to V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.3

3.5

µs

Time the bus must be free before a new transition can
start

BUF

4.7

µs

Data-out hold time

300

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

µs

Clock HIGH period

HIGH

µs

Noise suppression time constant at SCL, SDA inputs

100

Clock LOW period

LOW

4.7

µs

SDA and SCL rise time

µs

SCL clock frequency

SCL

100

KHz

Data-in setup time

SU:DAT

250

Start condition setup time

SU:STA

4.7

µs

Stop condition setup time

SU:STO

4.7

µs

WRITE cycle time

WRC

32MB / 64MB / 128MB (x72)

168-PIN SDRAM DIMMs

32, 64, 128MB x 64 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD5C4_8_16X72AG_B.fm - Rev. B 9/02

Table 21: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."

BYTE

DESCRIPTION

ENTRY

(VERSION)

MT5LSDT472A MT5LSDT872A(I) MT5LSDT1672A(I)

NUMBER OF BYTES USED BY MICRON

128

TOTAL NUMBER OF SPD MEMORY BYTES

256

MEMORY TYPE

SDRAM

NUMBER OF ROW ADDRESSES

12 or 13

NUMBER OF COLUMN ADDRESSES

8 or 9

NUMBER OF BANKS

MODULE DATA WIDTH

MODULE DATA WIDTH (continued)

MODULE VOLTAGE INTERFACE LEVELS

LVTTL

SDRAM CYCLE TIME,

(CAS LATENCY = 3)

7ns (-13E)

7.5ns (-133)

8ns (-10E)

70
75
80

SDRAM ACCESS FROM CLOCK,

(CAS LATENCY = 3)

5.4ns (-13E/-133)

6ns (-10E)

54
60

MODULE CONFIGURATION TYPE

ECC

REFRESH RATE/TYPE

(80) 15.6µs/SELF
(82) 7.81µs/SELF

SDRAM WIDTH (PRIMARY SDRAM)

ERROR-CHECKING SDRAM DATA WIDTH

MINIMUM CLOCK DELAY,

CCD

BURST LENGTHS SUPPORTED

1, 2, 4, 8, PAGE

NUMBER OF INTERNAL BANKS
ON SDRAM DEVICE

CAS LATENCIES SUPPORTED

2, 3

CS LATENCY

WE LATENCY

SDRAM MODULE ATTRIBUTES

UNBUFFERED

SDRAM DEVICE ATTRIBUTES: GENERAL

SDRAM CYCLE TIME,

(CAS LATENCY = 2)

7.5ns (-13E)

10ns (-133/-10E)

SDRAM ACCESS FROM CK,

(CAS LATENCY = 2)

5.4ns (-13E)

6ns (-133/-10E)

54
60

SDRAM CYCLE TIME,

(CAS LATENCY = 1)

SDRAM ACCESS FROM CK,

(CAS LATENCY = 1)

MINIMUM ROW PRECHARGE TIME,

15ns (-13E)

20ns (-133/-10E)

0F
14

MINIMUM ROW ACTIVE TO ROW ACTIVE,

RRD

14ns (-13E)
15ns (-133)
20ns (-10E)

0E
0F
14

MINIMUM RAS# TO CAS# DELAY,

RCD

15ns (-13E)

20ns (-133/-10E)

0F
14

32MB / 64MB / 128MB (x72)

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SD5C4_8_16X72AG_B.fm - Rev. B 9/02

NOTE:

1. The value of

RAS used for the -13E part is calculated from

RC -

RP. Actual device specification value is 37ns.

MINIMUM RAS# PULSE WIDTH,

RAS

(Note 1)

45ns (-13E)
44ns (-133)
50ns (-10E)

2C
32

MODULE BANK DENSITY

32MB, 64MB, or

128MB

COMMAND AND ADDRESS SETUP TIME

1.5ns (-13E/-133)

2ns (-10E)

15
20

COMMAND AND ADDRESS HOLD TIME

0.8ns (-13E/-133)

1ns (-10E)

08
10

DATA SIGNAL INPUT SETUP TIME

1.5ns (-13E/-133)

2ns (-10E)

15
20

DATA SIGNAL INPUT HOLD TIME

0.8ns (-13E/-133)

1ns (-10E)

08
10

36-61 RESERVED

SPD REVISION

1.2

CHECKSUM FOR BYTES 0-62

-13E
-133
-10E

70
B6
FE

79
BF
07

D2
1A

MANUFACTURER'S JEDEC ID CODE

MICRON

65-71 MANUFACTURER'S JEDEC ID CODE

(continued)

MANUFACTURING LOCATION

1-11

01-0B

73-90 MODULE PART NUMBER (ASCII)

Variable Data

PCB IDENTIFICATION CODE

1-9

01-09

IDENTIFICATION CODE (continued)

YEAR OF MANUFACTURE IN BCD

Variable Data

WEEK OF MANUFACTURE IN BCD

Variable Data

95-98 MODULE SERIAL NUMBER

Variable Data

99-125 MANUFACTURER-SPECIFIC DATA (RSVD)

Variable Data

126

SYSTEM FREQUENCY

100/133 MHz

127

SDRAM COMPONENT AND CLOCK DETAIL

Table 21: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."

BYTE

DESCRIPTION

ENTRY

(VERSION)

MT5LSDT472A MT5LSDT872A(I) MT5LSDT1672A(I)

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Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT5LSDT872AIG-133_

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT5LSDT872AIG-133_