PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

SMALL-OUTLINE
DDR SDRAM MODULE

MT8VDDT1664HD 128MB
MT8VDDT3264HD 256MB
MT8VDDT6464HD 512MB

For the latest data sheet, please refer to the Micron

Web

site:

www.micron.com/moduleds

Features

· 200-pin, small-outline, dual in-line memory

module (SODIMM)

· Fast data transfer rates PC1600, PC2100, or PC2700
· Utilizes 200 MT/s, 266 MT/s, and 333MT/s DDR

SDRAM components

· 128MB (16 Meg x 64), 256MB (32 Meg x 64), or

512MB (64 Meg x 64)

· V

= V

Q = +2.5V

· V

DDSPD

= +2.3V to +3.6V

· 2.5V I/O (SSTL_2 compatible)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

· Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

· Bidirectional data strobe (DQS) transmitted/received

with data--i.e., source-synchronous data capture

· Differential clock inputs CK and CK#
· Four internal device banks for concurrent operation
· Programmable burst lengths: 2, 4, or 8
· Auto precharge option
· Serial Presence Detect (SPD) with EEPROM
· Programmable READ CAS latency
· Auto Refresh and Self Refresh Modes
· 15.6µs (128MB), 7.8125µs (256MB and 512MB)

maximum average periodic refresh interval

· Gold edge contacts

Figure 1: 200-Pin SODIMM (MO-224)

NOTE:

1. Consult with factory for availability of lead-free

products.

2. CL = CAS (READ) Latency

OPTIONS

MARKING

· Package

200-pin SODIMM (Standard)

200-pin SODIMM (Lead-free)

· Frequency/CAS Latency

6ns/166 MHz (333MT/s) CL=2.5

-335

7.5ns/133 MHz (266 MT/s) CL = 2

-262

7.5ns/133 MHz (266 MT/s) CL = 2

-26A

7.5ns/133 MHz (266 MT/s) CL = 2.5

-265

10ns/100 MHz (200 MT/s) CL = 2

-202

Table 1:

Address Table

128MB

256MB

512MB

Refresh Count

Row Addressing

4K (A0A11)

8K (A0A12)

Device Bank Addressing

4 (BA0, BA1)

Device Configuration

8 Meg x 16

16 Meg x 16

32 Meg x 16

Column Addressing

512 (A0A8)

1K (A0A9)

Module Rank Addressing

2 (S0#, S1#)

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Table 2:

Part Numbers and Timing Parameters

PART NUMBER

MODULE
DENSITY

CONFIGURATION

MODULE

BANDWIDTH

MEMORY CLOCK/

DATA BIT RATE

LATENCY

(CL -

RCD -

RP)

MT8VDDT1664HDG-335__

128MB

16 Meg x 64

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT8VDDT1664HDY-335__

128MB

16 Meg x 64

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT8VDDT1664HDG-262__

128MB

16 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT8VDDT1664HDY-262__

128MB

16 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT8VDDT1664HDG-26A__

128MB

16 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT8VDDT1664HDY-26A__

128MB

16 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT8VDDT1664HDG-265__

128MB

16 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT8VDDT1664HDY-265__

128MB

16 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT8VDDT1664HDG-202__

128MB

16 Meg x 64

1.6 GB/s

10ns/200 MT/s

2-2-2

MT8VDDT1664HDY-202__

128MB

16 Meg x 64

1.6 GB/s

10ns/200 MT/s

2-2-2

MT8VDDT3264HDG-335__

256MB

32 Meg x 64

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT8VDDT3264HDY-335__

256MB

32 Meg x 64

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT8VDDT3264HDG-262__

256MB

32 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT8VDDT3264HDY-262__

256MB

32 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT8VDDT3264HDG-26A__

256MB

32 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT8VDDT3264HDY-26A__

256MB

32 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT8VDDT3264HDG-265__

256MB

32 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT8VDDT3264HDY-265__

256MB

32 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT8VDDT3264HDG-202__

256MB

32 Meg x 64

1.6 GB/s

10ns/200 MT/s

2-2-2

MT8VDDT3264HDY-202__

256MB

32 Meg x 64

1.6 GB/s

10ns/200 MT/s

2-2-2

MT8VDDT6464HDG-335__

512MB

64 Meg x 64

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT8VDDT6464HDY-335__

512MB

64 Meg x 64

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT8VDDT6464HDG-262__

512MB

64 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT8VDDT6464HDY-262__

512MB

64 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT8VDDT6464HDG-26A__

512MB

64 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT8VDDT6464HDY-26A__

512MB

64 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT8VDDT6464HDG-265__

512MB

64 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT8VDDT6464HDY-265__

512MB

64 Meg x 64

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT8VDDT6464HDG-202__

512MB

64 Meg x 64

1.6 GB/s

10ns/200 MT/s

2-2-2

MT8VDDT6464HDY-202__

512MB

64 Meg x 64

1.6 GB/s

10ns/200 MT/s

2-2-2

NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT8VDDT3264HDG-265A1.

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

NOTE:

Pin 99 is No Connect for 128MB, A12 for 256MB and 512MB.

Figure 2: Module Layout

Table 3:

Pin Assignment
(200-Pin SODIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

REF

101

151

DQ42

DQ19

103

153

DQ43

DQ0

DQ24

105

155

DQ1

107

157

DQ25

109

159

DQS0

DQS3

111

161

DQ2

113

163

DQ48

DQ26

115

A10

165

DQ49

DQ3

DQ27

117

BA0

167

DQ8

119

WE#

169

DQS6

DNU

121

S0#

171

DQ50

DQ9

DNU

123

173

DQS1

125

175

DQ51

DNU

127

DQ32

177

DQ56

DQ10

DNU

129

DQ33

179

DQ11

131

181

DQ57

DNU

133

DQS4

183

DQS7

CK0

135

DQ34

185

CK0#

137

187

DQ58

DNU

139

DQ35

189

DQ59

DQ16

DNU

141

DQ40

191

DQ17

143

193

SDA

CKE1

145

DQ41

195

SCL

DQS2

147

DQS5

197

DDSPD

DQ18

NC/

A12

149

199

Table 4:

Pin Assignment
(200-Pin SODIMM BACK)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

REF

102

152

DQ46

DQ23

104

154

DQ47

DQ4

DQ28

106

156

DQ5

108

158

CK1#

DQ29

110

160

CK1

DM0

DM3

112

162

DQ6

114

164

DQ52

DQ30

116

BA1

166

DQ53

DQ7

DQ31

118

RAS#

168

DQ12

120

CAS#

170

DM6

DNU

122

S1#

172

DQ54

DQ13

DNU

124

174

DM1

126

176

DQ55

DNU

128

DQ36

178

DQ60

DQ14

DNU

130

DQ37

180

DQ15

132

182

DQ61

DNU

134

DM4

184

DM7

136

DQ38

186

138

188

DQ62

140

DQ39

190

DQ63

DQ20

142

DQ44

192

DQ21

144

194

SA0

CKE0

146

DQ45

196

SA1

DM2

148

DM5

198

SA2

DQ22

100

A11

150

200

Back View

Front View

PIN 1

PIN 199

(all odd pins)

PIN 2

PIN 200

(all even pins)

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Table 5:

Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

118, 119, 120

WE#, CAS#, RAS#

Input Command Inputs: RAS#, CAS#, and WE# (along with S#)

define the command being entered.

35, 37, 158, 160

CK0, CK0#,
CK1, CK1#,

Input Clock: CK, CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.

95, 96

CKE0, CKE1

Input Clock Enable: CKE HIGH activates and CKE LOW deactivates

the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH
entry. CKE is asynchronous for SELF REFRESH exit and for
disabling the outputs. CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding
CK, CK# and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after V

is applied and until CKE is first brought HIGH. After

CKE is brought HIGH, it becomes an SSTL_2 input only.

121, 122

S0#, S1#

Input Chip Selects: S# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.

116, 117

BA0, BA1

Input Bank Address: BA0 and BA1 define to which device bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.

(256MB, 512MB)

, 100,

101, 102, 105, 106, 107,
108, 109, 110, 111, 112,

115

A0-A11

(128MB)

A0-A12

(256MB, 512MB)

Input Address Inputs: Provide the row address for ACTIVE

commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.

11, 25, 47, 61, 133, 147,

169, 183

DQS0-DQS7

Input/

Output

Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.

12, 26, 48, 62, 134, 148,

170, 184

DM0-DM7

Input Data Write Mask. DM LOW allows WRITE operation. DM HIGH

blocks WRITE operation. DM lines do not affect READ
operation.

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

5, 6, 7, 8, 13, 14, 17, 18,

19, 20, 23, 20, 29, 30, 31,
32, 41, 42, 43, 44, 49, 50,
53, 54, 55, 56, 59, 60, 65,
66, 67, 67, 127, 128, 129,

130, 135, 136, 139, 140,
141, 142, 145, 146, 151,
152, 153, 154, 163, 164,
165, 166, 171, 172, 175,
176, 177, 178, 181, 182,

187, 188, 189, 190

DQ0-DQ63

Input/

Output

Data I/Os: Data bus.

195

SCL

Input Serial Clock for Presence-Detect: SCL is used to synchronize

the presence-detect data transfer to and from the module.

194, 196, 198

SA0-SA2

Input Presence-Detect Address Inputs: These pins are used to

configure the presence-detect device.

193

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.

1, 2

REF

Input SSTL_2 reference voltage.

9, 10, 21, 22, 33, 34, 36,

45, 46, 57, 58, 69, 70, 81,

82, 92, 93, 94, 113, 114,
131, 132, 143, 144, 155,
156, 157, 167, 168, 179,

180, 191, 192

Supply Power Supply: +2.5V ±0.2V.

See note 50 on page 23.

3, 4, 15, 16, 27, 28, 38, 39,

40, 51, 52, 63, 64, 75, 76,
87, 88, 90, 103, 104, 125,

126, 137, 138, 149, 150,
159, 161, 162, 173, 174,

185, 186

Supply Ground.

197

DDSPD

Supply Serial EEPROM positive power supply: +2.3V to +3.6V.

71, 72, 73, 74, 77, 78, 79,

80, 83, 84

DNU

Do Not Use: These pins are not connected on these modules,
but are assigned pins on other modules in this product family.

85, 97, 98,

99 (128MB only), 123,

124, 199, 200

No Connect: These pins should be left unconnected.

Table 5:

Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Figure 3: Functional Block Diagram

CS#

S0#

CS#

S1#

CS#

BA0-BA1

A0-A11(128MB)

RAS#

CAS#

WE#

CKE0

DDR SDRAMs

CK0

CK1

DDR SDRAMs
U1, U2, U5, U6

DDR SDRAMs
U3, U4, U7, U8

CK1#

CK0#

DDR SDRAMs

DDR SDRAMs U1-U4

SA0

SERIAL PD

SDA

SA1

SA2

SCL

REF

DDSPD

A0-A12(256MB, 512MB)

DDR SDRAMs

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

LDQS
LDM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

LDQS
LDM

UDQS
UDM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS0
DM0

DQS1
DM1

DQS2
DM2

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

UDQS
UDM

CS#

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

LDQS
LDM

DQS3
DM3

LDQS
LDM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

UDQS
UDM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4
DM4

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5
DM5

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS6
DM6

DQS7
DM7

CKE1

DDR SDRAMs U5-U8

120

3pF

120

3pF

DDR SDRAMs

SPD

CS#

UDQS
UDM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

LDQS
LDM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

LDQS
LDM

UDQS
UDM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

CS#

UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

LDQS
LDM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

LDQS
LDM

UDQS
UDM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

NOTE:

1. Unless otherwise stated, all resistors are 22

2. Per industry standard, Micron utilizes various component speed grades as

referenced in the Module Part Numbering Guide at

www.micron.com/num-

berguide

DDR SDRAMs = MT46V8M16TG for 128MB modules
DDR SDRAMs = MT46V16M16TG for 256MB modules
DDR SDRAMs = MT46V32M16TG for 512MB modules

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

General Description

The MT8VDDT1664HD, MT8VDDT3264HD, and

MT8VDDT6464HD, are high-speed CMOS, dynamic
random-access, 128MB, 256MB, and 512MB memory
modules organized in x64 configuration. DDR SDRAM
modules use internally configured quad-bank DDR
SDRAMs.

DDR SDRAM modules use a double data rate archi-

tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effec-
tively consists of a single 2n-bit wide, one-clock-cycle
data transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.

DDR SDRAM modules operate from differential

clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.

Read and write accesses to DDR SDRAM modules

are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select device bank; A0A11 select
device row for 128MB module, A0A12 select device
row for 256MB and 512MB modules). The address bits
registered coincident with the READ or WRITE com-
mand are used to select the device bank and the start-
ing device column location for the burst access.

DDR SDRAM modules provide for programmable

READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, and 512Mb DDR SDRAM compo-
nent data sheets.

Serial Presence-Detect Operation

DDR SDRAM modules incorporate serial presence-

detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I

C bus

using the DIMM's SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 4, Mode Register Definition Diagram, on page 8.
The mode register is programmed via the MODE REG-
ISTER SET command (with BA0 = 0 and BA1 = 0) and
will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.

Mode register bits A0A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-
leaved), A4A6 specify the CAS latency, and A7A11

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

(128MB) or A7A12 (256MB, 512MB) specify the oper-
ating mode.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-
mable, as shown in Figure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1Ai when the burst length is set to two,
by A2Ai when the burst length is set to four and by
A3Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see Note 5 for Figure 6, Burst Definition
Table, on page 9). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Figure 6, Burst
Definition Table, on page 9.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS
Latency Diagram.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 9 indicates the oper-
ating frequencies at which each CAS latency setting
can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Figure 4: Mode Register Definition

Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA1 and BA0)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

M10

M12 M11

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA1and BA0)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

128MB Module Address Bus

256MB and 512MB Module Address Bus

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

NOTE:

1. For a burst length of two, A1

Ai select the two-data-

element block; A0 selects the first access within the
block.

2. For a burst length of four, A2

Ai select the four-data-

element block; A0

A1 select the first access within the

block.

3. For a burst length of eight, A3

Ai select the eight-data-

element block; A0

A2 select the first access within the

block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps
within the block.

5. i = 8 for 128MB and 256MB;

i = 9 for 512MB.

Figure 5: CAS Latency Diagram

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7A11 (for
128MB), or A7A12 (256MB, 512MB) each set to zero,
and bits A0A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command
with bits A7 and A9A11 (128MB), or A7 and A9A12
(256MB, 512MB) each set to zero, bit A8 set to one, and
bits A0A6 set to the desired values. Although not
required by the Micron device, JEDEC specifications
recommend when a LOAD MODE REGISTER com-
mand is issued to reset the DLL, it should always be
followed by a LOAD MODE REGISTER command to
select normal operating mode.

All other combinations of values for A7A11, or A7

A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram, on page 10. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and

Table 6:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Table 7:

CAS Latency (CL) Table

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

SPEED

CL = 2

CL = 2.5

-335

£ f £ 133

£ f £ 166

-262

£ f £ 133

£ f £133

-26A

£ f £ 133

£ f £133

-265

£ f £ 100

£ f £ 133

-202

£ f £ 100

£ f £ 125

CK#

COMMAND

DQS

CL = 2

READ

NOP

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T2n

T3n

T2n

T3n

DON'T CARE

TRANSITIONING DATA

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.

Output Drive Strength

The normal full drive strength for all outputs is

specified to be SSTL2, Class II. The x16 DDR SDRAM
devices used in these modules support an option for
reduced drive. The reduced drive option is intended
for lighter load and point-to-point environments. For
detailed information on output drive strength options,
refer to 128Mb, 256Mb, and 512Mb DDR SDRAM com-
ponent data sheets.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.

Figure 6: Extended Mode Register

Definition Diagram

NOTE:

1. BA1 and BA0 (E13 and E12 for 128MB or E14 and E13

for 256MB and 512MB) must be "0, 1" to select the
Extended Mode Register (vs. the base Mode Register).

2. The QFC# option is not supported.

Operating Mode

Normal Operation

All other states reserved

Valid

DLL

Enable

Disable

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Drive Strength

Normal

Reduced

E1,

Operating Mode

A10

A11

BA1 BA0

E6 E5

E10

E11

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Operating Mode

A10

A11

A12

BA1 BA0

128MB Module

256MB and 512MB Modules

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Commands

The Truth Tables below provides a general reference

of available commands. For a more detailed descrip-

tion of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data sheet.

NOTE:

1. DESELECT and NOP are functionally interchangeable.
2. BA0BA1 provide device bank address and A0A11 (128MB) or A0A12 (256MB, 512MB ) provide row address.
3. BA0BA1 provide device bank address; A0A8 (128MB, 256MB) or A0A9 (512MB), provide column address; A10 HIGH

enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

5. A10 LOW: BA0BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-

BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. BA0BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;

BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0BA1 are reserved). A0A11 (128MB) or A0
A12 (256MB, 512MB) provide the op-code to be written to the selected mode register.

Table 8:

Commands Truth Table

CKE is HIGH for all commands shown except SELF REFRESH

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDR

NOTES

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

Bank/Col

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

Table 9:

DM Operation Truth Table

Used to mask write data; provided coincident with the corresponding data

NAME (FUNCTION)

DQS

WRITE Enable

Valid

WRITE Inhibit

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Voltage on V

Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on V

Q Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on V

REF

and Inputs

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on I/O Pins

Relative to V

. . . . . . . . . . . . . -0.5V to V

Q +0.5V

Operating Temperature,

(ambient) . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C

Storage Temperature (plastic) . . . . . . -55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8W
Short Circuit Output Current. . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 15, 14, 50; notes appear on pages 2023; 0°C

£ T

£ +70°C

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.3

2.7

32, 37

I/O Supply Voltage

2.3

2.7

32, 37, 40

I/O Reference Voltage

REF

0.49

0.51

6, 40

I/O Termination Voltage (system)

REF

- 0.04 V

REF

+ 0.04

7, 40

Input High (Logic 1) Voltage

(

)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(

)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT
Any input 0V

£ V

, Vref pin 0V

£ V

£ 1.35V

(All other pins not under test = 0V)

Command/
Address, RAS#,
CAS#, WE#

-16

µA

CK, CK#, CKE

-8

µA

-4

µA

OUTPUT LEAKAGE CURRENT
(DQ pins are disabled; 0V

£ V

OUT

£ V

DQ, DQS

-10

µA

OUTPUT LEVELS
High Current (V

OUT

= V

Q-0.373V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

-16.8

33, 35

16.8

OUTPUT LEVELS: Reduced drive option
High Current (V

OUT

= V

Q -0.763V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.763V, maximum V

REF

,maximum V

)

OHR

-9

34, 35

OLR

Table 11: AC Input Operating Conditions

Notes: 15, 14, 50; notes appear on pages 2023; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.310

12, 25, 36

Input Low (Logic 0) Voltage

(

)

REF

- 0.310

12, 25, 36

I/O Reference Voltage

REF

(

)

0.49

´ V

0.51

´ V

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Table 12: I

Specifications and Conditions 128MB Module

DDR SDRAM component values only
Notes: 15, 8, 10, 12, 50; notes appear on pages 2023; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYM

-335

-262

-26A/

-265

-202

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs
changing once every two clock cycles

DD0

512

452

432

20, 44

OPERATING CURRENT: One device bank; Active-Read Precharge;
Burst = 2;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA; Address

and control inputs changing once per clock cycle

DD1

552

492

20, 44

PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;

CK =

CK (MIN); CKE = (LOW)

DD2P

21, 28, 46

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

180

160

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3P

100

21, 28, 46

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ,

DM andDQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle

DD3N

200

180

20, 43

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

572

532

512

20, 44

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

DD4W

572

512

492

AUTO REFRESH CURRENT

RC =

RC (MIN)

DD5

1,060

880

20, 46

RC = 15.625µs

DD5A

24, 46

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

OPERATING CURRENT: Four device bank interleaving READs (BL
= 4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN);

Address and control inputs change only during Active READ or
WRITE commands

DD7

1,432

1,332

1,312

20, 45

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

2p (CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Table 13: I

Specifications and Conditions 256MB Module

DDR SDRAM component values only
Notes: 15, 8, 10, 12, 50; notes appear on pages 2023; 0°C

£ T

£ +70°C; V

, V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYM

-335

-262

-26A/

-265

-202

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs
changing once every two clock cycles

DD0

516

436

495

20, 44

OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

0mA; Address and control inputs changing once per clock cycle

DD1

696

656

596

636

20, 44

PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;

CK =

CK (MIN); CKE = (LOW)

DD2P

21, 28, 46

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK =

CK (MIN); CKE = HIGH; Address and other control inputs

changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

400

360

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3P

240

200

240

21, 28, 46

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge;

RC =

RAS (MAX);

CK =

(MIN); DQ, DM andDQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle

DD3N

480

400

20, 43

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

716

616

716

20, 44

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

DD4W

636

556

776

AUTO REFRESH CURRENT

RC =

RC (MIN)

DD5

2,040

1,880

1,960

20, 46

RC = 7.8125µs

DD5A

24, 46

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

OPERATING CURRENT: Four device bank interleaving READs (BL
= 4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN);

Address and control inputs change only during Active READ or
WRITE commands

DD7

1,636

1,416

1,476

20, 45

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

2p (CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Table 14: I

Specifications and Conditions 512MB Module

DDR SDRAM component values only
Notes: 15, 8, 10, 12, 50; notes appear on pages 2023; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYM

-335

-262

-26A/

-265

-202

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs
changing once every two clock cycles

DD0

540

480

20, 44

OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

0mA; Address and control inputs changing once per clock cycle

DD1

660

600

20, 44

PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;

CK =

CK (MIN); CKE = (LOW)

DD2P

21, 28, 46

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK =

CK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

360

320

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3P

280

240

21, 28, 46

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge;

RC =

RAS (MAX);

CK =

(MIN); DQ, DM andDQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle

DD3N

360

320

20, 43

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

680

600

20, 44

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

DD4W

640

560

AUTO REFRESH CURRENT

RC =

RC (MIN)

DD5

2,320

2,240

20, 46

RC = 7.8125µs

DD5A6

24, 46

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

OPERATING CURRENT: Four device bank interleaving READs (BL
= 4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN);

Address and control inputs change only during Active READ or
WRITE commands

DD7

1,640

1,620

1,420

20, 45

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

2p (CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Table 15: Capacitance

Note: 11; notes appear on pages 2023

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input/Output Capacitance: DQ, DQS, DM

Input Capacitance: Command and Address

Input Capacitance: S#, CKE

Input Capacitance: CK, CK#

Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-335, -262)

Notes: 15, 1215, 29, 50; notes appear on pages 2023; 0°C

£ T

£ +70°C; V

, V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-335

-262

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.7

+0.75

-0.75

+0.75

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

7.5

41, 48

CL=2

7.5

41, 48

DQ and DM input hold time relative to DQS

0.45

0.5

23, 27

DQ and DM input setup time relative to DQS

0.45

0.5

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.60

+0.60

-0.75

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per
access

DQSQ

0.45

0.5

22, 23

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.70

+0.75

16, 38

Data-out low-impedance window from CK/CK#

-0.70

-0.75

16, 39

Address and control input hold time (fast slew rate)

0.75

0.90

Address and control input setup time (fast slew rate)

0.75

0.90

Address and control input hold time (slow slew rate)

0.80

Address and control input setup time (slow slew rate)

0.80

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

HP -

QHS

HP -

QHS

22, 23

Data hold skew factor

QHS

0.55

0.75

ACTIVE to PRECHARGE command

RAS

70,000

120,000

ACTIVE to READ with Auto precharge
command

128MB

RAP

256MB/ 512MB

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command
delay

WTR

Data valid output window

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval 128MB

REFC

140.6

µs

256MB/ 512MB

70.3

µs

Average periodic refresh interval

128MB

REFI

15.6

µs

256MB/ 512MB

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-335, -262) (Continued)

Notes: 15, 1215, 29, 50; notes appear on pages 2023; 0°C

£ T

£ +70°C; V

, V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-335

-262

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-26A, -265, and -202)

Notes: 15, 1215, 29, 50; notes appear on pages 2023; 0°C

£ T

£ +70°C; V

, V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-26A/-265

-202

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.75

+0.75

-0.8

+0.8

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

7.5

41, 48

CL=2

7.5/10

41, 48

DQ and DM input hold time relative to DQS

0.5

0.6

23, 27

DQ and DM input setup time relative to DQS

0.5

0.6

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.75

+0.75

-0.8

+0.8

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per
access

DQSQ

0.5

0.6

22, 23

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.75

+0.8

16, 38

Data-out low-impedance window from CK/CK#

-0.75

-0.8

16, 39

Address and control input hold time (fast slew rate)

0.90

1.1

Address and control input setup time (fast slew rate)

0.90

1.1

Address and control input hold time (slow slew rate)

1.1

Address and control input setup time (slow slew rate)

1.1

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

HP -

QHS

HP -

QHS

22, 23

Data hold skew factor

QHS

0.75

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to READ with Auto precharge
command

128MB

RAP

RAS(MIN) - (burst length *

CK/2)

256MB/ 512MB

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command
delay

WTR

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

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Data valid output window

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval 128MB

REFC

140.6

µs

256MB/ 512MB

70.3

µs

Average periodic refresh interval

128MB

REFI

15.6

µs

256MB/ 512MB

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-26A, -265, and -202) (Continued)

Notes: 15, 1215, 29, 50; notes appear on pages 2023; 0°C

£ T

£ +70°C; V

, V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-26A/-265

-202

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Notes

1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical AC and DC

characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test environment, but
input timing is still referenced to V

REF

(or to the

crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V

(ACV)

and V

(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal V

Q/2 of the transmit-

ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V

REF

may not exceed ±2 percent of the

DC value. Thus, from V

Q/2, V

REF

is allowed

±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V

REF

by-pass capacitor.

7. V

is not applied directly to the device. V

is a

system supply for signal termination resistors, is
expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

8. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -262, -26A, and -202,
CL = 2.5 for-335 and -265 with the outputs open.

9. Enables on-chip refresh and address counters.

10. I

specifications are tested after the device is

properly initialized, and is averaged at the defined
cycle rate.

11. This parameter is sampled. V

= +2.5V ±0.2V,

Q = +2.5V ±0.2V, V

REF

= V

, f = 100 MHz, T

25°C, V

OUT

(DC) = V

Q/2, V

OUT

(peak to peak) =

0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.

12. Command/Address input slew rate = 0.5V/ns. For -

335, -262, -26A, and -265 with slew rates 1V/ns and
faster,

IS and

IH are reduced to 900ps. If the slew

rate is less than 0.5V/ ns, timing must be derated:

IS has an additional 50ps per each 100mV/ns

reduction in slew rate from the 500mV/ns, while

IH remains constant. If the slew rate exceeds

4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V

REF

14. Inputs are not recognized as valid until V

REF

stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE

£ 0.3 x V

Q is recognized as LOW.

15. The output timing reference level, as measured at the

timing reference point indicated in Note 3, is V

16.

HZ and

LZ transitions occur in the same access

time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).

17. If DQS transitions to HIGH above V

(DC) MIN,

then it must not transition to LOW below V

(DC)

MIN prior to

DQSH (MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on

DQSS.

20. MIN (

RC or

RFC) for I

measurements is the

smallest multiple of

CK that meets the minimum

absolute value for the respective parameter.

RAS

(MAX) for I

measurements is the largest multi-

ple of

CK that meets the maximum absolute

value for

RAS.

21. The refresh period 64ms. This equates to an aver-

age refresh rate of 15.625µs (128MB) or 7.8125µs
(256MB, 512MB). However, an AUTO REFRESH
command must be asserted at least once every
140.6µs (128MB modules) or 70.3µs (256MB and
512MB modules); burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.

Output
(V

OUT

)

Reference

Point

30pF

128MB, 256MB, 512MB (x64)

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DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

22. The valid data window is derived by achieving

other specifications:

HP (

CK/2),

DQSQ, and

(

QH =

HP -

QHS). The data valid window derates

directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio. Figure 7, Derating
Data Valid Window (

QH -

DQSQ), shows the der-

ating curves for duty cycles ranging between 50/
50 and 45/55.

23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during
REFRESH command period (

RFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:
a. Sustain a constant slew rate from the current

AC level through to the target AC level, V

(AC)

or V

(AC).

b. Reach at least the target AC level.
c. After the AC target level is reached, continue to

maintain at least the target DC level, V

(DC)

or V

(DC).

26. JEDEC specifies CK and CK# input slew rate must

1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to

DS and

DH for each 100mv/ns reduction in slew rate. If

slew rate exceeds 4V/ns, functionality is uncertain.

28. V

must not vary more than 4 percent if CKE is

not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same
amount.

30.

HP min is the lesser of

CL minimum and

minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.

Figure 7: Derating Data Valid Window

(

QH -

DQSQ)

3.750

3.700

3.650

3.600

3.550

3.500

3.450

3.400

3.350

3.300

3.250

3.400

3.350

3.300

3.250

3.200

3.150

3.100

3.050

3.000

2.950

2.900

2.500

2.463

2.425

2.388

2.350

2.313

2.275

2.238

2.200

2.163

2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50

49.5/50.5 49/51

48.5/52.5

48/52

47.5/53.5

47/53

46.5/54.5

46/54

45.5/55.5

45/55

Clock Duty Cycle

-335 @

CK = 6ns

-262/-26A/-265 @

CK = 10ns

-202 @

CK = 10ns

-262/-26A/-265 @

CK = 7.5ns

-202 @

CK = 8ns

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

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DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

31. READs and WRITEs with auto precharge are not

allowed to be issued until

RAS(MIN) can be satis-

fied prior to the internal precharge command
being issued.

32. Any positive glitch in the nominal voltage must be

less than 1/3 of the clock and not more than
+400mV or 2.9V maximum, whichever is less. Any
negative glitch must be less than 1/3 of the clock
cycle and not exceed either -300mV or 2.2V mini-
mum, whichever is more positive.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Down Characteristics.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I curve
of Figure 8, Pull-Down Characteristics.

c. The full variation in driver pull-up current from

minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure 9, Pull-Up Char-
acteristics.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
9, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.

34. Reduced Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, tempera-
ture and voltage will lie within the outer bound-
ing lines of the V-I curve of Figure 10, Reduced-
Drive Pull-Down Characteristics, on page 23.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I curve
of Figure 10, Reduced-Drive Pull-Down Char-
acteristics, on page 23.

c. The full variation in driver pull-up current from

minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure 11, Reduced-
Drive Pull-Up Characteristics, on page 23.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 11, Reduced-Drive Pull-Up Characteris-
tics, on page 23.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.

Figure 8: Pull-Down Characteristics

Figure 9: Pull-Up Characteristics

160

140

OUT

(mA)

OUT

(V)

Nominal low

Minimum

Nominal high

Maximum

120

100

0.0

0.5

1.0

1.5

2.0

2.5

OUT

(V)

-20

OUT

(mA)

Nominal low

Minimum

Nominal high

Maximum

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0

0.5

1.0

1.5

2.0

2.5

Q - V

OUT

(V)

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200-PIN DDR SODIMM

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DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

35. The voltage levels used are derived from a mini-

mum V

level and the referenced test load. In

practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.

36. V

overshoot: V

(MAX) = V

Q + 1.5V for a

pulse width

£ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. V

undershoot:

(MIN) = -1.5V for a pulse width

£ 3ns and the

pulse width can not be greater than 1/3 of the
cycle rate.

37. V

and V

Q must track each other.

38. This maximum value is derived from the refer-

enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for

HZ(MAX) and the last DVW.

(MAX) will prevail over

DQSCK (MAX) +

RPST

(MAX) condition.

LZ (MIN) will prevail over

DQSCK (MIN) +

RPRE (MAX) condition.

39. For slew rates greater than 1V/ns the (LZ) transi-

tion will start about 310ps earlier.

40. During initialization, V

Q, V

, and V

REF

must

be equal to or less than V

+ 0.3V. Alternatively,

may be 1.35V maximum during power up,

even if V

Q are 0V, provided a minimum of

W of series resistance is used between the V

supply and the input pin.

41. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.

42.

RAP

RCD. Does not apply to -335 speed grade.

43. For the -335, -262, -26A, and -265, I

is speci-

fied to be 35mA at 100 MHz.

44. Random addressing changing and 50 percent of

data changing at every transfer.

45. Random addressing changing and 100 percent of

data changing at every transfer.

46. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until

REF later.

47. I

2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. I

similar to I

except I

specifies the

address and control inputs to remain stable.
Although I

, I

, and I

are similar,

is "worst case."

48. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).

49. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

50. The -335 module speed grade, using the -6R speed

device, has V

(MIN) = 2.4V.

Figure 10: Reduced-Drive Pull-Down

Characteristics

Figure 11: Reduced-Drive Pull-Up

Characteristics

0.0

0.5

1.0

1.5

2.0

2.5

OUT

(V)

OUT

(mA)

Nominal low

Minimum

Nominal high

Maximum

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Q - V

OUT

(V)

OUT

(mA)

Nominal low

Minimum

Nominal high

Maximum

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

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DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shwon in Figure 12, Data Validity, and Figure 13, Defi-
nition of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 14, Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 12: Data Validity

Figure 13: Definition of Start and Stop

Figure 14: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Figure 15: SPD EEPROM Timing Diagram

Table 18: EEPROM Device Select Code

The most significant bit (b7) is sent first

SELECT CODE

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 19: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

or V

START, Device Select, RW = `1'

Random Address Read

or V

START, Device Select, RW = `0', Address

or V

reSTART, Device Select, RW = `1'

Sequential Read

or V

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = `0'

Page Write

£ 16

START, Device Select, RW = `0'

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

NOTE:

1. The SPD EEPROM WRITE cycle time (

WRC) is the time from a valid stop condition of a write sequence to the end of the

EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 20: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +2.3V to +3.6V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

DDSPD

2.3

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

DDSPD

´ 0.7 V

DDSPD

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

DDSPD

´ 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

µA

STANDBY CURRENT: SCL = SDA = V

- 0.3V; All other inputs = V

or V

µA

POWER SUPPLY CURRENT:

SCL clock frequency = 100 KHz

Table 21: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +2.3V to +3.6V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.3

3.5

µs

Time the bus must be free before a new transition can start

BUF

4.7

µs

Data-out hold time

300

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

µs

Clock HIGH period

HIGH

µs

Noise suppression time constant at SCL, SDA inputs

100

Clock LOW period

LOW

4.7

µs

SDA and SCL rise time

µs

SCL clock frequency

SCL

100

KHz

Data-in setup time

SU:DAT

250

Start condition setup time

SU:STA

4.7

µs

Stop condition setup time

SU:STO

4.7

µs

WRITE cycle time

WRC

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Table 22: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29

BYTE

DESCRIPTION

ENTRY (VERSION) MT8VDDT1664HD MT8VDDT3264HD MT8VDDT6464HD

Number of Bytes Used by Micron

128

Total Number of SPD Memory Bytes

256

Memory Type

DDR SDRAM

Number of Row Addresses

12,13

Number of Column Addresses

9,10

Number of Module Ranks

Module Data Width

Module Data Width (Continued)

Module Voltage Interface Levels

SSTL 2.5V

SDRAM Cycle Time,

CK, CAS Latency

= 2.5, (See note 1)

6ns(-335)

7ns (-262/-26A)

7.5ns (-265)

8ns (-202)

60
70
75
80

SDRAM Access from Clock,

AC, CAS

Latency = 2.5

0.7ns (-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

70
75
80

Module Configuration Type

None

Refresh Rate/Type

15.62µs, 7.8µs/SELF

SDRAM Width (Primary SDRAM)

Error-checking SDRAM Data Width

None

Minimum Clock Delay, Back-to-Back
Random Column Access

1 clock

Burst Lengths Supported

2, 4, 8

Number of Banks on SDRAM
Device

CAS Latencies Supported

2, 2.5

CS Latency

WE Latency

SDRAM Module Attributes

Unbuffered/Diff.

Clock

SDRAM Device Attributes: General

Fast/Concurrent AP

SDRAM Cycle Time,

CK,CAS

Latency = 2

7.5ns (-335/-262/26A)

10ns (-265/-202)

SDRAM Access from Clock,

CK,

CAS Latency = 2

0.7ns (-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

70
75
80

SDRAM Cycle Time,

CK, CAS

Latency = 1

N/A

SDRAM Access From CK ,

AC, CAS

Latency = 1

N/A

Minimum Row Precharge Time,

18ns (-335)
15ns (-262)

20ns (-26A/-265/-202)

48
3C
50

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

Minimum Row Active to Row

Active,

RRD

12ns (-335)

15ns (-262/-26A/-265/-202)

30
3C

Minimum RAS# to CAS# Delay,

RCD

18ns (-335)

15ns (-262)

20ns (-26A/-265/-202)

48
3C
50

Minimum RAS# Pulse Width,

RAS

(See note 2)

42ns (-335)

45ns (-262/-26A/-265)

40ns (-202)

2A
2D

Module Rank Density

64MB, 128MB,

256MB

Address and Command Setup Time,

IS, (See note 3)

0.8ns (-335)

1.0ns (-262/-26A/-265)

1.1ns (-202)

Address and Command Hold Time,

IH, (See note 3)

0.8ns (-335)

1.0ns (-262/-26A/-265)

1.1ns (-202)

Data/Data Mask Input Setup Time,

0.45ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

45
50
60

Data/Data Mask Input Hold Time,

0.45ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

45
50
60

36-40 Reserved

Minimum Active/Auto Refresh

Time,

60ns (-335/-262)

65ns (-26A/-265)

70ns (-202)

3C
41
46

41
46

Minimum Auto Refresh to Active/
Auto Refresh Command Period,

RFC

72ns (-335)

75ns (-262/-26A/-265)

80ns (-202)

48
4B
50

SDRAM Device Maximum Cycle

Time,

CK (MAX)

12ns (-335)

13ns (-262/-26A/265/202)

30
34

SDRAM Device Maximum DQS-DQ

Skew Time,

DQSQ

0.45ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

32
3C

Maximum Read Data Hold Skew

Factor,

QHS

0.55ns (-335)

0.75ns (-262/-26A/-265)

1.0ns (-202)

55
75

Reserved

DIMM Height

4861 Reserved

SPD Revision

Release 1.0

Checksum for Bytes 0-62

-335
-262

-26A

-265
-202

FD
D0
FD
2D

A3
D0

00
9B

F1
21

Manufacturer's JEDEC ID Code

MICRON

65-71 Manufacturer's JEDEC ID Code

(Continued)

Table 22: Serial Presence-Detect Matrix (Continued)

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29

BYTE

DESCRIPTION

ENTRY (VERSION) MT8VDDT1664HD MT8VDDT3264HD MT8VDDT6464HD

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

NOTE:

1. Value for -262 and -26A

CK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

2. The value of

RAS used for -262/-26A/-265 modules is calculated from

RC -

RP. Actual device spec. value is 40 ns.

3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.

Manufacturing Location

0111

01B0

73-90 Module Part Number (ASCII)

Variable Data

PCB Identification Code

1-9

01-09

Identification Code (Continued)

Year of Manufacture in BCD

Variable Data

Week of Manufacture in BCD

Variable Data

95-98 Module Serial Number

Variable Data

99-

127

Manufacturer-Specific Data (RSVD)

Table 22: Serial Presence-Detect Matrix (Continued)

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29

BYTE

DESCRIPTION

ENTRY (VERSION) MT8VDDT1664HD MT8VDDT3264HD MT8VDDT6464HD

128MB, 256MB, 512MB (x64)

200-PIN DDR SODIMM

09005aef806e1d28

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 16: 200-Pin DDR SODIMM Dimensions

NOTE:

All dimensions are in inches (millimeters)

or typical where noted.

Data Sheet Designation

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete
power supply and temperature range for production

devices. Although considered final, these specifications
are subject to change, as further product development
and data characterization sometimes occur.

0.150 (3.80)

MAX

PIN 1

2.666 (67.72)
2.656 (67.45)

0.787 (20.00)

TYP

0.071 (1.80)

(2X)

0.024 (0.61)

TYP

0.018 (0.46)

TYP

0.079 (2.00) R

(2X)

PIN 199

PIN 200

PIN 2

FRONT VIEW

0.079 (2.00)

0.236 (6.00)

2.504 (63.60)

0.096 (2.44)

0.039 (.99)

TYP

1.255 (31.88)
1.245 (31.62)

BACK VIEW

0.043 (1.10)
0.035 (0.90)

TYP

0.45 (11.40)

TYP

1.87 (47.40)

TYP

MAX

MIN

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