PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

09005aef806e057b
DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

DDR SDRAM
SMALL-OUTLINE DIMM

MT9VDDT1672H 128MB, MT9VDDT3272H 256MB,
MT18VDDS6472H 512MB, MT9VDDT6472H
512MB, MT18VDDS12872H 1GB (ADVANCE

)

For the latest data sheet, please refer to the Micron

Web

site:

www.micron.com/moduleds

Features

· 200-pin, small-outline, dual in-line memory

module (SODIMM)

· ECC, 1-bit error detection and correction
· Fast data transfer rates: PC1600, PC2100, or PC2700
· Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM

components or TwinDie

Ô DDR SDRAM components

· MT9VDDT1672H (16 Meg x 72), MT9VDDT3272H (32 Meg

x 72), MT18VDDS6472H and MT9VDDT6472H (64
Meg x 72), and MT18VDDS12872H (128 Meg x 72)

· V

= V

Q = +2.5V

· V

DDSPD

= +2.3V to +3.6V

· 2.5V I/O (SSTL_2 compatible)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

NOTE:

1. CL = Device CAS (READ) Latency.

2. -335 and -262 speed grades available in single-

rank module only.

3. Consult Micron for availability; industrial tem-

perature option available in -265 speed only.

Figure 1: 200-Pin SODIMM (MO-224)

· Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

· Bidirectional data strobe (DQS) transmitted/received

with data--i.e., source-synchronous data capture

· Differential clock inputs CK and CK#
· Four internal device banks for concurrent operation
· Programmable burst lengths: 2, 4, or 8
· Auto precharge option
· Auto Refresh and Self Refresh Modes
· 15.625µs (MT9VDDT1672H), 7.8125µs

(MT9VDDT3272H, MT18VDDS6472H,
MT9VDDT6472H, and MT18VDDS12872H)
maximum average periodic refresh interval

· Serial Presence Detect (SPD) with EEPROM
· Programmable READ CAS latency
· Gold edge contacts

OPTIONS

MARKING

· Operating Temperature Range

Commercial (0°C

£ T

£ +70°C)

None

Industrial (-40°C

£ T

£ +85°C)

· Package

200-pin SODIMM (standard)

200-pin SODIMM (lead-free)

· Frequency/CAS Latency

6.0ns (167 MHz) 333 MT/s CL = 2.5

-335

7.5ns (133 MHz) 266 MT/s CL = 2

-262

7.5ns (133 MHz) 266 MT/s CL = 2

-26A

7.5ns (133 MHz) 266 MT/s CL = 2.5

-265

10ns (100 MHz) 200 MT/s CL = 2

-202

· PCB

Standard 1.5in. (38.10mm)

See page 2 note

Low Profile 1.25in. (31.75mm)

See page 2 note

Standard 1.5in. (38.10mm)

Low Profile 1.25in. (31.75mm)

Table 1:

Address Table

MT9VDDT1672H

MT9VDDT3272H

MT18VDDS6472H

MT9VDDT6472H

MT18VDDS12872H

Refresh Count

Row Addressing

4K (A0A11)

8K (A0A12)

Device Bank Addressing

4 (BA0, BA1)

Device Configuration

16 Meg x 8

32 Meg x 8

64 Meg x 8

Column Addressing

1K (A0A9)

2K (A0A9, A11)

Module Rank Addressing

1 (S0#)

2 (S0#, S1#)

1 (S0#)

2 (S0#, S1#)

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT9VDDT3272HG-265A1.

Table 2:

Part Numbers and Timing Parameters

PART NUMBER

MODULE
DENSITY

CONFIGURATION

MODULE

BANDWIDTH

MEMORY CLOCK/

DATA BIT RATE

LATENCY

(CL -

RCD -

RP)

MT9VDDT1672H(I)G-335__

128MB

16 Meg x 72

2.7 GB/s

6.0ns/333 MT/s

2.5-3-3

MT9VDDT1672H(I)Y-335__

128MB

16 Meg x 72

2.7 GB/s

6.0ns/333 MT/s

2.5-3-3

MT9VDDT1672H(I)G-262__

128MB

16 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT9VDDT1672H(I)Y-262__

128MB

16 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT9VDDT1672H(I)G-26A__

128MB

16 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT9VDDT1672H(I)Y-26A__

128MB

16 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT9VDDT1672H(I)G-265__

128MB

16 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT9VDDT1672H(I)Y-265__

128MB

16 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT9VDDT1672H(I)G-202__

128MB

16 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT9VDDT1672H(I)Y-202__

128MB

16 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT9VDDT3272H(I)G-335__

256MB

32 Meg x 72

2.7 GB/s

6.0ns/333 MT/s

2.5-3-3

MT9VDDT3272H(I)Y-335__

256MB

32 Meg x 72

2.7 GB/s

6.0ns/333 MT/s

2.5-3-3

MT9VDDT3272H(I)G-262__

256MB

32 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT9VDDT3272H(I)Y-262__

256MB

32 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT9VDDT3272H(I)G-26A__

256MB

32 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT9VDDT3272H(I)Y-26A__

256MB

32 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT9VDDT3272H(I)G-265__

256MB

32 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT9VDDT3272H(I)Y-265__

256MB

32 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT9VDDT3272H(I)G-202__

256MB

32 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT9VDDT3272H(I)Y-202__

256MB

32 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT18VDDS6472H(I)G-335__

512MB

64 Meg x 72

2.7 GB/s

6.0ns/333 MT/s

2.5-3-3

MT18VDDS6472H(I)Y-335__

512MB

64 Meg x 72

2.7 GB/s

6.0ns/333 MT/s

2.5-3-3

MT18VDDS6472H(I)G-262__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT18VDDS6472H(I)Y-262__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT18VDDS6472H(I)G-26A__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT18VDDS6472H(I)Y-26A__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT18VDDS6472H(I)G-265__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT18VDDS6472H(I)Y-265__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT18VDDS6472H(I)G-202__

512MB

64 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT18VDDS6472H(I)Y-202__

512MB

64 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT9VDDT6472H(I)G-26A__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT9VDDT6472H(I)Y-26A__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT9VDDT6472H(I)G-265__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT9VDDT6472H(I)Y-265__

512MB

64 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT9VDDT6472H(I)G-202__

512MB

64 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT9VDDT6472H(I)Y-202__

512MB

64 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT18VDDS12872H(I)G-26A__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT18VDDS12872H(I)Y-26A__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT18VDDS12872H(I)G-265__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT18VDDS12872H(I)Y-265__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT18VDDS12872H(I)G-202__

1GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT18VDDS12872H(I)Y-202__

1GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

NOTE:

Pin 99 is a No Connect for MT9VDDT1672H modules, or A12 for all other modules.

Figure 2: Module Layout

Table 3:

Pin Assignment
(200-Pin SODIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

REF

101

151

DQ42

DQ19

103

Vss

153

DQ43

DQ0

DQ24

105

155

Vdd

DQ1

107

157

Vdd

DQ25

109

159

DQS0

DQS3

111

161

DQ2

113

163

DQ48

DQ26

115

A10

165

DQ49

DQ3

DQ27

117

BA0

167

DQ8

119

WE#

169

DQS6

CB0

121

S0#

171

DQ50

DQ9

CB1

123

173

DQS1

125

175

DQ51

DQS8

127

DQ32

177

DQ56

DQ10

CB2

129

DQ33

179

DQ11

131

181

DQ57

CB3

133

DQS4

183

DQS7

CK0

135

DQ34

185

CK0#

137

187

DQ58

CK2

139

DQ35

189

DQ59

DQ16

CK2#

141

DQ40

191

DQ17

143

193

SDA

CKE1

145

DQ41

195

SCL

DQS2

147

DQS5

197

DDSPD

DQ18

NC/

A12

149

199

Table 4:

Pin Assignment
(200-pin SODIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

REF

102

152

DQ46

DQ23

104

154

DQ47

DQ4

DQ28

106

156

DQ5

108

158

CK1#

DQ29

110

160

CK1

DM0

DM3

112

162

DQ6

114

164

DQ52

DQ30

116

BA1

166

DQ53

DQ7

DQ31

118

RAS#

168

DQ12

120

CAS#

170

DM6

CB4

122

S1#

172

DQ54

DQ13

CB5

124

174

DM1

126

176

DQ55

DM8

128

DQ36

178

DQ60

DQ14

CB6

130

DQ37

180

DQ15

132

182

DQ61

CB7

134

DM4

184

DM7

136

DQ38

186

138

188

DQ62

140

DQ39

190

DQ63

DQ20

142

DQ44

192

DQ21

144

194

SA0

CKE0

146

DQ45

196

SA1

DM2

148

DM5

198

SA2

DQ22

100

A11

150

200

PIN 1

PIN 199

(all odd pins)

PIN 2

PIN 200

(all even pins)

Back View

Front View

U10

Standard 1.5in. (38.10mm)

Low-Profile 1.25in. (31.75mm)

U10

PIN 1

PIN 199

(all odd pins)

PIN 2

PIN 200

(all even pins)

Front View

Back View

Indicates a V

or V

DDQ

Indicates a V

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 5:

Pin Descriptions

Refer to Pin Assignment Tables on page 3 for pin number and symbol information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

118, 119, 120

WE#, CAS#, RAS#

Input

Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.

35, 37, 89, 91, 158, 160

CK0, CK0#, CK1,

CK1#, CK2, CK2#

Input

Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.

95, 96

CKE0, CKE1

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank).CKE is synchronous for POWER-
DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V

is applied.

121, 122

S0#, S1#

Input

Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.

116, 117

BA0, BA1

Input

Bank Address: BA0, BA1 define to which device bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.

(A12)

, 100, 101, 102,

105, 106, 107, 108, 109,

110, 111, 112, 115

A0A11

MT9VDDT1672H

A0A12

(99)

MT9VDDT3272H,

MT18VDDS6472H,

MT9VDDT6472H,

MT18VDDS12872H

Input

Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode
register or extended mode register) is loaded during the LOAD
MODE REGISTER command.

11, 25, 47, 61, 77, 133,

147, 169, 183

DQS0DQS8

Input/

Output

Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.

12, 26, 48, 62, 78, 134,

148, 170, 184

DM0DM8

Input

Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.

71,72, 73, 74, 79,

80, 83, 84

CB0CB7

Input/

Output

Check Bits: ECC, 1-bit error detection and correction.

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

5-8, 13-20, 23-24, 29-32,

41-44, 49-50, 53-56, 59-

60, 65-68, 127-130, 135-

136, 139-142, 145-146,
151-154, 163-166, 171-
172, 175-178, 181-182,

187-190

DQ0

DQ63

Input/

Output

Data I/Os: Data bus.

195

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.

194, 196, 198

SA0SA2

Input

Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.

193

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.

1, 2

REF

Input

SSTL_2 reference voltage.

9-10, 21-22, 33-34, 36, 45-

46, 57-58, 69-70, 81-82,

92-94, 113-114, 131-132,

143-144, 155-157, 167-

168, 17-180, 191-192

Supply

Power Supply: +2.5V

0.2V.

3-4 15-16, 27-28, 38-40,
51-52, 63-64, 75-76, 87-

88, 90, 103-104, 125-126,

137-138, 149-150, 159,
161-162, 173-174, 185-

186

Supply

Ground.

197

DDSPD

Supply

Serial EEPROM positive power supply: +2.3V to +3.6V.

85, 97, 99 (only for

MT9VDDT1672H), 123,

199, 98, 124, 200

No Connect: These pins should be left unconnected.

Table 5:

Pin Descriptions (Continued)

Refer to Pin Assignment Tables on page 3 for pin number and symbol information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Figure 3: Functional Block Diagram, (Single-Rank, Standard Profile PCB)

SA0

SERIAL PD

SDA

SA1

SA2

BA0, BA1

A0-A11

A0-A12

RAS#

BA0, BA1: DDR SDRAMs

A0-A11: DDR SDRAMs

A0-A12: DDR SDRAMs

RAS#: DDR SDRAMs

CAS#: DDR SDRAMs

CKE0: DDR SDRAMs

WE#: DDR SDRAMs

CAS#

CKE0

WE#

REF

DDR SDRAMs

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

U10

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DM CS# DQS

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DM0

S0#

SCL

DM CS# DQS

DQS0

DM4

DQS4

DM1

DQS1

DM5

DQS5

DM2

DQS2

DM6

DQS6

DM CS# DQS

DM3

DQS3

DM7

DQS7

DM8

DQS8

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

DDSPD

DDR SDRAMs

SPD

CK0
CK0#

120

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

3pF

U1
U9
U10

CK1
CK1#

120

3pF

U4
U5
U6

CK2
CK2#

120

3pF

U2
U3
U7

NOTE:

1. All resistor values are 22

W unless otherwise specified.

2. Per industry standard, Micron modules utilize various component speed

grades, as referenced in the module part numbering guide at

www.micron.com/numberguide

3. MT9VDDT1672H
4. MT9VDDT3272H and MT9VDDT6472H

DDR SDRAMs = MT46V16M8TG for MT9VDDT1672HG
DDR SDRAMs = MT46V32M8TG for MT9VDDT3272HG
DDR SDRAMs = MT46V64M8TG for MT9VDDT6472HG

Contact Micron for availability of IT modules.

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Figure 4: Functional Block Diagram, (Single Rank, Low-Profile PCB)

SA0

SERIAL PD

SDA

SA1

SA2

BA0, BA1

A0-A11

A0-A12

RAS#

BA0, BA1: DDR SDRAMs

A0-A11: DDR SDRAMs

A0-A12: DDR SDRAMs

RAS#: DDR SDRAMs

CAS#: DDR SDRAMs

CKE0: DDR SDRAMs

WE#: DDR SDRAMs

CAS#

CKE0

WE#

REF

DDR SDRAMS

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

U10

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DM CS# DQS

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DM0

S0#

SCL

DM CS# DQS

DQS0

DM4

DQS4

DM1

DQS1

DM5

DQS5

DM2

DQS2

DM6

DQS6

DM CS# DQS

DM3

DQS3

DM7

DQS7

DM8

DQS8

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

DDSPD

DDR SDRAMS

SPD

CK0
CK0#

120

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

U1
U9
U10

CK1
CK1#

120

U5
U6
U7

CK2
CK2#

120

U2
U3
U4

NOTE:

1. All resistor values are 22

W unless otherwise specified.

2. Per industry standard, Micron modules utilize various component speed

grades, as referenced in the module part numbering guide at

www.micron.com/numberguide

3. MT9VDDT1672H
4. MT9VDDT3272H and MT9VDDT6472H

DDR SDRAMs = MT46V16M8TG for MT9VDDT1672HG
DDR SDRAMs = MT46V32M8TG for MT9VDDT3272HG
DDR SDRAMs = MT46V64M8TG for MT9VDDT6472HG

Contact Micron for availability of IT modules.

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Figure 5: Functional Block Diagram, (Dual Rank, Standard Profile PCB)

SA0

SERIAL PD

SDA

SA1

SA2

BA0, BA1

A0-A12

RAS#

BA0, BA1: DDR SDRAMs

A0-A12: DDR SDRAMs

RAS#: DDR SDRAMs

CAS#: DDR SDRAMs

CKE0: DDR SDRAMs U1b-U7b, U9b, U10b

CKE1: DDR SDRAMs U1t-U7t, U9t, U10t

WE#: DDR SDRAMs

CAS#

CKE0

CKE1

WE#

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

U6b

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

U7b

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

U5b

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

U3b

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

U10b

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

U9b

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DM CS# DQS

U1b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DM0

S0#

U2b

SCL

U1t

U9t

U2t

U5t

S1#

DM CS# DQS

DQS0

DM4

DQS4

DM1

DQS1

DM5

DQS5

U7t

DM CS# DQS

DM2

DQS2

DM6

DQS6

DM CS# DQS

U4b

U4t

DM CS# DQS

DM3

DQS3

DM7

DQS7

U10t

DM CS# DQS

U6t

DM CS# DQS

DM8

DQS8

U3t

DM CS# DQS

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

CK0
CK0#

120

3pF

U1t, U1b
U9t, U9b
U10t, U10b

CK1
CK1#

120

3pF

U4t, U4b
U5t, U5b
U6t, U6b

CK2
CK2#

120

3pF

U2t, U2b
U3t, U3b
U7t, U7b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

REF

DDR SDRAMs

DDSPD

DDR SDRAMs

SPD

NOTE:

1. All resistor values are 22

W unless otherwise specified.

2. 'b' = bottom portion of TwinDie SDRAM, 't' = top portion of TwinDie SDRAM.
3. Per industry standard, Micron modules utilize various component speed

grades, as referenced in the module part numbering guide at

www.micron.com/numberguide

DDR SDRAMs = MT46V64M8S2 for MT18VDDS6472HG
DDR SDRAMs = MT46V64M8S2 for MT18VDDS12872HG
IT option is not available for TwinDie components.

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

General Description

The MT9VDDT1672H, MT9VDDT3272H, MT18VDDS6472H,

MT9VDDT6472H, and MT18VDDS12872H are high-
speed CMOS, dynamic random-access, 128MB,
256MB, 512MB, and 1GB memory modules organized
in x72 (ECC) configuration. DDR SDRAM modules use
internally configured quad-bank DDR SDRAM devices.

DDR SDRAM modules use a double data rate archi-

tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effec-
tively consists of a single 2n-bit wide, one-clock-cycle
data transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.

DDR SDRAM modules operate from differential

clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.

Read and write accesses to DDR SDRAM modules

are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed [BA0, BA1 select device bank; A0A11 select
device row for MT9VDDT1672H, and A0A12 select
device row for MT9VDDT3272H, MT18VDDS6472H,
MT9VDDT6472H, and MT18VDDS12872H]. The address
bits registered coincident with the READ or WRITE
command are used to select the device bank and the
starting device column location for the burst access.

DDR SDRAM modules provide for programmable

READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, and 512Mb DDR SDRAM and
512Mb and 1Gb DDR TwinDie component data sheets.

Serial Presence-Detect Operation

DDR SDRAM modules incorporate serial presence-

detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I

C bus

using the DIMM's SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 6, Mode Register Definition Diagram, on
page 10. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.

Mode register bits A0A2 specify the burst length, A3

specifies the type of burst (sequential or interleaved),
A4A6 specify the CAS latency, and A7A11 [for

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

MT9VDDT1672H(I)] or A7A12 [for MT9VDDT3272H(I),
MT18VDDS6472H(I), MT9VDDT6472H(I), and
MT18VDDS12872H(I)] specify the operating mode.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-
mable, as shown in Mode Register Diagram. The burst
length determines the maximum number of column
locations that can be accessed for a given READ or
WRITE command. Burst lengths of 2, 4, or 8 locations
are available for both the sequential and the inter-
leaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1Ai when the burst length is set to two,
by A2Ai when the burst length is set to four and by
A3Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see Note 5 of Table 6, Burst Definition
Table, on page 11). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 11.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 7, CAS
Latency Diagram, on page 11.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,

CAS Latency (CL) Table, indicates the operating fre-
quencies at which each CAS latency setting can be
used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Figure 6: Mode Register Definition

Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA1 and BA0)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

M10

M12 M11

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA1and BA0)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

MT9VDDT1672H Module Address Bus

MT9VDDT3272H; MT18VDDT6472H; MT9VDDS6472H,
MT18VDDS12872H Module Address Bus

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

NOTE:

1. For a burst length of two, A1Ai select the two-data-

element block; A0 selects the first access within the
block.

2. For a burst length of four, A2Ai select the four-data-

element block; A0A1 select the first access within the
block.

3. For a burst length of eight, A3Ai select the eight-data-

element block; A0A2 select the first access within the
block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps
within the block.

5. i = 9 for MT9VDDT1672H, MT9VDDT3272H,

and MT18VDDS6472H;

i = 9, 11 for MT9VDDT6472H and MT18VDDS12872H.

Figure 7: CAS Latency Diagram

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7A11 (for
MT9VDDT1672H), or A7A12 (for MT9VDDT3272H,
MT18VDDS6472H, MT9VDDT6472H, and MT18VDDS12872H)
each set to zero, and bits A0A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9A11 (for
MT9VDDT1672H), or A7 and A9A12 (for MT9VDDT3272H,
MT18VDDS6472H, MT9VDDT6472H, and MT18VDDS12872H)
each set to zero, bit A8 set to one, and bits A0A6 set to
the desired values. Although not required by the
Micron device, JEDEC specifications recommend when
a LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD MODE
REGISTER command to select normal operating mode.

All other combinations of values for A7A11, or A7

A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 8, Extended Mode Register

Table 6:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A1 A0

0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 7:

CAS Latency (CL) Table

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

SPEED

CL = 2

CL = 2.5

-335

N/A

£ f £ 167

-262

£ f £ 133

-26A

£ f £ 133

-265

£ f £ 100

£ f £ 133

-202

£ f £ 100

N/A

CK#

COMMAND

DQS

CL = 2

READ

NOP

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T2n

T3n

T2n

T3n

DON'T CARE

TRANSITIONING DATA

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

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DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.

Figure 8: Extended Mode Register

Definition Diagram

NOTE:

1. E13 and E12 (MT9VDDT1672H), or E14 and E13

(MT9VDDT3272H, MT18VDDS6472H, MT9VDDT6472H,
and MT18VDDS12872H) (BA1 and BA0) must be "0, 1"
to select the Extended Mode Register (vs. the base
Mode Register).

2. The QFC# option is not supported.

Operating Mode

Reserved

Valid

DLL

Enable

Disable

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Drive Strength

Normal

E1,

Operating Mode

A10

A11

A12

BA1 BA0

E6 E5

E10

E11

E12

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Operating Mode

A10

A11

BA1 BA0

MT9VDDT1672H(I) Module Address Bus

MT9VDDT3272H(I); MT9VDDT6472H(I); MT18VDDS6472H(I),
MT18VDDS12872H(I) Module Address Bus

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Commands

Table 8, Commands Truth Table, and Table 9, DM

Operation Truth Table, provide a general reference of
available commands. For a more detailed description

of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM and 512Mb and 1Gb
DDR TwinDie

component data sheets.

NOTE:

1. DESELECT and NOP are functionally interchangeable.
2. BA0BA1 provide device bank address and A0A11 (MT9VDDT1672H) or A0A12 (MT9VDDT3272H, MT18VDDS6472H(I),

MT9VDDT6472H, and MT18VDDS12872H) provide row address.

3. BA0BA1 provide device bank address; A0A9 (MT9VDDT1672H, MT9VDDT3272H, and MT9VDDT6472H) or A0A9,11

(MT18VDDS6472H, MT18VDDS12872H), provide column address; A10 HIGH enables the auto precharge feature (nonper-
sistent), and A10 LOW disables the auto precharge feature.

4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

5. A10 LOW: BA0BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-

BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. BA0BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0BA1 are reserved). A0A11 (MT9VDDT1672H) or
A0A12 (MT9VDDT3272H, MT18VDDS6472H, MT9VDDT6472H, MT18VDDS12872H) provide the op-code to be written to
the selected mode register.

Table 8:

Commands Truth Table

CKE is HIGH for all commands shown except SELF REFRESH

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDRESS

NOTES

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

Bank/Col

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

Table 9:

DM Operation Truth Table

Used to mask write data; provided coincident with the corresponding data

NAME (FUNCTION)

DQS

WRITE Enable

Valid

WRITE Inhibit

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Supply Voltage

Relative to V

. . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Q Supply Voltage

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

REF

and Inputs Voltage

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

I/O Pin Voltage

Relative to V

. . . . . . . . . . . . . -0.5V to V

Q +0.5V

Operating Temperature,

(commercial). . . . . . . . . . . . . . . . . .. 0°C to +70°C

(industrial). . . . . . . . . . . . . . . . . . . -40°C to +85°C

Storage Temperature (plastic) . . . . . .-55°C to +150°C
Power Dissipation

Single rank modules . . . . . . . . . . . . . . . . . . . . . . . 9W
Dual rank modules . . . . . . . . . . . . . . . . . . . . . . . 18W

Short Circuit Output Current. . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

(MT9VDDT1672H, MT9VDDT3272H, MT9VDDT6472H)

Notes: 15, 14, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.3

2.7

32, 36

I/O Supply Voltage

2.3

2.7

32, 36, 39

I/O Reference Voltage

REF

0.49

Q 0.51

6, 39

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

7, 39

Input High (Logic 1) Voltage

(DC)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(DC)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT
Any input 0V

£ V

, V

REF

pin 0V

£ V

1.35V (All other pins not under test = 0V)

Command/
Address, RAS#,
CAS#, WE#,
CKE, S#

-18

µA

CK, CK#

-6

-2

OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V

£ VOUT £ VDDQ)

DQS, DQ

-5

µA

OUTPUT LEVELS
High Current (V

OUT

= V

Q - 0.373V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

-16.8

33, 34

16.8

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 11: DC Electrical Characteristics and Operating Conditions

(MT18VDDS6472H(I), MT18VDDS12872H(I))

Notes: 15, 14, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.3

2.7

32, 36

I/O Supply Voltage

2.3

2.7

32, 36, 39

I/O Reference Voltage

REF

0.49

0.51

6, 39

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

7, 39

Input High (Logic 1) Voltage

(DC)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(DC)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT
Any input 0V

£ V

, V

REF

pin 0V

£ V

1.35V (All other pins not under test = 0V)

Command/
Address, RAS#,
CAS#, WE#,

-36

µA

CKE, S#

CK, CK#

-12

-4

OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V

£ V

OUT

£ V

DQS, DQ

-10

µA

OUTPUT LEVELS

High Current (V

OUT

= V

Q - 0.373V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

-16.8

33, 34

16.8

Table 12: AC Input Operating Conditions

Notes: 15,14, 16, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.310

12, 25, 35

Input Low (Logic 0) Voltage

(

)

REF

- 0.310

12, 25, 35

I/O Reference Voltage

REF

(

)

0.49

0.51

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 13: I

Specifications and Conditions (MT9VDDT1672H)

DDR SDRAM components only
Notes: 15, 8, 10, 12, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYMBOL

-335

-262

-26A/

-265/

-202

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs
changing once every two clock cycles

DD0

1,125

990

945

20, 42

OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2;

RC =

RC (MIN);

CK =

CK (MIN);

OUT

= 0mA; Address and control inputs changing once per

clock cycle

DD1

1,215

1,080

20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;

CK =

CK (MIN); CKE =

(LOW)

DD2P

21, 28,44

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK =

CK MIN; CKE = HIGH; Address and other control

inputs changing once per clock cycle. V

= V

REF

for DQ,

DQS, and DM

DD2F

405

402

360

ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;

CK =

CK (MIN); CKE =

LOW

DD3P

225

180

21, 28, 44

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM andDQS inputs changing twice

per clock cycle; Address and other control inputs changing
once per clock cycle

DD3N

450

405

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing
once per clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

1,260

1,170

1,125

20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle;

CK =

CK (MIN); DQ, DM,

and DQS inputs changing twice per clock cycle

DD4W

1,260

1,125

1,080

AUTO REFRESH CURRENT

RC =

RFC (MIN)

DD5

2,385

1,980

20, 44

RFC = 15.625µs

DD5A

24, 44

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN); Address and control inputs change only

during Active READ, or WRITE commands

DD7

3,195

2,970

2,925

20, 43

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 14: I

Specifications and Conditions (MT9VDDT3272H)

DDR SDRAM components only
Notes: 15, 8, 10, 12, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYMBOL

-335

-262

-26A/

-265

-202

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs
changing once every two clock cycles

DD0

1,125

945

1,080

20, 42

OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 4;

RC =

RC (MIN);

CK =

CK (MIN);

OUT

= 0mA; Address and control inputs changing once per

clock cycle

DD1

1,530

1,440

1,305

1,395

20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode;

CK =

CK (MIN);

CKE = (LOW)

DD2P

21,28, 44

IDLE STANDBY CURRENT: CS# = HIGH; All device banks
idle;

CK =

CK MIN; CKE = HIGH; Address and other

control inputs changing once per clock cycle. V

= V

REF

for

DQ, DQS, and DM

DD2F

450

405

ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;

CK =

CK (MIN);

CKE = LOW

DD3P

270

225

270

21, 28 ,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM andDQS inputs changing twice

per clock cycle; Address and other control inputs changing
once per clock cycle

DD3N

540

450

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing
once per clock cycle;

CK =

CK (MIN);

OUT

= 0mA

DD4R

1,575

1,350

1,575

20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle;

CK =

CK (MIN); DQ, DM,

and DQS inputs changing twice per clock cycle

DD4W

1,395

1,215

1,710

AUTO REFRESH CURRENT

RC =

RFC(MIN)

DD5

2,295

2,115

2,205

20,44

RFC = 7.8125µs

DD5A

24, 44

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN); Address and control inputs change only during

Active READ, or WRITE commands

DD7

3,645

3,150

3,285

20, 43

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 15: I

Specifications and Conditions (MT9VDDT6472H)

DDR SDRAM components only
Notes: 15, 8, 10, 12, 48, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYMBOL

-335

-262

-26A/-265/

-202

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs
changing once every two clock cycles

DD0

1,170

1,035

20, 42

OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 4;

RC =

RC (MIN);

CK =

CK (MIN);

OUT

= 0mA; Address and control inputs changing once per

clock cycle

DD1

1,440

1,305

20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;

CK =

CK (MIN); CKE =

(LOW)

DD2P

21, 28, 44

IDLE STANDBY CURRENT: CS# = HIGH; All device banks
idle;

CK =

CK MIN; CKE = HIGH; Address and other

control inputs changing once per clock cycle. V

= V

REF

for

DQ, DQS, and DM

DD2F

405

360

ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;

CK =

CK (MIN);

CKE = LOW

DD3P

315

270

21,28, 44

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM andDQS inputs changing twice

per clock cycle; Address and other control inputs changing
once per clock cycle

DD3N

405

360

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing
once per clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

1,485

1,305

20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle;

CK =

CK (MIN); DQ, DM,

and DQS inputs changing twice per clock cycle

DD4W

1,395

1,215

AUTO REFRESH CURRENT

RC =

RFC(MIN)

DD5

2,610

2,520

20, 44

RFC = 7.8125µs

DD5A

24, 44

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN); Address and control inputs change only

during Active READ, or WRITE commands

DD7

3,645

3,600

3,150

20, 43

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 16: I

Specifications and Conditions (MT18VDDS6472H)

DDR SDRAM components only
Notes: 15, 8, 10, 12, 48, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYMBOL -26A/-265

-202

UNITS NOTES

OPERATING CURRENT: (I

DD0

Condition) One device bank; Active-

Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs changing once
every two clock cycles

DD0

TBD

20, 42

OPERATING CURRENT: (I

DD1

condition) One device bank; Active-Read-

Precharge; Burst = 4;

RC =

RC (MIN);

CK =

CK (MIN)); I

OUT

= 0mA;

Address and control inputs changing once per clock cycle

TBD

20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: (I

DD2P

Condition) All

device banks idle; Power-down mode;

CK =

CK (MIN); CKE = (LOW)

DD2

TBD

21, 28,

IDLE STANDBY CURRENT: (I

DD2F

Condition) CS# = HIGH; All device banks

are idle;

CK =

CK (MIN); CKE = HIGH; Address and other control inputs

changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2

TBD

ACTIVE POWER-DOWN STANDBY CURRENT: (I

DD3P

Condition) One device

bank active; Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3

TBD

21, 28,

ACTIVE STANDBY CURRENT: (I

DD3N

condition) CS# = HIGH; CKE = HIGH;

One device bank active;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM and

DQS inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle

DD3

TBD

OPERATING CURRENT: (I

DD4R

condition) Burst = 2; Reads; Continuous

burst; One device bank active; Address and control inputs changing once

per clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4

TBD

20,42

OPERATING CURRENT: (I

DD4W

condition) Burst = 2; Writes; Continuous

burst; One device bank active; Address and control inputs changing once

per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs changing twice

per clock cycle

DD4

TBD

AUTO REFRESH BURST CURRENT: An AUTO
REFRESH command is given to one module rank,
and on the next clock cycle the second module rank
recieves an AUTO REFRESH command. CKE = HIGH

RC =

RFC(MIN)

TBD

20, 44

AUTO REFRESH DISTRUBUTED CURRENT: An AUTO
REFRESH command is given to one module rank,
and on the next clock cycle the second module rank
recieves an AUTO REFRESH command; CKE = LOW

for

RFC time

RFC = 7.8125µs

DD5

TBD

24, 44

SELF REFRESH CURRENT: Both module rank are in I

DD6

condition, CKE

0.2V

TBD

OPERATING CURRENT: One module rank in I

DD7

condition, one module

rank in I

DD3N

condition. (I

DD7

condition) Four device bank interleaving

READs (BL=4) with auto precharge,

RC =

RC (MIN);

CK = t

CK (MIN);

Address and control inputs change only during Active READ, or WRITE
commands.

TBD

20,43

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

DD2P

(CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 17: I

Specifications and Conditions (MT18VDDS12872H)

DDR SDRAM components only
Notes: 15, 8, 10,12, 48, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYMBOL

-26A/-265

-202

UNITS

NOTES

OPERATING CURRENT: (I

DD0

Condition) One device bank; Active-

Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs changing
once every two clock cycles

DD0

TBD

20, 42

OPERATING CURRENT: (I

DD1

condition) One device bank; Active-Read-

Precharge; Burst = 4;

RC =

RC (MIN);

CK =

CK (MIN)); I

OUT

= 0mA;

Address and control inputs changing once per clock cycle

TBD

20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: (I

DD2P

Condition) All

device banks idle; Power-down mode;

CK =

CK (MIN); CKE = (LOW)

DD2

TBD

21, 28,

IDLE STANDBY CURRENT: (I

DD2F

Condition) CS# = HIGH; All device

banks are idle;

CK =

CK (MIN); CKE = HIGH; Address and other control

inputs changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2

TBD

ACTIVE POWER-DOWN STANDBY CURRENT: (I

DD3P

Condition) One

device bank active; Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3

TBD

21, 28,

ACTIVE STANDBY CURRENT: (I

DD3N

condition) CS# = HIGH; CKE = HIGH;

One device bank active;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM

and DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle

DD3

TBD

OPERATING CURRENT: (I

DD4R

condition) Burst = 2; Reads; Continuous

burst; One device bank active; Address and control inputs changing

once per clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4

TBD

20, 42

OPERATING CURRENT: (I

DD4W

condition) Burst = 2; Writes; Continuous

burst; One device bank active; Address and control inputs changing

once per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

DD4

TBD

AUTO REFRESH BURST CURRENT: An AUTO REFRESH
command is given to one module rank, and on the
next clock cycle the second module rank recieves an
AUTO REFRESH command. CKE = HIGH

RC =

RFC(MIN)

TBD

20, 44

AUTO REFRESH DISTRUBUTED CURRENT: An AUTO
REFRESH command is given to one module rank, and
on the next clock cycle the second module rank
recieves an AUTO REFRESH command; CKE = LOW for

RFC time

RFC = 7.8125µs

DD5

TBD

24, 44

SELF REFRESH CURRENT: Both module rank are in I

DD6

condition, CKE

0.2V

TBD

OPERATING CURRENT: One module rank in I

DD7

condition, one module

rank in I

DD3N

condition. (I

DD7

condition) Four device bank interleaving

READs (BL=4) with auto precharge,

RC =

RC (MIN);

CK = t

CK (MIN);

Address and control inputs change only during Active READ, or WRITE
commands.

TBD

20,43

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

DD2P

(CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 18: Capacitance (MT9VDDT1672H(I), MT9VDDT3272H(I), MT9VDDT6472H(I))

Note: 11; notes appear on pages 2528

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input/Output Capacitance: DQ, DQS, DM

Input Capacitance: Command and Address

Input Capacitance: S#

Input Capacitance:CK, CK#

Input Capacitance: CKE

Table 19: Capacitance (MT18VDDS6472H(I), MT18VDDS12872H(I))

Note: 11; notes appear on pages 2528

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input/Output Capacitance: DQ, DQS, DM

Input Capacitance: Command and Address

Input Capacitance: S#

Input Capacitance:CK, CK#

Input Capacitance: CKE

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 20: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-335 and -262 Speed Grades)

Notes: 15, 12-15, 29, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-335

-262

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.7

+0.7

-0.75

+0.75

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

CK (2.5)

7.5

40, 46

CL=2

CK (2)

7.5

40, 46

DQ and DM input hold time relative to DQS

0.45

0.5

23, 27

DQ and DM input setup time relative to DQS

0.45

0.5

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.60

+0.60

-0.75

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.45

0.5

22, 23

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.70

+0.75

16, 37

Data-out low-impedance window from CK/CK#

-0.70

-0.75

16, 38

Address and control input hold time (fast slew rate)

0.75

0.90

Address and control input setup time (fast slew rate)

0.75

0.90

Address and control input hold time (slow slew rate)

0.80

Address and control input setup time (slow slew rate)

0.80

Address and Control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

HP -

QHS

HP -

QHS

22, 23

Data hold skew factor

QHS

0.60

0.75

ACTIVE to PRECHARGE command

RAS

70,000

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

17, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

QH -

DQSQ

QH -

DQSQ

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

REFRESH to REFRESH command
interval

MT9VDDT1672H

REFC

140.6

µs

All others

70.3

µs

Average periodic refresh interval

MT9VDDT1672H

REFI

15.6

µs

All others

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ
command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Table 20: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-335 and -262 Speed Grades) (Continued)

Notes: 15, 12-15, 29, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-335

-262

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Table 21: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-26A, -265, and -202 Speed Grades)

Notes: 15, 12-15, 29, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-26A/-265

-202

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.75

0.75

-0.8

0.8

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

CK (2.5)

7.5

40, 46

CL=2

CK (2)

7.5/10

40, 46

DQ and DM input hold time relative to DQS

0.5

0.6

23, 27

DQ and DM input setup time relative to DQS

0.5

0.6

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.75

+0.75

-0.8

+0.8

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.5

0.6

22, 23

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.75

+0.8

16, 37

Data-out low-impedance window from CK/CK#

-0.75

-0.8

16, 38

Address and control input hold time (fast slew rate)

0.90

1.1

Address and control input setup time (fast slew rate)

0.90

1.1

Address and control input hold time (slow slew rate)

1.1

Address and control input setup time (slow slew rate)

1.1

Address and Control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

HP -

QHS

HP -

QHS

22, 23

Data hold skew factor

QHS

0.75

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ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

17, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command
delay

WTR

Data valid output window

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval MT9VDDT1672H

REFC

140.6

µs

All others

70.3

µs

Average periodic refresh interval

MT9VDDT1672H

REFI

15.6

µs

All others

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Table 21: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-26A, -265, and -202 Speed Grades) (Continued)

Notes: 15, 12-15, 29, 48; notes appear on pages 2528; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-26A/-265

-202

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

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Notes

1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical AC and DC

characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test environment, but
input timing is still referenced to V

REF

(or to the

crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V

(

)

and V

(

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal V

Q/2 of the transmit-

ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V

REF

may not exceed ±2 percent of the

DC value. Thus, from V

Q/2, V

REF

is allowed

±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V

REF

by-pass capacitor.

7. V

is not applied directly to the device. V

is a

system supply for signal termination resistors, is
expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

8. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -26A and -202, CL =
2.5 for -265 and -335 with the outputs open.

9. Enables on-chip refresh and address counters.

10. I

specifications are tested after the device is

properly initialized, and is averaged at the defined
cycle rate.

11. This parameter is sampled. V

= +2.5V ±0.2V,

Q = +2.5V ±0.2V, V

REF

= V

, f = 100 MHz, T

25°C, V

OUT

(DC) = V

Q/2, V

OUT

(peak to peak) =

0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.

12. Command/Address input slew rate = 0.5V/ns. For

-262, -26A, and -265, with slew rates 1V/ns and
faster,

IS and

IH are reduced to 900ps; for -335

with those slew rates,

IS and

IH are reduced to

750ps. If the slew rate is less than 0.5V/ ns, timing
must be derated:

IS has an additional 50ps per

each 100mV/ns reduction in slew rate from the
500mV/ns, while

IH remains constant. If the slew

rate exceeds 4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V

REF

14. Inputs are not recognized as valid until V

REF

stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE

£ 0.3 x V

Q is recognized as LOW.

15. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is
V

16.

HZ and

LZ transitions occur in the same access

time windows as data valid transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).

17. The intent of the Don't Care state after completion

of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is, if DQS
transitions high [above V

IHDC

(MIN)] then it must

not transition low (below V

IHDC

) prior to

DQSH

(MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on

DQSS.

20. MIN (

RC or

RFC) for I

measurements is the

smallest multiple of

CK that meets the minimum

absolute value for the respective parameter.

RAS

(MAX) for I

measurements is the largest multi-

ple of

CK that meets the maximum absolute

value for

RAS.

Output
(V

OUT

)

Reference

Point

30pF

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21. The refresh period 64ms. This equates to an aver-

age refresh rate of 15.625µs (MT9VDDT1672H) or
7.8125µs (MT9VDDT3272H, MT18VDDS6472H,
MT9VDDT6472H, and MT18VDDS12872H). How-
ever, an AUTO REFRESH command must be as-
serted at least once every 140.6µs (MT9VDDT1672H)
or 70.3µs (MT9VDDT3272H, MT18VDDS6472H,
MT9VDDT6472H, and MT18VDDS12872H); burst
refreshing or posting by the DRAM controller
greater than eight refresh cycles is not allowed.

22. The valid data window is derived by achieving

other specifications:

HP (

CK/2),

DQSQ, and

(

QH =

HP -

QHS). The data valid window derates

directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Figure 9, Derating Data Valid Window,
shows derating curves are provided below for duty
cycles ranging between 50/50 and 45/55.

23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during

REFRESH command period (

RFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current

AC level through to the target AC level, V

(

)

or V

(

b. Reach at least the target AC level.
c. After the AC target level is reached, continue to

maintain at least the target DC level, V

(

) or

(

26. JEDEC specifies CK and CK# input slew rate must

1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to

DS and

DH for each 100mv/ns reduction in slew rate. If

slew rate exceeds 4V/ns, functionality is uncer-
tain.

28. V

must not vary more than 4 percent if CKE is

not active while any bank is active.

Figure 9: Derating Data Valid Window

(

DQSQ)

3.750

3.700

3.650

3.600

3.550

3.500

3.450

3.400

3.350

3.300

3.250

3.400

3.350

3.300

3.250

3.200

3.150

3.100

3.050

3.000

2.950

2.900

2.500

2.463

2.425

2.388

2.350

2.313

2.275

2.238

2.200

2.163

2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50

49.5/50.5 49/51

48.5/52.5

48/52

47.5/53.5

47/53

46.5/54.5

46/54

45.5/55.5

45/55

Clock Duty Cycle

-26A/-265 @

CK = 10ns

-202 @

CK = 10ns

-262/-26A/-265 @

CK = 7.5ns

-202 @

CK = 8ns

-335 @

CK = 6ns

N/A

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29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same
amount.

30.

HP min is the lesser of

CL minimum and

minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not

allowed to be issued until

RAS(MIN) can be satis-

fied prior to the internal precharge command
being issued.

32. Any positive glitch in the nominal voltage must be

less than 1/3 of the clock and not more than
+400mV or 2.9V maximum, whichever is less. Any
negative glitch must be less than 1/3 of the clock
cycle and not exceed either -300mV or 2.2V mini-
mum, whichever is more positive.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Pull-Down Characteristics.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 10, Pull-Down Characteristics.

c. The full variation in driver pull-up current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 11,
Pull-Up Characteristics.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
11, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between .71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.

34. The voltage levels used are derived from a mini-

mum V

level and the referenced test load. In

practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.

35. V

overshoot: V

(MAX) = V

Q + 1.5V for a

pulse width

£ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. V

undershoot:

(MIN) = -1.5V for a pulse width

£ 3ns and the

pulse width can not be greater than 1/3 of the
cycle rate.

36. V

and V

Q must track each other.

37. This maximum value is derived from the refer-

enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for

HZ (MAX) and the last DVW.

(MAX) will prevail over

DQSCK (MAX) +

RPST

(MAX) condition.

LZ (MIN) will prevail over

DQSCK (MIN) +

RPRE (MAX) condition.

38. For slew rates greater than 1V/ns the (LZ) transi-

tion will start about 310ps earlier.

39. During initialization, V

Q, V

, and V

REF

must

be equal to or less than V

+ 0.3V. Alternatively,

may be 1.35V maximum during power up,

even if V

Q are 0V, provided a minimum of

W of series resistance is used between the V

supply and the input pin.

Figure 10: Pull-Down Characteristics

Figure 11: Pull-Up Characteristics

160

140

OUT

(mA)

OUT

(V)

Nominal low

Minimum

Nominal high

Maximum

120

100

0.0

0.5

1.0

1.5

2.0

2.5

OUT

(V)

-20

OUT

(mA)

Nominal low

Minimum

Nominal high

Maximum

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0

0.5

1.0

1.5

2.0

2.5

Q - V

OUT

(V)

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40. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.

41. For -335, -262, -26A, and -265 speed grades, Idd3N

is specified to be 35mA per DDR SDRAM device at
100 MHz.

42. Random addressing changing and 50 percent of

data changing at every transfer.

43. Random addressing changing and 100 percent of

data changing at every transfer.

44. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until

REF later.

45. I

2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. I

2Q is

similar to I

2F except I

2Q specifies the

address and control inputs to remain stable.
Although I

2F, I

2N, and I

2Q are similar,

2F is "worst case."

46. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).

47. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

48. When an input signal is HIGH or LOW, it is

defined as a steady state logic HIGH or LOW.

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SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 12, Data Validity, and Figure 13, Defi-
nition of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 14, Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 12: Data Validity

Figure 13: Definition of Start and Stop

Figure 14: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

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Figure 15: SPD EEPROM Timing Diagram

Table 22: EEPROM Device Select Code

Most significant bit (b7) is sent first

SELECT CODE

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 23: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

or V

START, Device Select, RW = `1'

Random Address Read

or V

START, Device Select, RW = `0', Address

or V

reSTART, Device Select, RW = `1'

Sequential Read

or V

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = `0'

Page Write

£ 16

START, Device Select, RW = `0'

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

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NOTE:

1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising

edge of SDA.

2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (

WRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 24: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +2.3V to +3.6V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

DDSPD

2.3

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

0.7

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

x 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

µA

STANDBY CURRENT:
SCL = SDA = V

- 0.3V; All other inputs = V

or V

µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz

Table 25: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +2.3V to +3.6V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.2

0.9

µs

Time the bus must be free before a new transition can start

BUF

1.3

µs

Data-out hold time

200

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

0.6

µs

Clock HIGH period

HIGH

0.6

µs

Noise suppression time constant at SCL, SDA inputs

Clock LOW period

LOW

1.3

µs

SDA and SCL rise time

0.3

µs

SCL clock frequency

SCL

400

KHz

Data-in setup time

SU:DAT

100

Start condition setup time

SU:STA

0.6

µs

Stop condition setup time

SU:STO

0.6

µs

WRITE cycle time

WRC

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Table 26: Serial Presence-Detect Matrix (MT9VDDT1672H(I), MT9VDDT3272H(I),

MT9VDDT6472H(I))

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY (VERSION)

MT9VDDT1672H MT9VDDT3272H MT9VDDT6472H

Number of SPD Bytes Used by Micron

128

Total Number of Bytes in SPD Device

256

Fundamental Memory Type

SDRAM DDR

Number of Row Addresses on Assembly

12 or 13

Number of Column Addresses on
Assembly

10 or 11

Number of Physical Ranks on DIMM

Module Data Width

Module Data Width (Continued)

Module Voltage Interface Levels

SSTL 2.5V

SDRAM Cycle Time,

CK (CAS Latency =

2.5) (See note 1)

6ns (-335)

7ns (-262/-26A)

7.5ns (-265)

8ns (-202)

60
70
75
80

SDRAM Access from Clock,

AC (CAS

Latency = 2.5)

0.7ns (-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

70
75
80

Module Configuration Type

ECC

Refresh Rate/Type

15.62µs, 7.8µs/SELF

SDRAM Device Width (Primary DDR
SDRAM)

Error-checking DDR SDRAM Data Width

Minimum Clock Delay, Back-to-Back
Random Column Access

1 clock

Burst Lengths Supported

2, 4, 8

Number of Banks on DDR SDRAM Device

CAS Latencies Supported

2, 2.5

CS Latency

WE Latency

SDRAM Module Attributes

Unbuffered/Diff. Clock

SDRAM Device Attributes: General

Fast/Concurrent AP

SDRAM Cycle Time,

CK (CAS Latency = 2)

(See note 1)

7.5ns (-335/-262/-26A)

10ns (-265/-202)

SDRAM Access from CK,

AC (CAS Latency

= 2)

0.7ns (-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

70
75
80

SDRAM Cycle Time,

CK (CAS Latency =

1.5)

N/A

SDRAM Access from CK ,

AC (CAS Latency

= 1.5)

N/A

Minimum Row Precharge Time,

18ns (-335)
15ns (-262)

20ns (-26A/-265/-202)

48
3C
50

Minimum Row Active to Row Active,

RRD

12ns (-335)

15ns (-262/-26A/-265/-202)

30
3C

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Minimum RAS# to CAS# Delay,

RCD

18ns (-335)

20ns (-262)

20ns (-265/-26A/-2025)

48
3C
50

Minimum RAS# Pulse Width,

RAS

(See note 3)

42ns

45ns (-262/-26A/-265)

40ns (-202)

2A
2D

Module Rank Density

128MB, 256MB, 512MB

Address and Command Setup Time,

(See note 4)

0.8ns (-335)

1.0ns (-262/-26A/-265)

1.1ns (-202)

Address and Command Hold Time,

(See note 4)

0.8ns (-335)

1.0ns (-262/-26A/-265)

1.1ns (-202)

Data/Data Mask Input Setup Time,

0.45ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

45
50
60

Data/Data Mask Input Hold Time,

0.45ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

45
50
60

36-40 Reserved

Min Active Auto Refresh Time,

60ns (-335/-262)

65ns (-26A/-265)

70ns (-202)

3C
41
46

Minimum Auto Refresh to Active/

Auto Refresh Command Period,

RFC

72ns (-335)

75ns (-262/-26A/-265)

80ns (-202)

48
4B
50

SDRAM Device Max Cycle Time,

MAX

12ns (-335)

13ns (-262/-26A/-265/-202)

30
34

SDRAM Device Max DQS-DQ Skew Time

DQSQ

0.45ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

32
3C

SDRAM Device Max Read Data Hold Skew

Factor

QHS

0.6ns (-335)

0.75ns (-262/-26A/-265)

1.0ns (-202)

60
75

46-61 Reserved

SPD Revision

Release 0.0

Checksum For Bytes 0-62

-335
-262

-26A

-265
-202

F5
90

E8
18
B3

74
FC
29
59
F4

Manufacturer's JEDEC ID Code

MICRON

65-71 Manufacturer's JEDEC ID Code

(Continued)

Manufacturing Location

0111

01B0

73-90 Module Part Number (ASCII)

Variable Data

PCB Identification Code

1-9

01-09

Identification Code (Continued)

Table 26: Serial Presence-Detect Matrix (MT9VDDT1672H(I), MT9VDDT3272H(I),

MT9VDDT6472H(I)) (Continued)

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY (VERSION)

MT9VDDT1672H MT9VDDT3272H MT9VDDT6472H

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

NOTE:

1. Device latencies used for SPD values.

2. Value for -262/-26A

CK set to ns (0x70) for optimum BIOS compatibility. Actual device specification value is 7.5ns.

3. The value of

RAS used for -26A/-265 modules is calculated from

RC -

RP. Actual device spec value is 40 ns.

4. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.

Year of Manufacture in BCD

Variable Data

Week of Manufacture in BCD

Variable Data

95-98 Module Serial Number

Variable Data

99-127 Manufacturer-Specific Data (RSVD)

Table 26: Serial Presence-Detect Matrix (MT9VDDT1672H(I), MT9VDDT3272H(I),

MT9VDDT6472H(I)) (Continued)

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY (VERSION)

MT9VDDT1672H MT9VDDT3272H MT9VDDT6472H

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

Table 27: Serial Presence-Detect Matrix (MT18VDDS6472H(I),

MT18VDDS12872H(I))

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY (VERSION)

MT18VDDS6472H

MT18VDDS12872H

Number of SPD Bytes Used by Micron

128

Total Number of Bytes in SPD Device

256

Fundamental Memory Type

SDRAM DDR

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

10 or 11

Number of Physical Ranks on DIMM

Module Data Width

Module Data Width (Continued)

Module Voltage Interface Levels

SSTL 2.5V

SDRAM Cycle Time,

CK (CAS Latency = 2.5)

(See note 1)

7ns (-26A)

7.5ns (-265)

8ns (-202)

70
75
80

SDRAM Access from Clock,

AC (CAS Latency =

2.5) (See note 1)

0.75ns (-26A/-265)

0.8ns (-202)

75
80

Module Configuration Type

ECC

Refresh Rate/type

7.81µs/SELF

SDRAM Device Width (Primary DDR SDRAM)

Error-checking Ddr Sdram Data Width

Minimum Clock Delay, Back-to-Back Random
Column Access

1 clock

Burst Lengths Supported

2, 4, 8

Number of Banks on DDR SDRAM Device

CAS Latencies Supported

2, 2.5

CS Latency

WE Latency

SDRAM Module Attributes

Unbuffered/Diff. Clock

SDRAM Device Attributes: General

Fast/Concurrent AP

SDRAM Cycle Time,

CK (CAS Latency = 2) (See

note 2)

7.5ns (-26A)

10ns (-265/-202)

SDRAM Access from CK,

AC (CAS Latency = 2)

(See note 2)

7.5ns (-26A/-265)

8ns (-202)

75
80

SDRAM Cycle Time,

CK (CAS Latency = 1.5)

N/A

SDRAM Access from CK ,

AC (CAS Latency =

1.5)

N/A

Minimum Row Precharge Time,

20 ns

Minimum Row Active to Row Active,

RRD

15 ns

Minimum RAS# to CAS# Delay,

RCD

20 ns

Minimum RAS# Pulse Width,

RAS

(See note 3)

45ns (-26A/-265)

40ns (-202)

Module Rank Density

256MB, 512MB

Address and Command Setup Time,

IS, (See

note 4)

1.0ns (-26A/-265)

1.1ns (-202)

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

NOTE:

1. Device latencies used for SPD values.

2. Value for -262/-26A

CK set to ns (0x70) for optimum BIOS compatibility. Actual device specification value is 7.5ns.

3. The value of

RAS used for -26A/-265 modules is calculated from

RC -

RP. Actual device spec value is 40 ns.

4. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.

Address and Command Hold Time,

IH (See

note 4)

1.0ns (-26A/-265)

1.1ns (-202)

Data/Data Mask Input Setup Time,

0.5ns (-26A/-265)

0.6ns (-202)

50
60

Data/Data Mask Input Hold Time,

0.5ns (-26A/-265)

0.6ns (-202)

50
60

36-40 Reserved

Min Active Auto Refresh Time,

65ns (-26A/-265)

70ns (-202)

41
46

Minimum Auto Refresh to Active/

Auto Refresh Command Period,

RFC

75ns (-26A/-265)

80ns (-202)

4B
50

SDRAM Device Max Cycle Time,

MAX

CK (MAX) = 13.0ns

SDRAM Device Max DQS-DQ Skew Time

DQSQ

0.5ns (-26A/-265)

0.6ns (-202)

32
3C

SDRAM Device Max Read Data Hold Skew

Factor

QHS

0.75ns (-26A/-265)

1.0ns (-202)

46-61 Reserved

SPD Revision

Release 0.0

Checksum For Bytes 0-62

-26A

-265
-202

E9
19
B4

2A
5A

Manufacturer's JEDEC ID Code

MICRON

65-71 Manufacturer's JEDEC ID Code

(Continued)

Manufacturing Location

0111

01B0

73-90 Module Part Number (ASCII)

Variable Data

PCB Identification Code

1-9

01-09

Identification Code (Continued)

Year of Manufacture in BCD

Variable Data

Week of Manufacture in BCD

Variable Data

95-98 Module Serial Number

Variable Data

99-127 Manufacturer- Specific Data (RSVD)

Table 27: Serial Presence-Detect Matrix (MT18VDDS6472H(I), MT18VDDS12872H(I))

(Continued)

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY (VERSION)

MT18VDDS6472H

MT18VDDS12872H

128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

09005aef806e057b

Micron Technology, Inc., reserves the right to change products or specifications without notice..

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 17: 200-PIN DDR SODIMM Dimensions (Low-Profile PCB)

NOTE:

All dimensions are in inches (millimeters),

, or typical where noted.

Data Sheet Designation

Advance: This datasheet contains initial descrip-

tions of products still under development. This desig-
nation applies to part numbers MT18VDDS6472H(I)
and MT18VDDS12872H(I).

Released: This data sheet contains minimum and

maximum limits specified over the complete power

supply and temperature range for production devices.
Although considered final, these specifications are
subject to change, as further product development and
data characterization sometimes occur. This designa-
tion applies to part numbers MT9VDDT1672H(I),
MT9VDDT3272H(I), and MT9VDDT6472H(I).

U10

0.150 (3.80)

MAX

0.043 (1.10)
0.035 (0.90)

PIN 1

2.667 (67.75)
2.656 (67.45)

0.787 (20.00)

TYP

0.071 (1.80)

(2X)

0.024 (0.61)

TYP

0.018 (0.46)

TYP

0.079 (2.00) R

(2X)

PIN 199

PIN 200

PIN 2

FRONT VIEW

0.079 (2.00)

0.236 (6.00)

2.504 (63.60)

0.096 (2.44)

0.039 (0.99)

TYP

1.244 (31.60)
1.256 (31.90)

BACK VIEW

0.320 (8.13) MAX

Dual Rank SoDIMM

0.043 (1.10)
0.035 (0.90)

MAX

MIN

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Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT9VDDT1672HIG-262__