DAC 3550A
Stereo Audio DAC
6251-109-4E
Edition July 23, 1999
6251-467-1DS
MICRONAS
MICRONAS
MICRONAS
MICRONAS
MICRONAS
DAC 3550A
2
Micronas
Contents
Page
Section
Title
3
1.
Introduction
3
1.1.
Main Features
5
2.
Functional Description
5
2.1.
I
2
S Interface
6
2.2.
Interpolation Filter
6
2.3.
Variable Sample and Hold
6
2.4.
3rd-order Noise Shaper and Multibit DAC
6
2.5.
Analog Low-pass
6
2.6.
Input Select and Mixing Matrix
6
2.7.
Postfilter Op Amps, Deemphasis Op Amps, and Line-Out
7
2.8.
Analog Volume
7
2.9.
Headphone Amplifier
8
2.10.
Clock System
8
2.10.1.
Standard Mode
8
2.10.2.
MPEG Mode
9
2.11.
I
2
C Bus Interface
9
2.12.
Registers
9
2.13.
Chip Select
9
2.14.
Reduced Feature Mode
10
3.
Specifications
10
3.1.
Outline Dimensions
10
3.2.
Pin Connections and Short Descriptions
12
3.3.
Pin Descriptions
12
3.3.1.
Power Supply Pins
12
3.3.2.
Analog Audio Pins
12
3.3.3.
Oscillator and Clock Pins
13
3.3.4.
Other Pins
13
3.4.
Pin Configuration
14
3.5.
Pin Circuits
15
3.6.
Control Registers
17
3.7.
Electrical Characteristics
17
3.7.1.
Absolute Maximum Ratings
18
3.7.2.
Recommended Operating Conditions
20
3.7.3.
Characteristics
25
4.
Applications
25
4.1.
Line Output Details
25
4.2.
Recommended Low-Pass Filters for Analog Outputs
26
4.3.
Recommendations for Filters and Deemphasis
26
4.4.
Recommendations for MegaBass Filter without Deemphasis plus 1st-order low-pass
27
4.5.
Power-up/down Sequence
27
4.5.1.
Power-up Sequence
27
4.5.2.
Power-down Sequence
28
4.6.
Typical Applications
32
5.
Data Sheet History
DAC 3550A
Micronas
3
Stereo Audio DAC
1. Introduction
The DAC 3550A is a single-chip, high-precision, dual
digital-to-analog converter designed for audio applica-
tions. The employed conversion technique is based on
oversampling with noise-shaping.
With Micronas' unique multibit sigma-delta technique,
less sensitivity to clock jitter, high linearity, and a supe-
rior S/N ratio has been achieved. The DAC 3550A is
controlled via I
2
C bus.
Digital audio input data is received by a versatile I
2
S
interface. The analog back-end consists of internal
analog filters and op amps for cost-effective additional
external sound processing. The DAC 3550A provides
line-out, headphone/speaker amplifiers, and volume
control. Moreover, mixing additional analog audio
sources to the D/A-converted signal is supported.
The DAC 3550A is designed for all kinds of applica-
tions in the audio and multimedia field, such as:
MPEG players, CD players, DVD players, CD-ROM
players, etc. The DAC 3550A ideally complements the
MPEG 1/2 layer 2/3 audio decoder MAS 3507D.
No crystal required for standard applications with
sample rates from 32 to 48 kHz. Crystal required
only for automatic sample rate detection below 32 kHz,
MPEG mode (refer to Section 2.10), and use of clock
output CLKOUT.
1.1. Main Features
no master main input clock required
integrated stereo headphone amplifier and mono
speaker amplifier
SNR of 103 dBA
I
2
C bus, I
2
S bus
internal clock oscillator
full-feature mode by I
2
C control (three selectable
subaddresses)
reduced feature mode for non-I
2
C applications
continuous sample rates from 8 kHz to 50 kHz
analog deemphasis for 44.1 kHz
analog volume and balance: +18...
-
75 dB and mute
oversampling and multibit noise-shaping technique
THD better than 0.01 %
two additional analog stereo inputs (AUX) with
source selection and mixing
supply range: 2.7 V...5.5 V
low-power mode
additional line-out
on-chip op amps for cost-effective external analog
sound processing
Fig. 11: Block diagram of the DAC 3550A
Fig. 12: Typical application: MPEG Layer 3 Player
WSI
CLI
DRI
OUTL
OUTR
Inter-
DAC
Input
Select
polation
Filter
Volume
and
Headphone
Amplifier
I
2
S
Analog Inputs
and
Mixing
MAS
ROM, CD-ROM,
RAM, Flash Mem. ..
DAC
Host
3507D
3550A
(PC, Controller)
I
2
S
line out
demand signal
MPEG clock
MPEG bit stream
CLKOUT
14.725 MHz
DAC 3550A
4
Micronas
Fig. 13: Block diagram of the DAC 3550A
3rd-order Noise Shaper
I
2
S
Input Select
Interpolation Filter
Variable S & H
Osc.
Postfilter Op Amps
Analog Volume
Headphone Amplifier
Digital Supply
Analog
Control
I
2
C
Analog Low-pass Filter
Sample Rate
PLL
&
Multibit DAC
Deemphasis Op Amps
Vdd
Vss
AVDD0
AVDD1
AVSS0
AVSS1
VREF
AGNDC
SDA
SCL
PORQ
DEECTRL
MCS1
MCS2
AUX1R
AUX2R
DEEMR
FOPR
FOUTR
FINR
OUTR
OUTL
FINL
FOUTL
DEEML
AUX2L
AUX1L
XTO
XTI
CLKOUT
CLI
DAI
WSI
TESTEN
Switch Matrix
FOPL
Line-Out
9
10
3
2
44
1
16
15
27
26
19
21
20
32
30
35
42
41
43
18
17
5
7
39
37
38
34
31
29
12
13
14
23
24
25
Detection
Supply
DAC 3550A
Micronas
5
2. Functional Description
2.1. I
2
S Interface
The I
2
S interface is the digital audio interface between
the DAC 3550A and external digital audio sources
such as CD/DAT players, MPEG decoders etc. It cov-
ers most of the I
2
S-compatible formats.
All modes have two common features:
1. The MSB is left justified to an I
2
S frame identifica-
tion (WSI) transition.
2. Data is valid on the rising edge of the bit clock CLI.
16-bit mode
In this case, the bit clock is 32
fs
audio
. Maximum word
length is 16 bit.
32-bit mode
In this case, the bit clock is 64
fs
audio
. Maximum word
length is 32 bit.
Automatic Detection
No I
2
C control is required to switch between 16- and
32-bit mode. It is recommended to switch the
DAC 3550A into mute position during changing
between 16- and 32-bit mode.
For high-quality audio, it is recommended to use the
32-bit mode of the I
2
S interface to make use of the full
dynamic range (if more than 16 bits are available).
Left-Right Selection
Standard I
2
S format defines an audio frame always
starting with left channel and low-state of WSI. How-
ever, I
2
C control allows changing the polarity of WSI.
Delay Bit
Standard I
2
S format requires a delay of one clock
cycle between transitions of WSI and data MSB. In
order to fit other formats, however, this characteristic
can be switched off and on by I
2
C control.
Fig. 21: I
2
S 16-bit mode (LR_SEL=0)
Fig. 22: I
2
S 32-bit mode (LR_SEL=0)
Note: Volume mute should be applied before changing
I
2
S mode in order to avoid audible clicks.
CLI
DAI
V
h
V
l
WSI
left 16-bit audio sample
right 16-bit audio sample
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
13 12 11 10
9 8
7
6
5
4
3
2
1
0
15 14
V
h
V
l
V
h
V
l
programmable delay bit
CLI
DAI
V
h
V
l
WSI
left 32-bit audio sample
right 32-bit audio sample
29 28 27 26 25 24
7
6
5
4
3
2
1
0
31 30
V
h
V
l
V
h
V
l
programmable delay bit
29 28 27 26 25 24 7
6
5
4
3
2
1
0
31 30
DAC 3550A
6
Micronas
2.2. Interpolation Filter
The interpolation filter increases the sampling rate by a
factor of 8. The characteristic for fs
audio
= 48 kHz is
shown in Fig. 23.
Fig. 23: 1
8 Interpolation filter; frequency range:
0...22 kHz
2.3. Variable Sample and Hold
The advantage of this system is that even at low sam-
ple frequencies the out-of-band noise is not scaled
down to audible frequencies.
2.4. 3rd-order Noise Shaper and Multibit DAC
The 3rd-order noise shaper converts the oversampled
audio signal into a 5-bit noise-shaping signal at a high
sampling rate. This technique results in extremely low
quantization noise in the audio band.
2.5. Analog Low-pass
The analog low-pass is a first order filter with a cut-off
frequency of approximately 1.4 MHz which removes
the high-frequency components of the noise-shaping
signal.
2.6. Input Select and Mixing Matrix
This block is used to switch between or mix the auxil-
iary inputs and the signals coming from the DAC. A
switch matrix allows to select between mono and ste-
reo mode as shown in Fig. 24.
Fig. 24: Switch matrix
Mono mode is realized by adding left and right
channel.
2.7. Postfilter Op Amps, Deemphasis Op Amps,
and Line-Out
This block contains the active components for the ana-
log postfilters and the deemphasis network. The
op amps and all I/O-pins for this block are shown in
Fig. 25.
0
5000
10000
15000
20000
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
dB
f/Hz
AUX1L
DAD
DAI
AUX1R
AUX2L
AUX2R
D/A
AUX_MS
24.576 MHz
FOUTR
FOUTL
-
-
-
-
WSI
INSEL_AUX2
INSEL_AUX1
INSEL_DAC
DAC 3550A
Micronas
7
Fig. 25: Postfilter op amps, deemphasis op amps, and line-out
2.8. Analog Volume
The analog volume control covers a range from
+18 dB to
-
75 dB. The lowest step is the mute posi-
tion.
Step size is split into a 3-dB and a 1.5-dB range:
-
75 dB...
-
54 dB:
3 dB step size
-
54 dB...+18 dB: 1.5 dB step size
2.9. Headphone Amplifier
The headphone amplifier output is provided at the
OUTL and OUTR pins connected either to stereo
headphones or a mono loudspeaker. The stereo head-
phones require external 47-
serial resistors in both
channels. If a loudspeaker is connected to these out-
puts, the power amplifier for the right channel must be
switched to inverse polarity. In order to optimize the
available power, the source of the two output amplifiers
should be identical, i.e. a monaural signal.
Please note, that if a speaker is connected, it should
strictly be connected as shown in Fig. 25. Never use
a separate connector for the speaker, because electro-
static discharge could damage the output transistors.
FOPL
A
V
O
L_R
FINL
FOPR
AV
O
L
_
L
IRP
A
-
-
-
-
AGNDC
VREF
Speaker
Headphones
OUTL
OUTR
15
0
F
1.5 k
47
15
0
F
FOUTL
FOUTR
from switch matrix
3.3
F/100 nF
+
+
+
AVSS
AVDD
32
to
C (HP-switch)
1.5 k
47
optional line-out
DEEML
For external components
,
DEEMR
16-32
FINR
see section "Applications"
For external components
,
see section "Applications"
Table 21: Volume Control
Volume/dB
AVOL
18.0 111000
16.5 110111
15.0
110110
13.5
110101
-
-
0.0
101100 (default)
-
1.5
101011
-
-
-
54.0
001000
-
57.0
000111
-
-
-
75
000001
Mute
000000
DAC 3550A
8
Micronas
2.10. Clock System
The advantage of the DAC 3550A clock system is that
no external master clock is needed. Most DACs need
256
fs
audio
, 384
fs
audio
, or at least an asynchro-
nous clock.
All internal clocks are generated by a PLL circuit,
which locks to the I
2
S bit clock (CLI). If no I
2
S clock is
present, the PLL runs free, and it is guaranteed that
there is always a clock to keep the IC controllable by
I
2
C.
The device can be set to two different modes:
Standard mode
MPEG mode
In the standard mode, I
2
C subaddressing is possible
(ADR0, ADR1, ADR2).
MPEG mode always uses ADR3.
To select the modes, the MCS1/MCS2 pins must be
set according to Table 22.
2.10.1. Standard Mode
without I
2
C
In standard mode, sample rates from 48 kHz to
32 kHz are handled without I
2
C control automati-
cally. The setting for this range is the default setting.
with I
2
C
Sample rates below 32 kHz require an I
2
C control to
set the PLL divider. This ensures that even at low
sample rates, the DAC 3550A runs at a high clock
rate. This avoids audible effects due to the noise-
shaping technique of the DAC 3550A. Sample rate
range is continuous from 8 to 50 kHz. The I
2
C set-
ting of low sample rates must follow according to
Section 3.6. "Control Registers" on page 15.
An additional mode allows automatic sample rate
detection. In this case, the clock oscillator is
required and must run at frequencies between
13.3 MHz to 17 MHz. This mode, however, does not
support continuous sample rates. Only the following
sample rates are allowed:
8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz,
24 kHz, 32 kHz, 44.1 kHz, 48 kHz
The sample rate detection allows a tolerance of
200 ppm at WSI.
If the oscillator is not used for automatic sample rate
detection, it can be used as a general-purpose clock
for the application. The frequency range in this case is
10 MHz to 25 MHz.
2.10.2. MPEG Mode
This mode should be used in conjunction with
MAS 3507D in MPEG player applications. In this case
a 14.725 MHz signal is needed to provide a clock for
the MAS 3507D and to allow an automatic sample rate
detection in the DAC 3550A. All MPEG sample rates
from 8 to 48 kHz can be detected. The internal pro-
cessing and the DAC itself are automatically adjusted
to keep constant performance throughout the entire
range. I
2
C control for sample rate adjustment is not
needed in this case. Register SR_REG[0:2] is locked
to SRC_A; see Section 3.6. "Control Registers" on
page 15.
The MPEG sample rates:
8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz,
24 kHz, 32 kHz, 44.1 kHz, 48 kHz
As in standard mode, the sample rate detection allows
a tolerance of
200 ppm at WSI.
Subaddressing is not possible in MPEG mode; this
means, in multi-DAC systems, only one DAC 3550A
can run in MPEG mode.
Table 22: Operation Modes
MCS1
MCS2
Mode
Sub-
address
Default
Sample
Rate
0
0
Stan-
dard
ADR0
3248 kHz
0
1
Stan-
dard
ADR1
3248 kHz
1
0
Stan-
dard
ADR2
3248 kHz
1
1
MPEG
ADR3
Automatic
DAC 3550A
Micronas
9
2.11. I
2
C Bus Interface
The DAC 3550A is equipped with an I
2
C bus slave
interface. The I
2
C bus interface uses one level of sub-
addressing: The I
2
C bus address is used to address
the IC. The subaddress allows chip select in multi DAC
applications and selects one of the three internal regis-
ters. The registers are write-only. The I
2
C bus chip
address is given below.
dev_write = $9A.
The registers of the DAC 3550A have 8- or 16-bit data
size; 16-bit registers are accessed by writing two 8-bit
data words.
Fig. 26: I
2
C bus protocols for write operations
2.12. Registers
In Section 3.6. "Control Registers" on page 15, a defi-
nition of the DAC 3550A control registers is shown. A
hardware reset initializes all control registers to 0. The
automatic chip initialization loads a selected set of reg-
isters with the default values given in the table.
All registers are write-only.
The register address is coded by 3 bits (RA1, RA0)
according to Table 23.
The mnemonics used in the DAC 3550A demo soft-
ware of Micronas are given in the last column.
2.13. Chip Select
Chip select allows to connect up to four DAC 3550A to
an I
2
C control bus. The chip subaddresses are defined
by the MCS1/MCS2 (Mode and Chip Select) pins. Only
in standard mode, chip select is possible. MPEG mode
always uses chip subaddress 3.
Register address and chip select are mapped into the
subaddress field in Table 24.
2.14. Reduced Feature Mode
If I
2
C control is not used, the IC is in the default mode
(see Section 3.6. "Control Registers" on page 15) after
start-up. Default Volume setting is 0 dB and digital
audio input is set to standard I
2
S. Sample rates from
32 kHz to 48 kHz are supported in this mode. Applica-
tions with no need for volume control or analog input
could use this mode.
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
1
1
0
1
0
8-bit I
2
C write access
SDA
SCL
1
0
S
P
Start
Stop
W
R
Ack
Nak
S
P
=
1
0
=
=
=
=
=
0
1
1 byte data
S
dev_write
Ack sub_adr
Ack
Ack P
S dev_write Ack sub_adr Ack 1 byte data Ack 1 byte data Ack P
16-bit I
2
C write access
Table 23: I
2
C Register Address
RA1
RA0
Mnemonics
0
1
SR_REG
1
0
AVOL
1
1
GCFG
Table 24: I
2
C Subaddress
7
6
5
4
3
2
1
0
MCS2
MCS1
RA1
RA0
DAC 3550A
10
Micronas
3. Specifications
3.1. Outline Dimensions
Fig. 31:
44-Pin Plastic Metric Quad Flat Package
(PMQFP44)
Weight approximately 0.4 g
Dimensions in mm
3.2. Pin Connections and Short Descriptions
NC = not connected, leave vacant
LV
= if not used, leave vacant
VSS = if not used, connect to VSS
X
= obligatory; connect as described in application
diagram
VDD = connect to VDD
D0024/2E
34
44
1
11
12
22
23
33
13.2
13.2
1.3
1.75
1.75
2.0
0.1
2.15
0.17
0.8
10
10
0.8
10 x 0.8 = 8
10 x 0.8 = 8
0.375
Pin
No.
Pin Name
Type
Connection
(if not used)
Short Description
1
AGNDC
IN/OUT
X
Analog reference Voltage
2
AVSS1
IN
X
VSS 1 for audio back-end
3
AVSS0
IN
X
VSS 0 for audio output amplifiers
4
NC
LV
Not connected
5
OUTL
OUT
LV
Audio Output: Headphone left or Speaker +
6
NC
LV
Not connected
7
OUTR
OUT
LV
Audio Output: Headphone right or Speaker
-
8
NC
LV
Not connected
9
AVDD0
IN
X
VDD 0 for audio output amplifiers
10
AVDD1
IN
X
VDD 1 for audio back-end
11
NC
LV
Not connected
12
XTI
IN
X
Quartz oscillator pin 1
13
XTO
IN/OUT
X
Quartz oscillator pin 2
14
CLKOUT
OUT
LV
Clock Output
15
SCL
IN/OUT
LV
I
2
C clock
DAC 3550A
Micronas
11
16
SDA
IN/OUT
LV
I
2
C data
17
VSS
IN
X
Digital VSS
18
VDD
IN
X
Digital VDD
19
MCS1
IN
X
I
2
C Chip Select 1
20
MCS2
IN
X
I
2
C Chip Select 2
21
DEECTRL
IN
VSS
Deemphasis on/off Control
22
NC
LV
Not connected
23
CLI
VSS
I
2
S Bit Clock
24
DAI
IN
VSS
I
2
S Data
25
WSI
IN
VSS
I
2
S Frame Identification
26
PORQ
IN
VDD
Power-On Reset, active-low
27
TESTEN
IN
X
Test Enable
28
NC
LV
Not connected
29
AUX2L
IN
LV
AUX2 left input for external analog signals (e.g. tape)
30
AUX2R
IN
LV
AUX2 right input for external analog signals (e.g. tape)
31
AUX1L
IN
LV
AUX1 left input for external analog signals (e.g. FM)
32
AUX1R
IN
LV
AUX1 right input for external analog signals (e.g. FM)
33
NC
LV
Not connected
34
DEEML
OUT
LV
Deemphasis Network Left
35
DEEMR
OUT
LV
Deemphasis Network Right
36
NC
LV
Not connected
37
FOUTL
OUT
X
Output to left external filter
38
FOPL
IN/OUT
X
Filter op amp inverting input, left
39
FINL
IN/OUT
X
Input for FOUTL or
filter op amp output (line out)
40
NC
LV
Not connected
41
FOUTR
OUT
X
Output to right external filter
42
FOPR
IN/OUT
X
Right Filter op amp inverting input
43
FINR
IN/OUT
X
Input for FOUTR or
filter op amp output (line out)
44
VREF
IN
X
Analog reference Ground
Pin
No.
Pin Name
Type
Connection
(if not used)
Short Description
DAC 3550A
12
Micronas
3.3. Pin Descriptions
3.3.1. Power Supply Pins
The DAC 3550A combines various analog and digital
functions which may be used in different modes. For
optimized performance, major parts have their own
power supply pins. All VSS power supply pins must be
connected.
VDD (18)
VSS (17)
The VDD and VSS power supply pair are connected
internally with all digital parts of the DAC 3550A.
AVDD0 (9)
AVSS0 (3)
AVDD0 and AVSS0 are separate power supply pins
that are exclusively used for the on-chip headphone/
loudspeaker amplifiers.
AVDD1 (10)
AVSS1 (2)
The AVDD1 and AVSS1 pins supply the analog audio
processing parts, except for the headphone/loud-
speaker amplifiers.
3.3.2. Analog Audio Pins
AGNDC (1)
Reference for analog audio signals. This pin is used as
reference for the internal op amps. This pin must be
blocked against VREF with a 3.3
F capacitor.
Note: The pin has a typical DC-level of 1.5/2.25 V. It
can be used as reference input for external op amps
when no current load is applied.
VREF (44)
Reference ground for the internal band-gap and bias-
ing circuits. This pin should be connected to a clean
ground potential. Any external distortions on this pin
will affect the analog performance of the DAC 3550A.
AUX1L (31)
AUX1R (32)
AUX2L (29)
AUX2R (30)
The AUX pins provide two analog stereo inputs. Auxil-
iary input signals, e.g. the output of a conventional
receiver circuit or the output of a tape recorder can be
connected with these inputs. The input signals have to
be connected by capacitive coupling.
FOUTL (37)
FOPL (38)
FINL (39)
FOUTR (41)
FOPR (42)
FINR (43)
Filter op amps are provided in the analog baseband
signal paths. These inverting op amps are freely
accessible for external use by these pins.
The FOUTL/R pins are connected with the buffered
output of the internal switch matrix. The FOPL/R-pins
are directly connected with the inverting inputs of the
filter op amps. The FINL/R pins are connected with the
outputs of the op amps. The driving capability of the
FOUTL/R pins is not sufficient for standard line output
signals. Only the FINL/R pins are suitable for line out-
put.
OUTL (5)
OUTR (7)
The OUTL/R pins are connected to the internal output
amplifiers. They can be used for either stereo head-
phones or a mono loudspeaker. The signal of the right
channel amplifier can be inverted for mono loud-
speaker operation.
Caution: A short circuit at these pins for more than a
momentary period may result in destruction of the
internal circuits.
3.3.3. Oscillator and Clock Pins
XTI (12)
XTO (13)
The XTI pin is connected to the input of the internal
crystal oscillator, the XTO pin to its output. Both pins
should be directly connected to the crystal and two
ground-connected capacitors (see application dia-
gram).
CLKOUT (14)
The CLKOUT pin provides a buffered output of the
crystal oscillator.
Caution: Power dissipation limit may be exceeded in
case of short to VSS or VDD.
CLI (23)
DAI (24)
WSI (25)
These three pins are inputs for the digital audio data
DAI, frame indication signal WSI, and bit clock CLI.
The digital audio data is transmitted in an I
2
S-compati-
ble format. Audio word lengths of 16 and 32 bits are
supported, as well as SONY and Philips I
2
S protocol.
SCL (15)
SDA (16)
SCL (serial clock) and SDA (serial data) provide the
connection to the serial control interface (I
2
C).
DAC 3550A
Micronas
13
3.3.4. Other Pins
TESTEN (27)
Test enable. This pin is for test purposes only and must
always be connected to VSS.
PORQ (26)
This pin may be used to reset the chip. If not used, this
pin must be connected to VDD.
DEEML (34)
DEEMR (35)
These pins connect an external analog deemphasis
network to the signal path in the analog back-end. This
connection can be switched on and off by an internal
switch which is controlled either by I
2
C or the
DEECTRL-pin.
DEECTRL (21)
If no I
2
C-control is used, deemphasis can be switched
on and off with this pin.
MCS1 (19)
MCS2 (20)
Mode select pins to select MPEG, Standard Mode, and
I
2
C subaddress.
3.4. Pin Configuration
Fig. 32: 44-pin PMQFP package
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
10 11
33 32 31 30 29 28 27 26 25 24 23
DEEML
DEEMR
NC
FOUTL
FOPL
FINL
NC
FOUTR
FOPR
FINR
VREF
NC
DEECTRL
MCS2
MCS1
VDD
VSS
SDA
SCL
CLKOUT
XTO
XTI
AUX1R
AUX1L
AUX2R
AUX2L
NC
NC
TESTEN
PORQ
WSI
DAI
CLI
AVSS1
AVSS0
NC
OUTL
NC
AGNDC
OUTR
NC
AVDD0
AVDD1
NC
DAC 3550A
DAC 3550A
14
Micronas
3.5. Pin Circuits
Fig. 33: Input/Output Pins SDA, SCL
N
VSS
VDD
Fig. 34: Input Pins DAI, WSI, PORQ, CLI
Fig. 35: Output Pin CLKOUT
P
VDD
N
VSS
Fig. 36: Pins FINR, FOPR, FINL, FOPL,
DEEML, DEEMR
AGNDC
FOPn
FINn
FOUTn
ext. filter network
DEEM
(DEEMCTRL)
Fig. 37: Pins AGNDC, VREF
125 k
AVSS0/1
AGNDC
VREF
Fig. 38: Output Pins FOUTL, FOUTR
AGNDC
FOUTn
Fig. 39: Input/Output Pins XTI, XTO
500 k
XTI
XTO
AUXnL
AUXnR
Fig. 310: Input Pins AUX1R, AUX1L, AUX2R,
AUX2L, AGNDC
AGNDC
sel/nonsel
sel/nonsel
mono/stereo
mono/stereo
AGNDC
Fig. 311: Output Pins OUTL, OUTR
OUTn
AGNDC
Fig. 312: Input Pins MCS1, MCS2, DEECTRL
VDD
VSS
DAC 3550A
Micronas
15
3.6. Control Registers
I
2
C Sub-
address
(hex)
Number
of Bits
Mode
Function
Default
Values
(hex)
Name
SAMPLE RATE CONTROL SR_REG
01
8
w
sample rate control
bit[7:5]
not used, set to 0
bit[4]
L/R-bit
0
(WSI = 0
left channel)
1)
1
(WSI = 0
right channel)
1)
bit[3]
Delay-Bit
0 No Delay
1 1 bit Delay
bit[2:0]
sample rate control
000 32
-
48 kHz
001 26
-
32 kHz
010 20
-
26 kHz
011 14
-
20 kHz
100 10
-
14 kHz
101 8
-
10 kHz
11x
2)
autoselect
0H
LR_SEL
SP_SEL
SRC_48
SRC_32
SRC_24
SRC_16
SRC_12
SRC_8
SRC_A
ANALOG VOLUME AVOL
02
16
w
audio volume control
bit[15]
not used, set to 0
bit[14]
deemphasis on/off
0 deemphasis off
1 deemphasis on
bit[13:8] analog audio volume level left:
000000
mute
000001
-
75 dB
101100
+0 dB (default)
111000
+18 dB
bit[7:6]
not used, set to 0
bit[5:0]
analog audio volume level right
000000
mute
000001
-
75 dB
101100
+0 dB (default)
111000
+18 dB
2C2CH
DEEM
AVOL_L
AVOL_R
1)
see Fig. 21 and Fig. 22 on page
5
2)
don't care
DAC 3550A
16
Micronas
Global Configuration GCFG
03
8
w
global configuration
bit[7]
not used, set to 0
bit[6]
select 3V-5 V mode
0
3 V
1
5 V
bit[5]
power-mode
0
normal
1
low power
bit[4]
AUX2 select
0
AUX2 off
1
AUX2 on
bit[3]
AUX1 select
0
AUX1 off
1
AUX1 on
bit[2]
DAC select
0
DAC off
1
DAC on (default)
bit[1]
aux-mono/stereo
0
stereo
1
mono
bit[0]
invert right power amplifier
0
not inverted
1
inverted
4H
SEL_53V
PWMD
INSEL_AUX2
INSEL_AUX1
INSEL_DAC
AUX_MS
IRPA
I
2
C Sub-
address
(hex)
Number
of Bits
Mode
Function
Default
Values
(hex)
Name
DAC 3550A
Micronas
17
3.7. Electrical Characteristics
3.7.1. Absolute Maximum Ratings
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
Symbol
Parameter
Pin
Name
Min.
Max.
Unit
T
A
Ambient Operating Temperature
1)
0
70
C
T
S
Storage Temperature
-
40
125
C
P
max
Power Dissipation
500
mW
V
SUPA
Analog Supply Voltage
2)
AVDD0/1
-
0.3
6
V
V
SUPD
Digital Supply Voltage
VDD
-
0.3
6
V
V
Idig1
Input Voltage, digital inputs
MCS1,
MCS2,
DEECTRL
-
0.3
V
SUPD
+ 0.3
V
V
Idig2
Input Voltage, digital inputs
WSI,
CLI,
DAI,
PORQ,
SCL,
SDA
-
0.3
6
V
I
Idig
Input Current, all digital inputs
-
5
+5
mA
V
Iana
Input Voltage, all analog inputs
-
0.3
V
SUPA
+ 0.3
V
I
Iana
Input Current, all analog inputs
-
5
+5
mA
I
Oaudio
Output Current, audio output
3)
OUTL/R
-
0.2
0.2
A
I
Odig
Output Current, all digital outputs
4)
-
10
10
mA
1)
=standard temperature range, DAC 3550A tested in extended temperature range on request
2)
Both have to be connected together!
3)
These pins are NOT short-circuit proof!
4)
Total chip power dissipation must not exceed absolute maximum rating
DAC 3550A
18
Micronas
3.7.2. Recommended Operating Conditions
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Temperature Ranges and Supply Voltages
T
A
Ambient Temperature Range
1)
0
70
C
V
SUPA1
Analog Audio Supply Voltage
AVDD0/1
3.0
2)
3.3
5.5
V
V
SUPD
Digital Supply Voltage
VDD
2.7
3.3
5.5
V
Relative Supply Voltages
V
SUPA
Analog Audio Supply Voltage in
relation to the Digital Supply Volt-
age
AVDD0/1
V
SUPD
-
0.25 V
5.5 V
Analog Reference
C
AGNDC1
Analog Reference Capacitor
AGNDC
1.0
3.3
F
C
AGNDC2
Analog Reference Capacitor
AGNDC
10
nF
Analog Audio Inputs
V
AI
Analog Input Voltage AC,
SEL_53V = 0
AUXnL/R
3)
0.35
0.7
V
rms
V
AI
Analog Input Voltage AC,
SEL_53V = 1
AUXnL/R
3)
0.525
1.05
V
rms
Analog Filter Input and Output
Z
AFLO
Analog Filter Load Output
4)
FOUTL/R
7.5
6
k
pF
Z
AFLI
Analog Filter Load Input
4)
FINL/R
5.0
7.5
k
pF
Analog Audio Output
Z
LO
Audio Line Output
5)
(680
Series Resistor required)
FINL/R
10
1.0
k
nF
Z
AOL_HP
Analog Output Load HP
(47
Series Resistor required)
OUTL/R
32
400
pF
Z
AOL_SP
Analog Output Load SP (bridged)
OUTL/R
32
50
pF
Analog Output Load SP (Stereo)
16
100
pF
1)
=standard temperature range, DAC 3550A tested in extended temperature range on request
2)
typically operable down to 2.7 V, without loss in performance
3)
n = 1 or 2
4)
Please refer to Section 4.2. "Recommended Low-Pass Filters for Analog Outputs" on page 25.
5)
Please refer to Section 4.1. "Line Output Details" on page 25.
DAC 3550A
Micronas
19
I
2
C Input
f
I2C1
I
2
C Clock Frequency, I
2
S active
SCL
400
kHz
f
I2C2
I
2
C Clock Frequency, I
2
S inactive
100
kHz
Digital Inputs
V
IH
Input High Voltage
CLI,
WSI,
DAI,
PORQ,
SCL,
SDA
0.5
VDD
V
V
IL
Input Low Voltage
0.2
VDD
V
Quartz Characteristics
F
P
Load Resonance Frequency
at C
l
= 20 pF
13.3
14.725
17
MHz
R
EQ
Equivalent Series Resistance
12
30
C
0
Shunt (parallel) Capacitance
3
5
pF
Load at CLKOUT Output
C
load
Capacitance
CLKOUT
0
50
pF
1)
=standard temperature range, DAC 3550A tested in extended temperature range on request
2)
typically operable down to 2.7 V, without loss in performance
3)
n = 1 or 2
4)
Please refer to Section 4.2. "Recommended Low-Pass Filters for Analog Outputs" on page 25.
5)
Please refer to Section 4.1. "Line Output Details" on page 25.
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
DAC 3550A
20
Micronas
3.7.3. Characteristics
At T
A
= 0 to 70
C
*
, V
SUPD
= 2.7 to 5.5 V, V
SUPA
= 3.0 to 5.5 V; typical values at T
J
= 27
C, V
SUPD
= V
SUPA
= 3.3 V,
quartz frequency = 14.725 MHz, duty cycle = 50 %, positive current flows into the IC
* =standard temperature range, DAC 3550A tested in extended temperature range on request
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Digital Supply
I
VDD
Current Consumption
VDD
5
mA
V
SUPD
=3 V
I
VDD
Current Consumption
VDD
8
mA
V
SUPD
=5 V
Digital Input Pin
Leakage
I
I
Input Leakage Current
CLI, WSI,
DAI,
TESTEN,
PORQ,
DEECTRL,
MCS1/2
1
A
V
GND
V
I
V
SUP
Digital Output Pin
Clock Out
V
OH
Output High Voltage
CLKOUT
V
SUPD
-
0.3
V
no load at output
V
OL
Output Low Voltage
0.3
V
I
2
C Bus
R
on
Output Impedance
SCL, SDA
60
I
load
= 5 mA,
V
SUPD
= 2.7 V
Analog Supply
I
AVDD
Current Consumption
Analog Audio, SEL_53V = 0
AVDD0/1
8
1.5
11
mA
mA
PWMD = 0, Mute
PWMD = 1, Mute
SEL_53V = 1
11
2
15
mA
mA
PWMD = 0, Mute
PWMD = 1, Mute
PSRR
AA
Power Supply Rejection
Ratio for Analog Audio
Output
AVDD0/1,
OUTL/R
50
dB
1 kHz sine at
100 mV
rms
20
dB
100 kHz sine at
100 mV
rms
PSRR
LO
Power Supply Rejection
Ratio for Line Output
AVDD0/1,
FINL/R
50
dB
1 kHz sine at
100 mV
rms
40
dB
100 kHz sine at
100 mV
rms
Reference Frequency Generation
V
DCXTI
DC Voltage at Oscillator
Pins
XTI/O
0.5 *
V
SUPA
V
C
LI
Input Capacitance at
Oscillator Pin
XTI/O
3
pF
Vxtalout
Voltage Swing at Oscillator
Pins, pp
XTI/O
60
100
%
VSUPA
Oscillator Start-Up Time
50
ms
AV
DD
/V
DD
2.5 V
DAC 3550A
Micronas
21
Analog Audio
V
AO
Analog Output Voltage AC
OUTL/R,
FOUTL/R,
FINL/R
0.65
0.7
0.75
V
rms
SEL_53V = 0,
R
L
> 5 k
,
Analog Gain = 0 dB
Input = 0 dBFS digital
1.0
1.05
1.1
V
rms
SEL_53V = 1
G
AUX
Gain from Auxiliary Inputs to
Line Outputs
AUXnL/R,
FINL/R
-
0.5
0
0.5
dB
f = 1 kHz, sine wave,
R
L
> 5 k
0.5 V
rms
to AUXnL/R
P
HP
Output Power (Headphone)
OUTL/R
5
mW
SEL_53V = 0,
R
L
= 32
,
Analog Gain = +3 dB,
distortion < 1%,
external 47
series
resistor required
12
mW
SEL_53V = 1
P
SP
Output Power (Speaker)
OUTL/R
120
mW
R
L
= 32
(bridged)
,
Analog Gain = +3 dB,
distortion < 10%,
SEL_53V = 0, IRPA = 1
280
mW
SEL_53V = 1
G
AO
Analog Output Gain
Setting Range
OUTL/R
-
75
18
dB
dG
AO1
Analog Output Gain
Step Size
OUTL/R
3.0
dB
Analog Gain:
-
75 dB...
-
54 dB
dG
AO2
Analog Output Gain
Step Size
OUTL/R
1.5
dB
Analog Gain:
dB
32 bit I
2
S, SEL_53V = 1
103
dBA
32 bit I
2
S, SEL_53V = 1
SNR
2
Signal-to-Noise Ratio
OUTL/R
58
62
dB
R
L
32
(external
47
series resistor
required)
BW = 20 Hz..0.5 fs
unweighted
Analog Gain=
-
40.5 dB,
Input =
-
3 dBFS
Lev
Mute
Mute Level
OUTL/R
-
110
dBV
BW = 20 Hz...22 kHz
unweighted, no digital
input signal,
Analog Gain = Mute
R
D/A
D/A Pass Band Ripple
OUTL/R,
FOUTL/R
-
0.1
dB
0...0.446 fs
(no external filters
used)
A
D/A
D/A Stop Band Attenuation
40
dB
0.55...7.533 fs
(no external filters
used)
BW
AUX
Bandwidth for
Auxiliary Inputs
AUXnL/R,
FINL/R
760
kHz
(no external filters
used)
THD
ALO
Total Harmonic Distortion
from Auxiliary Inputs to
Line Outputs
AUXnL/R,
FINL/R
0.01
%
BW = 20 Hz... 22 kHz,
unweighted,
R
L
> 5 k
Input 1 kHz at 0.5 V
rms
R
dec
612
THD
DLO
Total Harmonic Distortion
(D/A converter to Line
Output)
FINL/R
0.01
%
BW = 20 Hz... 0.5 fs,
unweighted,
R
L
> 5 k
Input 1 kHz at
-
3 dBFS
R
dec
612
THD
HP
Total Harmonic Distortion
(Headphone)
OUTL/R
0.05
%
BW = 20 Hz... 0.5 fs,
unweighted, R
L
32
(47
series resistor
required),
Analog Gain = 0 dB,
Input 1 kHz at
-
3 dBFS
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
DAC 3550A
Micronas
23
THD
SP
Total Harmonic Distortion
(Speaker)
OUTL/R
0.5
%
BW = 20 Hz...0.5 fs,
unweighted, R
L
32
(speaker bridged),
Analog Gain = 0 dB,
Input 1 kHz at
-
3 dBFS
XTALK
LO
Cross-Talk
Left/Right Channel
(Line Output)
AUXnL/R,
FOUTL/R,
FINL/R
-
70
-
80
dB
f = 1 kHz, sine wave,
R
L
> 7.5 k
Analog Gain = 0 dB,
Input =
-
3 dBFS or
0.5 V
rms
to AUXnL/R
XTALK
HP
Crosstalk
Left/Right Channel
(Headphone)
OUTL/R
-
70
-
80
dB
f = 1 kHz, sine wave,
OUTL/R: R
L
32
(47
series resistor
required)
Analog Gain = 0 dB,
Input =
-
3 dBFS or
0.5 V
rms
to AUXnL/R
XTALK
2
Crosstalk between
Input Signal Pairs
AUXnL/R
-
70
-
80
dB
f = 1 kHz, sine wave,
FOUTL/R: R
L
> 7.5 k
OUTL/R: R
L
32
(47
series resistor
required)
Analog Gain = 0 dB,
Input =
-
3 dBFS and
0.5 V
rms
to AUXnL/R
V
AGNDC
Analog Reference Voltage
AGNDC
1.5
V
SEL_53V = 0
R
L
>>
10 M
,
referred to VREF
2.25
V
SEL_53V = 1
R
L
>>
10 M
,
referred to VREF
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
DAC 3550A
24
Micronas
R
IAUX
Input Resistance at
Input Pins
AUXnL/R
12.1
11.6
15
17.9
19.0
k
k
T
J
=
27
C
T
A
=
0 to 70
C
1)
Input selected,
PWMD = 0
i =
10
A,
referred to VREF
24.2
23.3
30
35.8
37.9
k
k
T
J
=
27
C
T
A
=
0 to 70
C
1)
Input not selected
i =
10
A,
referred to VREF
R
OOUT
Output Resistance at
Output Pins
OUTL/R
700
T
J
=
27
C
PWMD = 1
i =
200
A,
referred to VREF
R
OFILT
Output Resistance of
Filter Pins
FINL
15
k
PWMD = 1, Mute
i =
10
A,
referred to VREF
FINR
11.25
k
V
OffI
Offset Voltage at Input Pins
AUXnL/R
-
20
20
mV
referred to AGNDC
V
OffO
Offset Voltage at
Output Pins
OUTL/R
-
10
10
mV
Mute
referred to AGNDC
V
OffFO
Offset Voltage at
Filter Output Pins
FOUTL/R
-
20
20
mV
PWMD = 0,
referred to AGNDC
V
OffFI
Offset Voltage at
Filter Input Pins
FINL/R
-
20
20
mV
PWMD = 0,
referred to AGNDC
dV
DCPD
Difference of DC Voltage at
Output Pins after Back-end
Low Power Sequence
OUTL/R
-
10
10
mV
Analog Gain = Mute,
PWMD switched from 0
to 1
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
DAC 3550A
Micronas
25
4. Applications
4.1. Line Output Details
Fig. 41: Use of FINL/R as Line Outputs
4.2. Recommended Low-Pass Filters for Analog
Outputs
*
Fig. 42: 1st-order low-pass filter
Fig. 43: 2nd-order low-pass filter
Fig. 44: 3rd-order low-pass filter
Table 41: Load at FINL/R when used as Line Output
for external amplifier
Filter Order
R
dec
R
in
1st, 2nd, 3rd
680
> 10 k
R
dec
: Resistor used for decoupling C
line
from
FINL(R) to achieve stability
C
line
: Capacitive load according to e.g. cable,
amplifier
R
in
: Input resistance of amplifier
* without deemphasis circuit
Table 42: Attenuation of 1st-order low-pass filter
Frequency
Gain
24 kHz
-
2.2 dB
30 kHz
-
3.0 dB
FINL(R)
AVSS
C
line
R
dec
R
in
330 pF
15 k
15 k
1st-order
-
FINL(R)
FOPL(R)
FOUTL(R)
Table 43: Attenuation of 2nd-order low-pass filter
Frequency
Gain
24 kHz
-
1.5 dB
30 kHz
-
3.0 dB
Table 44: Attenuation of 3rd-order low-pass filter
Frequency
Gain
18 kHz
0.17 dB
24 kHz
-
0.23 dB
30 kHz
-
3.00 dB
11 k
220 pF
11 k
11 k
1.0 nF
-
FINL(R)
FOPL(R)
FOUTL(R)
2nd-order
AVSS
-
FINL(R)
FOPL(R)
FOUTL(R)
15 k
120 pF
7.5 k
7.5 k
1.8 nF
1.8 nF
7.5 k
3rd-order
AVSS
DAC 3550A
26
Micronas
4.3. Recommendations for Filters and Deemphasis
Fig. 45: General circuit schematic
4.4. Recommendations for MegaBass Filter
without Deemphasis plus 1st-order low-pass
Fig. 46: General circuit schematic
Table 45: Resistor and Capacitor values
1st order
2nd order
3rd order
R1 (k
)
0
7.5
C1 (pF)
open
560
R2 (k
)
18
11
7.5
C2 (pF)
open
1000
270
R3 (k
)
18
11
15
C3 (pF)
180
180
82
R4 (k
)
0
11
7.5
R5 (k
)
18
22
22
C4 (nF)
1.8
1.0
1.0
-
FINL(R)
FOPL(R)
FOUTL(R)
R3
C3
R2
R4
C2
C1
R1
AVSS
R5
C4
DEEML(R)
Table 46: Resistor and Capacitor values
DC-Gain = 10 dB
fc1
= 100 Hz
fc2
= 330 Hz
R1 (k
)
13
C1 (nF)
47
R2 (k
)
0
R3 (k
)
15
R4 (k
)
15
R5 (k
)
13
C2 (nF)
47
C3 (pF)
180
-
FINL(R)
FOPL(R)
FOUTL(R)
R4
R2
R3
C2
C1
R1
R5
ON
OFF
C3
DAC 3550A
Micronas
27
4.5. Power-up/down Sequence
In order to get a click-free power-up/down characteris-
tic, it is recommended to use the following sequences:
Pin Name
Min.
Typ.
Max.
Unit
Temperature Ranges and Supply Voltages
T
A
Ambient Temperature Range
1)
0
70
C
V
SUPA1
Analog Audio Supply Voltage
AVDD0/1
3.0
2)
3.3
5.5
V
V
SUPD
Digital Supply Voltage
VDD
2.7
3.3
5.5
V
Relative Supply Voltages
V
SUPA
Analog Audio Supply Voltage in
relation to the Digital Supply Volt-
age
AVDD0/1
V
SUPD
-
0.25 V
5.5 V
Analog Reference
C
AGNDC1
Analog Reference Capacitor
AGNDC
1.0
3.3
F
C
AGNDC2
Analog Reference Capacitor
AGNDC
10
nF
Analog Audio Inputs
V
AI
Analog Input Voltage AC,
SEL_53V = 0
AUXnL/R
3)
0.35
0.7
V
rms
V
AI
Analog Input Voltage AC,
SEL_53V = 1
AUXnL/R
3)
0.525
1.05
V
rms
Analog Filter Input and Output
Z
AFLO
Analog Filter Load Output
4)
FOUTL/R
7.5
6
k
pF
Z
AFLI
Analog Filter Load Input
4)
FINL/R
5.0
7.5
k
pF
Analog Audio Output
Z
LO
Audio Line Output
5)
(680
Series Resistor required)
FINL/R
10
1.0
k
nF
Z
AOL_HP
Analog Output Load HP
(47
Series Resistor required)
OUTL/R
32
400
pF
Z
AOL_SP
Analog Output Load SP (bridged)
OUTL/R
32
50
pF
Analog Output Load SP (Stereo)
16
100
pF
1)
=standard temperature range, DAC 3550A tested in extended temperature range on request
2)
4.5.1. Power-up Sequence
1. Start VDD from 0 to +3.3 V and start AVDD0/1 from
0 to +3.3 V/+5 V. AVDD should not ramp up faster
than VDD.
2. Release PORQ from 0 to AVDD0/1.
3. Send I2C: volume, input select, speaker, ... optional.
4. Start I2S data.
The most important point is: PORQ has to ramp up
after AVDD0/1, simply by using a 10-k
pull-up resis-
tor to AVDD0/1 and a 2.2-nF capacitor to ground. No
further control on PORQ is needed.
Fig. 47: Power-up sequence
4.5.2. Power-down Sequence
1. Stop I2S data.
2. Send I2C: LOW POWER.
3. Switch VDD, AVDD0/1 to 0.
VDD
AVDD
PORQ
90% VDD
90 % AVDD
<0.2
VDD
<30 ms
0.7
AVDD
DAC
3
550
A
28
M
i
c
r
onas
4
.
6
.
T
y
pic
a
l Applic
a
t
ions
Fig. 4
8:
A
ppl
ic
ati
on
ci
r
c
ui
t s
c
h
e
ma
tic
1
:
St
and
ar
d ap
pli
c
ati
on wi
th
anal
og
dee
mph
a
s
i
s. O
s
c
i
l
l
a
t
or
no
t ne
ede
d.
n
A
DAC
3
5
50A
M
i
c
r
o
nas
29
Fig. 4
9:
A
ppl
ic
at
ion
ci
r
c
u
i
t s
c
hem
ati
c
2
:
MP
E
G
appl
ic
at
ion
wit
h
an
al
og M
ega
bas
s
and
14.
725
MHz
c
r
ys
ta
l
n
A
A
DAC 3550A
30
Micronas
Fig. 410: MPEG Layer-3 Player
Fig. 411: CD-Player with FM-Radio
Fig. 412: ADR Receiver
MAS
ROM, CD-ROM,
RAM, Flash Mem. ..
DAC
Host
3507D
3550A
(PC, Controller)
I
2
S
line out
demand signal
MPEG clock
MPEG bit stream
CLKOUT
14.725 MHz
Optical
DSP
I
2
S
line out
CLKOUT
DAC
3550A
DAC
3550A
&
SERVO
Pickup
FM-TUNER
DEMOD
R
L
384
fs
I
2
S
line-out
DAC
3550A
DAC
3550A
TUNER
ADRBUS
DATA
BCLK
LRCLK
32 kHz
18.432 MHz
18.432 MHz
DRP
3510 A
MSP
34xx
DAC 3550A
Micronas
31
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
DAC 3550A
32
Micronas
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com
Printed in Germany
Order No. 6251-467-1DS
5. Data Sheet History
1. Final data sheet: "DAC 3550A Stereo Audio DAC,
Edition July 23, 1999, 6251-467-1DS. First release of
the final data sheet.
MICRONAS INTERMETALL
page 1 of 3
Subject:
Data Sheet Concerned:
Supplement:
Edition:
Preliminary Data Sheet Supplement
New Package for DAC 3550A: 49-Ball Plastic Ball Grid Array (PBGA49)
1. Outline Dimensions
Fig. 1:
49-Ball Plastic Ball Grid Array
(PBGA49)
Dimensions in mm
D0026/1E
New Package for DAC 3550A
DAC 3550A
6251-467-1PD, Edition April 23, 1999
No. 2/ 6251-467-1PDS
May 18, 1999
DAC 3550A
DAC 3550A
PRELIMINARY DATA SHEET SUPPLEMENT
page 2 of 3
MICRONAS INTERMETALL
2. Pin Connections and Short Descriptions
NC = not connected, leave vacant
X
= obligatory; connect as described
in application circuit diagram
LV
= if not used, leave vacant
VSS = if not used, connect to VSS
VDD = connect to VDD
Unassigned pins must be left vacant.
Pin No. / Pin ID
Pin Name
Type
Connection
(If not used)
Short Description
PMQFP
44-pin
PBGA
49-ball
1
B5
AGNDC
BID
X
Analog reference voltage
2
A6
AVSS1
SUPPLY
X
VSS 1 for audio back-end
3
B4
AVSS0
SUPPLY
X
VSS 0 for audio output amplifiers
4
NC
LV
Not connected
5
C4
OUTL
OUT
LV
Audio output:
headphone left or speaker +
6
NC
LV
Not connected
7
A3
OUTR
OUT
LV
Audio output:
headphone right or Speaker
-
8
NC
LV
Not connected
9
A2
AVDD0
SUPPLY
X
VDD 0 for audio output amplifiers
10
A1
AVDD1
SUPPLY
X
VDD 1 for audio back-end
11
NC
LV
Not connected
12
C3
XTI
IN
X
Quartz oscillator pin 1
13
C2
XTO
BID
X
Quartz oscillator pin 2
14
D2
CLKOUT
OUT
LV
Clock output
15
C1
SCL
BID
LV
I
2
C clock
16
D3
SDA
BID
LV
I
2
C data
17
D1
VSS
SUPPLY
X
Digital VSS
18
E1
VDD
SUPPLY
X
Digital VDD
19
F2
MCS1
IN
X
I
2
C chip sSelect 1
20
F1
MCS2
IN
X
I
2
C chip select 2
21
G1
DEECTRL
IN
VSS
Deemphasis on/off control
22
NC
LV
Not connected
23
E3
CLI
VSS
I
2
S bit clock
24
F3
DAI
IN
VSS
I
2
S data
25
F4
WSI
IN
VSS
I
2
S frame identification
26
G4
PORQ
IN
VDD
Power-on-reset, active-low
PRELIMINARY DATA SHEET SUPPLEMENT
DAC 3550A
MICRONAS INTERMETALL
page 3 of 3
27
F5
TESTEN
IN
X
Test enable
28
NC
LV
Not connected
29
G5
AUX2L
IN
LV
AUX2 left input for external analog
signals (e.g. tape)
30
F6
AUX2R
IN
LV
AUX2 right input for external analog
signals (e.g. tape)
31
G6
AUX1L
IN
LV
AUX1 left input for external analog
signals (e.g. FM)
32
G7
AUX1R
IN
LV
AUX1 right input for external analog
signals (e.g. FM)
33
NC
LV
Not connected
34
E5
DEEML
OUT
LV
Deemphasis network, left
35
E6
DEEMR
OUT
LV
Deemphasis network, right
36
NC
LV
Not connected
37
F7
FOUTL
OUT
X
Output to left external filter
38
D6
FOPL
BID
X
Filter op amp inverting input, left
39
E7
FINL
IN/OUT
X
Input for FOUTL or
filter op amp output (line out)
40
NC
LV
Not connected
41
D7
FOUTR
OUT
X
Output to right external filter
42
C6
FOPR
BID
X
Right filter op amp inverting input
43
C7
FINR
IN/OUT
X
Input for FOUTR or
filter op amp output (line out)
44
A7
VREF
IN
X
Analog reference ground
Pin No. / Pin ID
Pin Name
Type
Connection
(If not used)
Short Description
PMQFP
44-pin
PBGA
49-ball
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