DRX 8872C

DATA SHEET

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Micronas

Contents, continued

Page

Section

Title

Introduction

1.1.

Features

1.2.

Applications

1.3.

DVB-T Front-End Application

Functional Description

2.1.

Analog input

2.2.

AGC

2.3.

Crystal

2.4.

Manufacturing Guidelines

2.5.

Lock Indication

2.5.1.

Host Interface

2.6.

MPEG2 Output

Application Programming Interface (API)

3.1.

Initialize System Settings

3.1.1.

SP7_LoadMicrocode

3.1.2.

SP7_LoadImage

3.1.3.

SP7_SetSamplingMode

3.1.4.

SP7_SetAGCParams

3.1.5.

SP7_SetOutputEnable

3.1.6.

SP7_GetOutputEnable

3.1.7.

SP7_TSOutput

3.1.8.

SP7_LCKMode

3.2.

Setup Signal Parameters

3.2.1.

SP7_SetChannelParams

3.2.2.

SP7_GetChannelParams

3.2.3.

SP7_SetOfdmParams

3.2.4.

SP7_GetOfdmParams

3.2.5.

SP7_Start

3.3.

Selecting Channels

3.3.1.

SP7_Tune_init

3.3.2.

SP7_Tune_properties

3.3.3.

SP7_Tune_program

3.3.4.

SP7_Tune_error

3.3.5.

SP7_Tune_get_freq

3.3.6.

SP7_EnableTunerAccess

3.3.7.

SP7_LockingStatus

3.4.

Monitor Channel Quality

3.4.1.

SP7_GetSN

3.4.2.

SP7_GetConstellationDiagram

3.4.3.

SP7_GetBer

3.4.4.

SP7_GetTpsInfo

3.5.

Commands and other Useful Functions

3.5.1.

SP7_Reboot

3.5.2.

SP7_Reset

3.5.3.

SP7_SysReset

Contents, continued

Page

Section

Title

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DRX 8872C

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Nov, 28, 2003; 6251-618-2DS

3.5.4.

SP7_Restart

3.5.5.

SP7_Halt

3.5.6.

SP7_Nop

3.5.7.

SP7_Wreg

3.5.8.

SP7_Rreg

3.5.9.

SP7_Wvar

3.5.10.

SP7_Rvar

3.6.

Interrupts and Events

3.6.1.

SP7_ReadIrq

3.6.2.

SP7_PollEvent

Specifications

4.1.

Outline Dimensions

4.2.

Pin Connections and Short Descriptions

4.3.

Pin Configurations

4.4.

Electrical Characteristics

4.4.1.

Absolute Maximum Ratings

4.4.2.

Recommended Operating Conditions

4.4.2.1.

General Recommended Operating Conditions

4.4.3.

Characteristics

4.4.3.1.

DC Electrical Characteristics

4.4.3.2.

Temperature Ratings

4.4.3.3.

ADC Parameters

Appendix A API Data Types

5.1.

Basic Data Types

5.2.

Chip-specific Data Types

Appendix B API Required Platform Functions

6.1.

PC Platforms Running Windows 98, NT, 2000, and XP

6.2.

Other platforms

6.2.1.

SP7_I2C_Write

6.2.2.

SP7_I2C_Read

6.2.3.

I2ctest.c

Data Sheet History

DRX 8872C

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Micronas

COFDM Demodulator/FEC

1. Introduction

The DRX 8872C is an ETS 300 744-compliant inte-
grated demodulator and forward error corrector (FEC)
for DVB-T receivers.

The IC accepts 1

and 2

IF COFDM signals as input

data. The 1

IF sampling option further decreases sys-

tem cost. The incoming signal is sampled by a high-
performance 10-bit A/D converter. The internal micro-
processor performs the detection of the COFDM
parameters and configuration of the demodulator auto-
matically, without any interaction with the host proces-
sor. The error correction unit corrects remaining errors
and outputs a DVB-compliant MPEG-2 transport
stream.

The DRX 8872C can cope with very severe channel
distortions due to its state-of-the-art channel estima-
tion unit.

1.1. Features

Excellent performance in presence of echoes, co-

channel and AWGN

Integrated microprocessor to perform autonomous

operation

Flexible concept by "micro-coded" algorithms

Detection of channel type (echoes, co-channel,

gaussian noise ...) via channel classificator function

Very suitable for SFN operation

Complete software API for smooth integration

Integrated 10-bit ADC

and 2

IF COFDM supported

No VCXO required because of digital resampling

techniques

Quick synchronization after channel switch

(<70 ms)

6 MHz, 7 MHz, and 8 MHz channel-

compliant with only one crystal

Supports all DVB-T modes including hierarchical

modulation

Digital AFC

BER, S/N, packet error, constellation diagram, lock

indication readout

Serial or parallel MPEG-2 transport stream output

Supply voltage: 2.5 V (core); 3.3V (I/O)

Control: via serial bus

Package: 80-pin PTQFP

Ambient operating temperature:

0 °C to +70 °C

IEEE 1149.1 boundary scan

1.2. Applications

IDTV receivers

Set-top boxes

Network Interface Modules (NIMs)

PC-TV cards

Fig. 11: Block diagram of the DRX 8872C

AGC

1st IF

or 2nd IF OFDM

MPEG 2

Host

Interface

Output

Control

Boundary

Scan

Reed-

Solomon

Decoder

Viterbi

Decoder

Pilot

Processor

Inner

De-inter-

leaver

Outer

De-inter-

leaver

Signal

Processing

8K/2K

FFT/

Phase

Rotation

Channel

Estimation

Data

Demulti-

plexer

Diversity

MUX

ADC

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DRX 8872C

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1.3. DVB-T Front-End Application

Fig. 12 shows a block diagram of a typical DVB-T
front-end using the DRX 8872C at the first intermedi-
ate frequency. The tuner converts the COFDM signal
to a first intermediate frequency of about 36 MHz
which is then band-pass-filtered by a SAW filter stage.
The SAW filter is followed by a differential-in / differen-
tial-out IF amplifier.

This chapter describes in detail how to connect the
DRX 8872C in such an application.

Fig. 12: Front-end block diagram for the DRX 8872C

61 MHz

Down-

Converter

Gain

SAW

Gain

IF-AGC

ADC

1 IF

~36 MHz

DRX 8872C

COFDM

MPEG2

Transport Stream

RF-AGC

DRX 8872C

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2. Functional Description

2.1. Analog input

The input signal of the DRX 8872C consists of a 1

IF COFDM signal with a bandwidth of 6, 7, or

8 MHz. The input of the demodulator is differential for
optimal noise performance. The reference voltages
that are needed for the ADC are generated internally.
The reference voltages are connected to pins for
decoupling reasons.

Fig. 21: Input stage application diagram.

2.2. AGC

The DRX 8872C delivers a control signal for an ampli-
fier in the tuner part of the system. The system control-
ler controls a register that is used for a pulse train
using a Pulse Width Modulator (PWM) circuit. 256 val-
ues can be distinguished. The SP7_SetAGCParams
function of the API determines the way this register is
controlled. By default, the maximum level is repre-
sented by all `1's and the minimum level is represented
by all `0's. A low-pass RC filter connected to the AGC
pin will filter the PWM signal, generating a stable ana-
log signal for controlling the amplifier of the tuner. The
bandwidth of this filter should be small enough to mini-
mize the PWM-jitter on the control signal. The external
AGC control is slow compared to the fast internal
AGC. A filter bandwidth of 1 kHz is recommended for
filtering the PWM-jitter.

Fig. 22: AGC application diagram.

For tuners that need voltages other than 0 to 3.3 Volt a
buffer connected to 5 Volt could be inserted for gener-
ating a higher control voltage.

2.3. Crystal

A single crystal operates the DRX 8872C. Sample rate
mismatches are corrected completely in the digital
domain. The clock generated by the crystal is used as
the system clock. A `divide by three'-block generates
the sample clock for the ADC. There are two possible
frequencies that can be used by the DRX 8872C.
When using the 1

IF sampling technique, a 61 MHz

crystal should be used. For 2

IF sampling one should

select a 55 MHz crystal. The next figure shows why.

VDDL 2.5 Volt digital

VDDH 3.3 Volt digital

VDDA 2.5 Volt analog

digital ground

analog ground for ADC

100 nF decoupling capacitor

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DRX 8872C

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Fig. 23: 1

or 2

IF sampling

The API function SP7_SetSamplingMode has been
defined to set the mode. Default 1

IF sampling is

assumed. To generate 55 or 61 MHz, a third overtone
crystal must be used. The fundamental tone must be
filtered out using an LC network with a time constant
defined by:

, where

with f=61 MHz for 1

IF sampling and f=55 MHz for

baseband sampling. The application diagram shows
the complete crystal circuitry, for example:

Fig. 24: Clocking circuitry for 1

IF or baseband

sampling

A frequency mismatch of ±100 ppm is allowed for the
described crystals.

Frequency (MHz)

36.125

18.3

(ADC sample
frequency)

Second down-conversion by
external mixer + lowpass filter

Frequency (MHz)

36.125

20.3

(ADC sample
frequency)

Second down-conversion by
subsampling first IF by internal
ADC at 20.6 Mhz

IF Sampling

-----------

--------

15pF

4.7 H

55 MHz

IF Sampling

15pF

12 pF

4.7 H

15 pF

61 MHz

DRX 8872C

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2.4. Manufacturing Guidelines

To maximize both the removal of heat from the pack-
age and the electrical performance, a land pattern
must be incorporated on the PCB within the footprint of
the package corresponding to the exposed metal pad
on the package, as shown in Fig. 25.

Fig. 25: Top layer solder mask

The dimensions of the PCB pad may be larger or
smaller or even a different shape than the exposed
metal pad but should have a clearance of at least
0.25 mm between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to
avoid any shorts.

To improve the thermal dissipation, a thermal via array
should be made within the PCB pad area. The vias
should be 0.3 mm in diameter at a pitch of between 1.0
and 1.2 mm and preferably with 1 oz copper via barrel
plating.

Fig. 26: Thermal via array

For further information regarding the optimal usage of
the Micronas exposed-pad QFP please refer to the
Application Note "Surface Mount Assembly of
Exposed-Pad QFP packages".

2.5. Lock Indication

Two hardware lock indicators are available. They can
be used for LED control as shown in Fig. 27.

Fig. 27: Lock indication LEDs

The lock indicator pins FEC_LCK and OFDM_LCK can
also be put in two other modes:

SAW filter select

In this mode the two lock signal indicate whether the
input signal has a 6, 7, or 8 MHz bandwidth. These
pins can than be used directly to switch SAW filters in
the tuner accordingly.

User defined

In this mode the value of the pins can be programmed
via software by the host of the system.

The API function SP7_LCKMode takes care of these
settings.

150

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2.5.1. Host Interface

The DRX 8872C communicates via a serial protocol.
The DRX 8872C only acts as a slave device. A write
access consists of a `start' followed by the DRX 8872C
device address, then the internal register address
(2 bytes) and finally the data that needs to be written.
During a read-access a repeated start should follow
the internal register address definition, after which the
data can be read.

Fig. 28: I2C_Write timing (NrOfBytes = 2)

Fig. 29: I2C_Read timing (NrOfBytes = 2)

The device address is either "1110000x" if the ASEL
pin is tied low or "1110001x" if the ASEL pin is tied
high.

DRX 8872C

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2.6. MPEG2 Output

The DRX 8872C has a parallel or serial transport
stream output. The system controller adjusts the
MPEG2 clock (MCLK) in order to minimize the jitter on
the gaps in between packets. The maximum jitter is
limited to 20

s. There are several combinations of

clock and data formats possible allowing flexible inter-
facing to MPEG2 decoders. The following figure shows
the behavior of the MPEG2 output pins in parallel and
serial mode.

The DRX 8872C can output the parity bytes in
between two transport stream packages or one can
choose to have the transport stream packets output
without parity bytes. The API function SP7_TSOutput
lets the user control this. Furthermore, this function
can be used to put the MPEG output pins in tristate
mode. This can be useful in multistandard STBs where
both satellite and terrestrial front-ends are connected
to one common interface. No external multiplexer is
needed.

Fig. 210: MPEG2 TS output timing

SYNC BYTE

BYTE 1

PAR MCLK

PAR MSTR

PAR MVAL

PAR MDAT

SER MCLK

SER MSTR

SER MVAL

SER MDAT

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3. Application Programming Interface (API)

For a description of the types used in the API proto-
types, refer to Appendix A in Section 5. on page 37.
Most functions in the API return a status (of type
Status_t) that indicates whether the function com-
pleted successfully.

The API assumes availability of low-level serial inter-
face functions, as described in Appendix B.

3.1. Initialize System Settings

The DRX 8872C integrates a processor. This proces-
sor performs the algorithms to synchronize and track
the COFDM signal. The algorithms are described in
microcode.

There are two versions of the microcode available: A
basic version including only the code that will actually
be uploaded to the chip and another version including
a so-called symbol-table. The basic version is 16 kB
and the extended code is about 20 kB. The symbol
table includes a memory map of internal processor
variables. When monitoring these variables, the sym-
bol table tells the application which address to use.
Most applications don't need to monitor the internal
processor variables and then one only needs the basic
code. In the API distribution, the source code for a tool
called "SP7Strip" is included. This tool can strip the
symbol table from the microcode as distributed.

After start of the software application, uploading the
microcode to the internal processors memory must be
the first action. When uploading the originally distrib-
uted microcode, one should use the following function.

3.1.1. SP7_LoadMicrocode

Status_t

SP7_LoadMicrocode

(

pu16_t

mc_addr,

pu32_t

version

);

For uploading the `stripped' version, the following function is available.

3.1.2. SP7_LoadImage

Status_t

SP7_LoadImage

(

u16_t

image_size,

pu8_t

image_addr,

pu32_t

version

);

Variable

Type

Description

mc_addr

pu16_t

Memory address of the binary file containing the algorithms for the internal processor.

version

pu32_t

Returns version of microcode uploaded.

Variable

Type

Description

image_size

u16_t

Number of bytes to load (typically 16384).

image_addr

pu8_t

Memory address of the 16 kB stripped binary file containing the algorithms for the internal
processor.

version

pu32_t

Returns version of microcode uploaded.

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The processor inside the DRX 8872C needs to be
given some basic information about the application in
order to be able to automatically acquire lock. The first
parameter is the sampling mode. The DRX 8872C
supports 1

IF sampling as well as base-band sam-

pling. All one needs to do is tell the processor which
system clock frequency (crystal) and which input sig-
nal frequency generally 36.125 MHz for 1

IF or

4.57 MHz for baseband sampling is used. In combi-
nation with knowledge about whether the signal is mir-
rored or not, the chip will automatically calculate the
correct settings for the internal sample-rate correction
filters. The digital timing recovery enables the system
to acquire lock when the system clock is within
500 ppm of the preprogrammed value.

3.1.3. SP7_SetSamplingMode

Status_t

SP7_SetSamplingMode (

u16_t SystemClockFrequency,
u16_t

SigInputFrequency,

Mirror_t

SigInputMirror

);

Variable

Type

Description

SystemClockFrequency

u16_t

Frequency of the crystal applied to the DRX 8872C, in kHz (e.g. set to 61000
when using a 61-MHz crystal).

SigInputFrequency

u16_t

16 bit integer number representing the center frequency of the COFDM signal
that is applied to the DRX 8872C, in kHz (e.g. set to 36125 for 1

IF sampling).

SigInputMirror

Mirror_t

In case the input signal to the DRX 8872C is mirrored, depending on the number
of down-conversion stages in the system, this can be indicated using this flag.
The DRX 8872C will adjust automatic frequency correction algorithms
accordingly.

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Depending on the tuner one uses, it is either preferred
to have a slow AGC control or a fast feedback to
changes on the incoming energy level. The type of
control can be selected using the AGC control variable
in the next API function.

When not controlled by the internal processor, it is
possible to adjust the level of the amplifier stages by
changing the AGC-level variables as described in the
next function.

3.1.4. SP7_SetAGCParams

Status_t

SP7_SetAGCParams

(

AGC_t AGC_ctrl,
Bool_t AGC_SelectPin2,
u16_t

AGC_level1,

u16_t

AGC_level2,

u16_t

AGC_level3

);

Variable

Type

Description

AGC_ctrl

AGC_t

Variable indicating type of control.

AGC_OFF
No control, the default levels will be applied.

AGC_FAST
Fast reaction to changes in energy level. In this mode the chip uses a hardwired AGC
control function.

AGC_SLOW
Instead of the hardwired AGC functionality the internal processor controls the incoming
energy level on symbol basis.

AGC_INV
By default, a positive control is used. With this setting this can be changed into a negative
control. This is only possible in combination with AGC_SLOW. If one wants to negate the
control in combination with AGC_FAST, one must use an external inverting component.

AGC_SelectPin2

Bool_t

If TRUE, AGC is applied to the secondary PWM output (only DRX8872P).

AGC_level1

u16_t

Unsigned integer indicating the default level of AGC1 when no control is applied to it.

AGC_level2

u16_t

Unsigned integer indicating the default level of AGC2 when no control is applied to it.

AGC_level3

u16_t

Unsigned integer indicating the default level of AGC3 when no control is applied to it.

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Upon power-on reset, all output pins are tri-stated to
allow other demodulators (e.g. satellite or cable) to
drive the TS signals. The output pins must be put in

output mode using the following API function. The
monitor-bus with real-time channel information is only
available with the professional version.

3.1.5. SP7_SetOutputEnable

Status_t

SP7_SetOutputEnable (

Bool_t

MpegTS,

Bool_t

MonitorBus,

Bool_t

InterfacePins

);

The actual mode of the pins can be obtained using the following function.

3.1.6. SP7_GetOutputEnable

Status_t

SP7_GetOutputEnable (

pBool_t

MpegTS,

pBool_t

MonitorBus,

pBool_t

InterfacePins

);

Variable

Type

Description

MpegTS

Bool_t

Boolean indicating MPEG TS pin driver state.

FALSE
MPEG TS pins are tristated (default).

TRUE
MPEG TS pins are put in output mode.

MonitorBus

Bool_t

Boolean indicating Monitor bus pin driver state (MT8872P only).

FALSE
Monitor bus pins are tristated (default).

TRUE
Monitor bus pins are put in output mode.

InterfacePins

Bool_t

Boolean indicating pin driver state of OFDM_LCK, FEC_LCK, I2C2_EN, IRQN and
SCL2 (DRX 8872C only).

FALSE
Pins are tristated.

TRUE
Pins are put in output mode.

Variable

Type

Description

MpegTS

pBool_t

Boolean indicating MPEG TS pin driver state.

FALSE
MPEG TS pins are tristated (default).

TRUE
MPEG TS pins are in output mode.

MonitorBus

pBool_t

Boolean indicating Monitor bus pin driver state (MT8872P only).

FALSE
Monitor bus pins are tristated (default).

TRUE
Monitor bus pins are in output mode.

InterfacePins

pBool_t

Boolean indicating pin driver state of OFDM_LCK, FEC_LCK, I2C2_EN, IRQN and SCL2
(DRX 8872C only).

FALSE
Pins are tristated.

TRUE
Pins are in output mode.

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The MPEG Transport Stream interface clocking can be
configured. When no valid data bytes are output (the
parity bytes in between two packets or during the
remaining gap in the guard interval) the MCLK pin can

either be disabled or a continuous clock can be cho-
sen. When using the continuous clock the MVAL signal
can be used to indicate non-valid data.

3.1.7. SP7_TSOutput

Status_t

SP7_TSOutput

(

Bool_t

Parity,

Bool_t

SuppressClock

);

The last pins that can be configured are the OFDM_LCK and the FEC_LCK pins.

3.1.8. SP7_LCKMode

Status_t

SP7_LCKMode

(

LCK_t

OFDM_LCK_Ctrl,

LCK_t

FEC_LCK_Ctrl

);

For function SP7_LCKMode to work correctly, the OFDM_LCK and FEC_LCK pins must have been configured for
output, by using the function SP7_SetOutputEnable.

Variable

Type

Description

Parity

Bool_t

If TRUE, The Reed Solomon parity bytes will be output in between two transport stream
packets.

SuppressClock

Bool_t

If TRUE, the MCLK pin is suppressed when no valid data is output (parity bytes and gaps
between packets or during guard interval).

Variable

Type

Description

OFDM_LCK_Ctrl

LCK_t

Parameter indicating use of the OFDM LCK pin.

LCK_INDICATOR
The OFDM_LCK pin reflects the locking state of the COFDM demodulator part of
the chip.

LCK_SAW_8
The OFDM_LCK pin will go high if an 8 MHz SAW filter must be selected, otherwise
(for 7 or 6 MHz bandwidths) it will be low.

LCK_SAW_7
The OFDM_LCK pin will go high if an 7 or 8 MHz SAW filter must be selected,
otherwise (for 6 MHz bandwidths) it will be low.

LCK_UIO_0
The OFDM_LCK pin will be always low.

LCK_UIO_1
The OFDM_LCK pin will be always high.

FEC_LCK_Ctrl

LCK_t

Parameter indicating use of the FEC LCK pin.

LCK_INDICATOR
The FEC_LCK pin reflects the locking state of the FEC error correction part of the
chip.

LCK_SAW_8
The FEC_LCK pin will be high if an 8 MHz SAW filter must be selected, otherwise
(for 7 or 6 MHz bandwidths) it will be low.

LCK_SAW_7
The FEC_LCK pin will go high if an 7 or 8 MHz SAW filter must be selected,
otherwise (for 6 MHz bandwidths) it will be low.

LCK_UIO_0
The FEC_LCK pin will be always low.

LCK_UIO_1
The FEC_LCK pin will be always high.

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3.2. Setup Signal Parameters

All hardware related parameters have been set now.
The next step is to configure the system for the incom-
ing signal. In the application one can either let the
DRX 8872C detect all settings automatically or one
can choose to pre-program some parameters in case
they are known. This can improve locking speed. The

functions

SP7_GetChannelParams and

SP7_SetChannelParams relate to channel parameters
like frequency offsets and signal bandwidth. The
SP7_GetOfdmParams and SP7_SetOfdmParams
functions relate to the COFDM symbol parameters like
code rate, FFT size etc. The parameters that are set
up with these functions are not programmed until the
chip is started using the SP7_Start function.

3.2.1. SP7_SetChannelParams

Status_t

SP7_SetChannelParams (

s16_t

SysFrequencyOffset,

s16_t

SigFrequencyOffset,

Bandwidth_t SigBandwidth,
Mirror_t

SigMirror,

Cls_t

SigClass

);

Next to programming the values, the measured values can be obtained from the system.

Variable

Type

Description

SysFrequencyOffset

s16_t

Signed integer number indicating the known system clock frequency
mismatch in kHz, relative to the value that was set with
SP7_SetSamplingMode.

SigFrequencyOffset

s16_t

Signed integer number indicating the known signal frequency mismatch in
kHz. If unknown, set to zero.

SigBandwidth

Bandwidth_t

The bandwidth can be programmed.

BANDWIDTH_6MHZ
6 MHz Channel.

BANDWIDTH_7MHZ
7 MHz Channel.

BANDWIDTH_8MHZ
8 MHz Channel (default).

SigMirror

Mirror_t

This parameter indicates whether the spectrum is mirrored.

MIRRORED
Spectrum is mirrored.

NORMAL
Spectrum is normal.

AUTO
Detect automatically.

SigClass

Cls_t

This parameter sets the channel classification.

CLS_GAUSS
Gaussian noise.

CLS_HEAVYGAUSS
Heavy Gaussian noise.

CLS_COCHANNEL
Co-channel.

CLS_STATIC
Static echo.

CLS_MOVING
Moving echo.

CLS_ZERODB
Zero dB echo.

AUTO
Detect automatically.

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3.2.2. SP7_GetChannelParams

Status_t

SP7_GetChannelParams (

ps16_t

SysFrequencyOffset,

ps16_t

SigFrequencyOffset,

pBandwidth_tSigBandwidth,
pMirror_t

SigMirror,

pCls_t

SigClass

);

Variable

Type

Description

SysFrequencyOffset

ps16_t

Signed integer number indicating the system clock frequency mismatch in
kHz, relative to the value that was set with SP7_SetSamplingMode.

FrequencyOffset

ps16_t

Signed integer number indicating the signal frequency mismatch in kHz.
Depending on the step-size of the tuner, the mismatch can be minimized by
re-tuning.

SigBandwidth

pBandwidth_t

The bandwidth is reported. This returns either a default value or the value
that was set by a previous call of SP7_SetChannelParams.

BANDWIDTH_6MHZ
6 MHz Channel.

BANDWIDTH_7MHZ
7 MHz Channel.

BANDWIDTH_8MHZ
8 MHz Channel.

SigMirror

pMirror_t

This parameter indicates whether the spectrum is mirrored.

MIRRORED
Spectrum is mirrored.

NORMAL
Spectrum is normal.

SigClass

pCls_t

The channel classification is reported.

CLS_GAUSS
Gaussian noise.

CLS_HEAVYGAUSS
Heavy Gaussian noise.

CLS_COCHANNEL
Co-channel.

CLS_STATIC
Static echo.

CLS_MOVING
Moving echo.

CLS_ZERODB
Zero dB echo.

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The mode of the COFDM signal path is being transmit-
ted using the TPS carriers can be detected automati-
cally. The information can be obtained by using the
SP7_GetOfdmParams function and the system can be
told to use a specific mode using the
SP7_SetOfdmParams API function.

3.2.3. SP7_SetOfdmParams

Status_t

SP7_SetOfdmParams

(

Mode_t

Mode,

Guard_t

Guard,

Const_t

Constellation,

Hier_t

Hierarchy,

Prior_t

Priority,

Rate_t

CodeRate

);

Variable

Type

Description

Mode

Mode_t

MODE_2K
8k Mode.

MODE_8K
2k Mode.

AUTO
Detect automatically.

Guard

Guard_t

GUARD_32
1/32nd Guard interval.

GUARD_16
1/16th Guard interval.

GUARD_8
1/8th Guard interval.

GUARD_4
1/4th Guard interval.

AUTO
Detect automatically.

Constellation

Const_t

CONST_QPSK
QPSK constellation.

CONST_QAM16
QAM16 constellation.

CONST_QAM64
QAM64 constellation.

AUTO
Detect automatically.

Hierarchy

Hier_t

HIER_NONHIER
No hierarchical transmission.

HIER_ALPHA_1
Hierarchical transmission,

is one.

HIER_ALPHA_2
Hierarchical transmission,

is two.

HIER_ALPHA_4
Hierarchical transmission,

is four.

AUTO
Detect automatically.

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3.2.4. SP7_GetOfdmParams

Status_t

SP7_GetOfdmParams

(

pMode_t

Mode,

pGuard_t

Guard,

pConst_t

Constellation,

pHier_t

Hierarchy,

pPrior_t

Priority,

pRate_t

CodeRate

);

The processor now knows all it needs to know and one
can start to acquire lock.

Variable

Type

Description

Mode

pMode_t

MODE_2K
8k Mode.

MODE_8K
2k Mode.

Guard

pGuard_t

GUARD_32
1/32nd Guard interval.

GUARD_16
1/16th Guard interval.

GUARD_8
1/8th Guard interval.

GUARD_4
1/4th Guard interval.

Constellation

pConst_t

CONST_QPSK
QPSK constellation.

CONST_QAM16
QAM16 constellation.

CONST_QAM64
QAM64 constellation.

Hierarchy

pHier_t

HIER_NONHIER
No hierarchical transmission.

HIER_ALPHA_1
Hierarchical transmission,

is one.

HIER_ALPHA_2
Hierarchical transmission,

is two.

HIER_ALPHA_4
Hierarchical transmission,

is four.

Priority

pPrior_t

In case of hierarchical transmission:

PRIOR_LOW
Low priority.

PRIOR_HIGH
High priority.

CodeRate

pRate_t

RATE_1_2
Code rate 1/2nd.

RATE_2_3
Code rate 2/3rd.

RATE_3_4
Code rate 3/4th.

RATE_5_6
Code rate 5/6th.

RATE_7_8
Code rate 7/8th.

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The SP7_Start function will start the internal processor
and the demodulation process will start, making use of
the settings that were applied using the previously
described API functions.

3.2.5. SP7_Start

Status_t

SP7_Start

(

void );

If an COFDM signal is applied to the input of the
DRX 8872C, the system will start to acquire lock.

3.3. Selecting Channels

In order to get a correct COFDM signal, the tuner in
front of the demodulator must be programmed to the
right frequency. The DRX 8872C has been tested in
combination with many tuners. Each tuner has its own
specifications. The frequency range, step-size and
charge pump settings vary per tuner. Also the optimal
AGC setting can be different per tuner type. To ease
the work of the customers some API functions have
been made available. When using one of the tested
tuner types the optimal settings will automatically be
chosen.

To initialize the API with the settings of the tuner that is
currently in use, first the SP7_Tune_init function
should be called.

3.3.1. SP7_Tune_init

Status_t

SP7_Tune_init

(

u16_t

tune_type );

Variable

Type

Description

tune_type

u16_t

Variable indicating which tuner is used. Refer to source code for list of tuners
supported.

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The function SP7_Tune_properties can be called to
retrieve the parameters of the tuner that is used (if
known by the API). The output of this function can be
used when setting up the system. In this case the user

does not have to worry about whether the tuner out-
puts its signal at 1

or 2

IF, whether the signal is mir-

rored or not and what the preferred AGC settings
should be.

3.3.2. SP7_Tune_properties

Status_t

SP7_Tune_properties (

pu8_t*

Name,

pu32_t

FrequencyMin,

pu32_t

FrequencyMax,

pu16_t

FrequencyStep,

pu16_t

FrequencyOut,

pMirror_t

FrequencyMirror,

pAGC_t

AgcType,

pu16_t

Agc_level3

);

Next to acquiring information related to the type of
tuner used, the API supports functions that will actually
program the tuner to the desired frequency with the
appropriate settings.

3.3.3. SP7_Tune_program

Status_t

SP7_Tune_program

(

u32_t

F );

In case communication with the tuner fails, the exact
error status can be read back using the following func-
tion.

3.3.4. SP7_Tune_error

u16_t

SP7_Tune_error

(

void );

Returns number that represents an error code.

Variable

Type

Description

Name

pu8_t*

Returns the name of the tuner. Only relevant when more than one tuner is taken into
account during compilation, for instance in applications like Signal Spyder.

FrequencyMin

pu32_t

Minimum available frequency for this tuner, in kHz.

FrequencyMax

pu32_t

Maximum supported frequency for this tuner, in kHz.

FrequencyStep

pu16_t

RF frequency step-size for this tuner.

FrequencyOut

pu16_t

Output frequency of this tuner.

FrequencyMirror

pMirror_t

Variable indicating whether the output of this tuner is mirrored or not.

AgcType

pAGC_t

Variable indicating the preferred AGC setting for the tuner currently used.

AGC_level3

pu16_t

Integer value indicating the optimum PGA level in combination with the tuner
currently used.

Variable

Type

Description

u32_t

Frequency to which the tuner should be programmed, in kHz.

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Since the tuner has a finite step-size it will not be pos-
sible to exactly program the tuner to the desired fre-
quency. The next function reports the frequency to
which the tuner was actually programmed.

3.3.5. SP7_Tune_get_freq

u32_t

SP7_Tune_get_freq

(

void );

Returns exact frequency to which the tuner was pro-
grammed, in kHz.

When not using the given tuner programming func-
tions, one needs to calculate the tuner settings and
generate the command string (5 bytes) using the tuner
specification. The DRX 8872C supports a gated clock-
line to the tuner. This means that the tuner is not con-
nected directly to the serial bus but via the demodula-
tor and an external analog switch. If connected in this
way, the serial lines towards the tuner can be kept
quiet during normal operation to minimize noise on the
PLL inside the tuner. To select a channel first the con-
nection to the tuner must be enabled, then the tuner
specific settings must be applied (5 I

C byte

accesses), and finally the connection to the tuner can
be closed again. The following API function has been
defined for opening and closing this port.

3.3.6. SP7_EnableTunerAccess

Status_t

SP7_EnableTunerAccess(

Bool_t

TunerAccess );

After programming the tuner, the chip will start to
acquire lock. It is of course important to know whether

the chip has acquired lock. For this purpose the
SP7_LockingStatus function has been defined.

3.3.7. SP7_LockingStatus

Status_t

SP7_LockingStatus

(

pBool_t

Locked );

Variable

Type

Description

TunerAccess

Bool_t

If TRUE, the secondary protocol port is opened for programming the tuner.

Variable

Type

Description

Locked

pBool_t

If TRUE, chip has acquired lock.

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3.4. Monitor Channel Quality

The channel estimator unit of the DRX 8872C per-
forms a signal to noise measurement on the constella-
tion diagram. The output of this calculation can be

retrieved using the API function SP7_GetSN. From this
measurement, a MER is also derived. The MER is cal-
culated using the deviation of the continual pilots and
is therefore an indication, not an exact value.

3.4.1. SP7_GetSN

Status_t

SP7_GetSN

(

pu16_t

SN,

pu16_t

MER

);

The S/N ratio gives a very good indication of the chan-
nel quality, independent of the mode of the signal. For
a graphical feedback one can use the constellation

diagram. A slow non-real-time diagram can be built
using the following function.

3.4.2. SP7_GetConstellationDiagram

Status_t

SP7_GetConstellationDiagram (

ps16_t

Real,

ps16_t

Imag

);

A more common way to give an indication of the signal
quality is to look at the BER values. This also allows

for comparison of the quality of the DRX 8872C to the
ETS300744 DVB-T standard.

3.4.3. SP7_GetBer

Status_t

GetBer

(

pu32_t

PreViterbi,

pu32_t

PostViterbi,

pu32_t

PacketError

);

Variable

Type

Description

pu16_t

Integer number indicating the S/N ratio detected at the input of the demapper, in steps of
1/10th of a dB.

MER

pu16_t

Integer number indicating the MER, in steps of 1/10th of a dB.

Variable

Type

Description

Real

ps16_t

Real part of the constellation point. The values 256/-256 correspond to the energy level
of the pilots of the COFDM symbol. The maximum values range from 512 to +511.

Imag

ps16_t

Imaginary part of the constellation point.

Variable

Type

Description

PreViterbi

pu32_t

Bit error rate (BER) before error correction, with a scale of 1e-6.

PostViterbi

pu32_t

BER after Viterbi decoder, with a scale of 1e-6. A value of 200 corresponds to a BER of
2e-4, the so-called QEF level.

PacketError

pu16_t

Counter indicating the number of packet errors after Reed Solomon decoding.

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Next to using the previously described function
SP7_GetOfdmParams to obtain information on the
incoming COFDM signal, the TPS information con-
tained in the COFDM signal can be read using the fol-
lowing API function.

3.4.4. SP7_GetTpsInfo

Status_t

SP7_GetTpsInfo

(

pMode_t

TpsMode,

pGuard_t

TpsGuard,

pConst_t

TpsConstellation,

pHier_t

TpsHierarchy,

pRate_t

TpsHiRate,

pRate_t

TpsLoRate,

pTpsFrame_t TpsFrame,
pu8_t

TpsLength,

pBool_t

TpsCellIdRdy,

pu16_t

TpsCellId

);

Variable

Type

Description

TPSMode

pMode_t

Variable indicating the mode as described in the TPS parameters.

TpsGuard

pGuard_t

Guard interval length as described in the TPS parameters.

TpsConstella-
tion

pConst_t

Constellation diagram depth as described in the TPS parameters.

TpsHierarchy

pHier_t

Level of Hierarchy as described in the TPS parameters.

TpsHiRate

pRate_t

High priority code rate.

TpsLoRate

pRate_t

Low priority code rate.

TpsFrame

pTpsFrame_
t

Frame number.

TpsLength

pu8_t

Integer number indicating the length of the TPS Frame.

TpsCellIdRdy

pBool_t

Flag indicating that the returned TpsCellId is valid.

TpsCellId

pu16_t

16-Bit received Cell identifier.

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3.5. Commands and other Useful Functions

Next to the application specific function as described in
the previous paragraphs, also some low level functions
are available. Other API functions also make use of
these low-level functions themselves.

3.5.1. SP7_Reboot

Status_t

SP7_Reboot

(

void );

Reinstall all register settings, which were stored during
the first start-up, and reload all default algorithm con-
stants. Starts demodulator.

3.5.2. SP7_Reset

Status_t

SP7_Reset

( void );

Reinstalls all register settings, does not reinitialize
algorithm constants, such that user patches remain
active. Restarts algorithm.

3.5.3. SP7_SysReset

Status_t

SP7_SysReset

( void );

First resets all internal hardware, then behaves like
SP7_Reset.

3.5.4. SP7_Restart

Status_t

SP7_Restart

( void );

Just restart algorithm, with current register settings
and algorithm constants.

3.5.5. SP7_Halt

Status_t

SP7_Halt

( void );

Halts the current state of the DRX 8872C. This is a
useful function when debugging your application. The
DRX 8872C remains executing commands.

3.5.6. SP7_Nop

Status_t

SP7_Nop

( void );

Do nothing, but generate an interrupt on completion.

The next two functions enable different algorithm con-
stants to be programmed to influence the behavior of
the algorithm. Also the state of all microcode variables
can be queried. Reading and writing microcode vari-
ables is done "atomically".

3.5.7. SP7_Wreg

Status_t

SP7_Wreg

(

u16_t

Reg,

u16_t

Data

);

3.5.8. SP7_Rreg

Status_t

SP7_Rreg

(

u16_t

Reg,

pu16_t

Data

);

Variable

Type

Description

Reg

u16_t

Address of register that needs to be written.

Data

u16_t

New value for the register.

Variable

Type

Description

Reg

u16_t

Address of register that needs to be read.

Data

pu16_t

Returns value of the register.

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3.5.9. SP7_Wvar

Status_t

SP7_Wvar

(

u16_t

Adr,

u16_t

Wnr,

pu16_t

Wdata

);

3.5.10.SP7_Rvar

Status_t

SP7_Rvar

(

u16_t

Adr,

u16_t

Rnr,

pu16_t

Rdata

);

3.6. Interrupts and Events

The DRX 8872C has an IRQN output which can gen-
erate an interrupt to the host to trigger an event. Two
types of interrupts are reported back to the host: "Com-
mand Completion" interrupt, and "Algorithm Event"
interrupt. The API uses the "Command Completion"
interrupt internally. The "Algorithm Event" interrupt is of
special interest to the application.

3.6.1. SP7_ReadIrq

Status_t

SP7_ReadIrq

( void );

Reads the interrupt status register, such that new
interrupts may occur.

Variable

Type

Description

Adr

u16_t

Address of (processor) variable that needs to be written.

Wnr

u16_t

Number of words that must be written.

Wdata

pu16_t

New value for the variable (array).

Variable

Type

Description

Adr

u16_t

Address of (processor) variable that needs to be read.

Rnr

u16_t

Number of words that must be read.

Rdata

pu16_t

Returns value of the variable (array).

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On any occasion, the event register may be read to
see if the DRX 8872C algorithm generated an event. If
an event occurs, an interrupt is also generated. Thus if
the interrupt line is used, it makes sense to only read
the event register on an interrupt.

3.6.2. SP7_PollEvent

Status_t

SP7_PollEvent

(

pu16_t

OccurredEvents );

Reads the event register and sets bits in OccurredE-
vents according to the events that occurred since the
last read.

Variable

Type

Description

OccurredEvents

pu16_t

The following event bits may be set:

SP7_EV_ERR
Algorithm restarted (lock lost).

SP7_EV_SIG
Algorithm detected a DVB-T signal, lock will follow soon.

SP7_EV_LCK
Algorithm acquired a lock on the DVB-T signal and is demodulating now.

SP7_EV_VBER
A new Pre-Viterbi BER measurement is ready to be read.

SP7_EV_RBER
A new Post-Viterbi BER measurement (or packet error count) is ready to be read.

SP7_EV_SN
A new SN and MER measurement is ready to be read.

SP7_EV_TPS
A new TPS frame is ready to be read.

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4.2. Pin Connections and Short Descriptions

Pin
No.

Pin Name

Type

Connection

Short Description

(If not used)

VDDL

Digital core supply 2.5 volt

VSS

GND

Digital ground

VSS

GND

Digital ground

ASEL

Serial interface address select

VSS

GND

Digital ground

AGC

Automatic gain output

VSSA

GND

Analog ground

VREF

Bias circuitry reference voltage decoupling pin

INM

Symmetrical IF or Base band input

INP

Symmetrical IF or Base band input

VSSA

GND

Analog ground

VDDA

Analog supply 2.5V

VRM

External middle rail reference

VDDA

Analog supply 2.5V

VSSA

GND

Analog ground

VRH

High reference Voltage

VRL

Low reference Voltage

VSSA

GND

Analog ground

VSSA

GND

Analog ground

VDDH

Digital IO supply 3.3V

SCL

Clock line for serial protocol

SDA

I/O

Data line for serial protocol

VSS

GND

Digital ground

TCLK

10 k

pull-up

to VDDH

JTAG test clock

TDI

10 k

pull-up

to VDDH

JTAG test data in

TMS

10 k

pull-up

to VDDH

JTAG test mode select

TDO

JTAG test data out

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VDDL

Core supply 2.5V

VSS

GND

Digital ground

VDDH

Digital IO supply 3.3V

VSS

GND

Digital ground

VSS

GND

Digital ground

VSS

GND

Digital ground

VSS

GND

Digital ground

IRQN

Interrupt to host (active low)

VDDL

Digital core supply 2.5V

VSS

GND

Digital ground

SCL2

Secondary serial interface clock

MERR

MPEG packet error flag

MSTRT

Frame start flag

VDDL

Digital core supply 2.5V

VDDH

Digital IO supply 3.3V

MVAL

MPEG2 data valid signal

MCLK

MPEG2 clock

MD_7

MPEG2 data output

VSS

GND

Digital ground

MD_6

MPEG2 data output

MD_5

MPEG2 data output

MD_4

MPEG2 data output

VDDH

Digital IO supply 3.3V

VSS

GND

Digital ground

MD_3

MPEG2 data output

MD_2

MPEG2 data output

MD_1

MPEG2 data output

MD_0

MPEG2 data output/ MPEG serial data output

OFDM_LCK

Lock signal indicating valid OFDM signal

VSS

GND

Digital ground

VDDH

Digital IO supply 3.3V

Pin
No.

Pin Name

Type

Connection

Short Description

(If not used)

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FEC_LCK

Lock signal indicating FEC lock

Should be left open

VDDL

Digital core supply 2.5V

I2C_EN

Secondary serial interface enable line

VSS

GND

Digital ground

VSS

GND

Digital ground

VSS

GND

Digital ground

VSS

GND

Digital ground

VSS

GND

Digital ground

VSS

GND

Digital ground

VDDH

Digital IO supply 3.3V

VSS

GND

Digital ground

Crystal oscillator output

VSS

GND

Digital ground

Crystal oscillator input

VSS

GND

Digital ground

XPD

Power down mode low = oscillator active

VDDL

Digital core supply 2.5V

VSS

GND

Digital ground

IREFSEL

Internal voltage reference select high = enable

RST

Reset signal (active low)

VSS

GND

Digital ground

Pin
No.

Pin Name

Type

Connection

Short Description

(If not used)

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4.3. Pin Configurations

Fig. 41: 80-pin PTQFP package

10 11 12 13 14 15

DRX 8872C

16 17 18 19 20

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

VSS

VDDL

I2C_EN

VSS

VDDH

VSS

XPD

VSS

RST

VSS

VDDL

IREFSEL

VSS

MSTRT

MERR

SCL2

VDDL

IRQN

VSS

VDDH

TMS

VSS

TDO

VDDL

SDA

SCL

TDI

VSS

TCLK

MD_1

MD_0

OFDM_LCK

VDDH

FEC_LCK

VSS

MD_3

MD_2

VDDL

MD_6

VSS

MD_7

MVAL

VDDH

MCLK

VDDH

MD_4

MD_5

VDDL

VSSA

AGC

VSS

ASEL

INP

INM

VREF

VDDH

VDDA

VSSA

VRH

VSSA

VRL

VSSA

VDDA

VRM

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4.4. Electrical Characteristics

Abbreviations

tbd = to be defined
vacant = not applicable
positive current values mean current flowing into the chip

4.4.1. Absolute Maximum Ratings

Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute
maximum rating conditions for extended periods will affect device reliability.

This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso-
lute maximum-rated voltages to this high-impedance circuit.

All voltages listed are referenced to ground except where noted.

All GND pins must be connected to a low-resistive ground plane close to the IC.

Table 41: Absolute Maximum Ratings

Symbol

Parameter

Pin Name

Limit Values

Unit

Min.

Max.

Ambient Operating Temperature

Storage Temperature

125

MAX

Maximum Power Dissipation 1.1 W

DDA

Analog supply

VDDA

0.3

3.0

DDL

Digital core supply

VDDL

0.3

3.0

DDH

Digital IO supply

VDDH

0.3

3.6

SUP

Voltage differences within supply
domains (V

DDA

- V

DDL

)

0.2

I analgoue

Analog Input Voltage

INM; INP; AGC;
VRH; VRL

0.3

DDA

+ 0.3

I digital

Digital Input Voltage

ASEL; SDA;
SCL; TDI; TMS;
IRQN; XI, XPD,
IREFSEL, RST

0.3

DDH

+ 0.3

A thermally-optimized board layout is recommended; refer to the application note "Surface Mount Assembly of
Exposed-Pad QFP packages".

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4.4.2. Recommended Operating Conditions

Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteris-
tics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device.

All voltages listed are referenced to ground except where noted.

All GND pins must be connected to a low-resistive ground plane close to the IC.

Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.

4.4.2.1. General Recommended Operating Conditions

Symbol

Parameter

Pin Name

Limit Values

Unit

Min.

Typ.

Max.

Ambient Operating Temperature

MAX

Maximum Power Dissipation

1.1

DDA1

Analog Supply

VDDA

2.3

2.5

2.7

DDL

Digital Core Supply

VDDL

2.3

2.5

2.7

DDH

Digital IO Supply

VDDH

3.0

3.3

3.6

A thermally-optimized board layout is recommended; refer to the application note "Surface Mount Assembly of
Exposed-Pad QFP packages"

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4.4.3. Characteristics

4.4.3.1. DC Electrical Characteristics

4.4.3.2. Temperature Ratings

4.4.3.3. ADC Parameters

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

DDL

Digital Core Supply

VDDL

2.3

2.5

2.7

DDA

Analog Supply

VDDA

2.3

2.5

2.7

DDH

Digital IO Supply

VDDH

3.0

3.3

3.6

DDL

Digital Core Supply Current

VDDL

380

420

DDA

Analog Supply Current

VDDA

DDH

Digital IO Supply Current VDDH

32 40 mA

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Junction Temperature

125

°C

Ambient Temperature
Range

°C

Storage Temperature
Range

125

°C

Case Temperature Range

110

°C

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

DDA

ADC Power Supply

VDDA

2.3

2.5

2.7

analog

Analog Power Consump-
tion

(INM-INP)

Input Voltage Swing

INM, INP

0.5

1.2

High Voltage Reference

VRH

1.6

1.7

Low Voltage Reference

VRL

0.7

0.85

Input Impedance

INM, INP

200

Input Capacitance

INM, INP

2.5

Common Mode

VRM

1.0

1.2

1.35

DATA SHEET

DRX 8872C

Micronas

Nov, 28, 2003; 6251-618-2DS

5. Appendix A API Data Types

For ease of porting the library across different operat-
ing systems and platforms, basic data types have
been defined for 8-bit, 16-bit and 32-bit signed and
unsigned integers. These data type definitions are
valid for most 32-bit platforms. When porting the API to
a 16-bit or 8-bit platform, you may need to redefine a
few of these data types.

Additionally, chip-specific data types are defined.

All data types are defined in the file "SP7_Type.h"

5.1. Basic Data Types

(p)u8_t

(pointer to) unsigned 8-bit integer
value: 0...255

(p)s8_t

(pointer to) signed 8-bit integer
value: 128...127

(p)u16_t

(pointer to) unsigned 16-bit integer
value: 0...65,535

(p)s16_t

(pointer to) signed 16-bit integer
value: -32,768...32,767

(p)u32_t

(pointer to) unsigned 32-bit integer
value: 0...4,294,967,295

(p)s32_t

(pointer to) signed 32-bit integer
value: -2,147,483,648...2,147,483,647

(p)Bool_t

(pointer to) Boolean
value: TRUE, FALSE

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5.2. Chip-specific Data Types

(p)AGC_t

(pointer to) AGC control data-type
value: AGC_OFF, AGC_FAST, AGC_SLOW, AGC_INV

(p)Bandwidth_t

(pointer to) bandwidth data type
value: AUTO, BANDWIDTH_8MHZ, BANDWIDTH_7MHZ, BANDWIDTH_6MHZ

(p)Cls_t

(pointer to) channel classification data-type
value: AUTO, CLS_GAUSS, CLS_HEAVYGAUSS, CLS_COCHANNEL, CLS_STATIC,
CLS_MOVING, CLS_ZERODB

(p)Const_t

(pointer to) constellation data-type
value: AUTO, CONST_QPSK, CONST_QAM16, CONST_QAM64

(p)Guard_t

(pointer to) guard data-type
value: AUTO, GUARD_32, GUARD_16, GUARD_8, GUARD_4

(p)Hier_t

(pointer to) hierarcy data-type
value: AUTO, HIER_NONHIER, HIER_ALPHA_1, HIER_ALPHA_2, HIER_ALPHA_4

(p)LCK_t

(pointer to) LCK pin usage data-type
value: LCK_UIO_0, LCK_UIO_1, LCK_INDICATOR, LCK_SAW_8, LCK_SAW_7

(p)Mirror_t

(pointer to) mirrored signal data-type
value: AUTO, NORMAL, MIRROR

(p)Mode_t

(pointer to) mode data-type
value: AUTO, MODE_2K, MODE_8K

(p)Prior_t

(pointer to) priority data-type
value: PRIOR_HIGH, PRIOR_LOW

(p)Rate_t

(pointer to) code rate data-type
value: AUTO, RATE_1_2, RATE_2_3, RATE_3_4, RATE_5_6, RATE_7_8

(p)Status_t

(pointer to) NIM function call result status
value: STS_OK, STS_BUSY, STS_INVALID_ARG, STS_ERROR

(p)TpsFrame_t

(pointer to) TPS frame number data-type
value: TPS_FRAME_1, TPS_FRAME_2, TPS_FRAME_3, TPS_FRAME_4

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DRX 8872C

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Nov, 28, 2003; 6251-618-2DS

6. Appendix B API Required Platform Functions

The API interfaces with the DRX 8872C via a serial
protocol. The implementation of the serial protocol is
platform dependent.

If your platform is a PC running Microsoft Windows 98,
2000, NT, or XP you can use serial interface functions
as supplied that make use of the Micronas proprietary
serial driver that implements serial access via a paral-
lel port. Refer to section 6.1.

For other platforms, you will have to write your own
serial access functionality. Refer to Section 6.2.

6.1. PC Platforms Running Windows 98, NT, 2000,

and XP

If you want to use the Micronas serial driver for serial
access via a parallel port, do the following:

1. Install the Signal Spyder application (as supplied on

the CD). Refer to Signal Spyder manual for instruc-
tions.

In file "SP7_Conf.h", make sure that the following
definition is enabled:

GHILQH 63B,&B63$6(

By default, this line is commented out.

2. Compile the API and the supplied file "i2ctest.c" and

link them into an executable "i2ctest.exe".

3. Make sure that the file "I2CECP.DLL" (as provided

in the Signal Spyder distribution) is in the search
path.

4. Test the serial access by running "i2ctest.exe".

6.2. Other platforms

The API assumes that the following two functions are
made available to read and write registers inside the
DRX 8872C:

Status_t SP7_I2C_Write( u16_t NrOfWbytes, pu8_t
Wdata )
Status_t SP7_I2C_Read ( u16_t NrOfWBytes, pu8_t
Wdata, u16_t NrOfRbytes, pu8_t Rdata )

The SP7_I2C_Write and SP7_I2C_Read functions
must be implemented using the available serial func-
tionality of the specific platform.

The functions must be created in the file "SP7_I2c.c"'.
Below, the requirements for these functions are
described in detail.

After these serial functions have been implemented,
use the supplied file "i2ctest.c" to verify the implemen-
tation.

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6.2.1. SP7_I2C_Write

Writing data to the DRX8872C involves the following
steps:

1. Generate I

C start condition.

2. Write the bytes pointed to by

:GDWD

. Wdata will

include the device address (0xE0 or 0xE2 for the
DRX 8872C and 0xC0 for tuner part). The number
of bytes that must be written is

1U2I:%\WHV

3. Generate I

C stop condition

Or graphically:

Fig. 61: I

C_Write timing (in this case NrOfWbytes=5).

6.2.2. SP7_I2C_Read

Reading data from the DRX8872C involves the follow-
ing steps:

1. Generate I

C start condition.

2. Write the bytes pointed to by

:GDWD

. The number of

bytes that must be written i

1U2I:%\WHV

. This is

used to setup the device address and the internal
address of the register that is going to be pro-
grammed. Before the actual read operation starts,
the device address needs to be setup again. There-
fore the last byte of the

:GDWD

array needs to be

preceded by a start operation as indicated in the
picture below.

3. Read

1U2I5%\WHV

consecutive data-bytes (mini-

mum of 2 bytes) into the memory location pointed to
by

5GDWD

4. Generate I

C stop condition.

Or graphically:

Fig. 62: I

C_Read timing (in this case NrOfWbytes=4, NrOfRbytes=2).

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6.2.3. I2ctest.c

The API distribution includes the source file "i2ctest.c".

The program "I2Ctest" can be used to test the function-
ality of your "SP7_I2c.c" implementation. Simply com-
pile and link these two programs for your platform and
then run the code. The program will return 0 (zero) if
the test was successful, otherwise

1 if any error

occurred. Additionally, if you define VERBOSE during
compilation, the program will also show results using
"printf" calls.

In this file, the I

C address is set at 0xE0. Depending

on your DRX8872C configuration, you may need to
change this I

C address to 0xE2.

/******************************************************************************
* FILENAME: i2ctest.c
*
* DESCRIPTION:
* Test the customer provided SP7_I2C_Read and SP7_I2C_Write functions
*
* This program does the following:
*
* - Switch off system controller
* - Write test pattern in SC_INFO0 register
* - Write different test pattern in SC_INFO1 register
* - Read from SC_INFO0 register
* - Check if read-back value from SC_INFO0 equals written value
*
* By default, it uses I2C address 0xE0. To use 0xE2 redefine I2C_ADDR in i2ctest.c.
*
* By default, it uses stdout to print the test results.
* This can be switched off by removing the line:
* #define VERBOSE
*
* This program only uses the SP7_I2C_Read and SP7_I2C_Write functions in the file SP7_I2C.c.
*
* USAGE:
* Link with SP7_I2C.c to separate executable
* Define VERBOSE to output test results to stdout
*
* NOTES:
* $(c) 2003 Micronas GmbH. All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Micronas and are copyright of Micronas, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Micronas. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Micronas is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND MICRONAS HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* MICRONAS' NEGLIGENCE. $
*
******************************************************************************/

#include "SP7.h"
#include "SP7_Regs.h"

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Micronas

/* Change this I2C address to 0xE2 if ASEL pin of demodulator chip is high */
#define I2C_ADDR 0xE0

/* Remove next line if printf's must be suppressed */
#define VERBOSE

#ifdef VERBOSE
#include <stdio.h>
#endif

/******************************************************************************
* Write a value to a register
*****************************************************************************/
Status_t WriteReg (u16_t Reg, u16_t Data)
{
u8_t Wdata[5];
Status_t rc;

#ifdef VERBOSE
printf("Writing: I2C_addr: 0x%04x, Reg: 0x%04x <== 0x%04x ", I2C_ADDR, Reg, Data);
#endif

Wdata[0] = (u8_t) I2C_ADDR;
Wdata[1] = (u8_t)((Reg >> 8) & 0xff);
Wdata[2] = (u8_t)((Reg >> 0) & 0xff);
Wdata[3] = (u8_t)((Data >> 8) & 0xff);
Wdata[4] = (u8_t)((Data >> 0) & 0xff);

rc = SP7_I2C_Write(5, Wdata);

if (rc == STS_OK) {
#ifdef VERBOSE
printf("OK\n");
#endif
} else {
#ifdef VERBOSE
printf("FAILED\n");
#endif
}

return rc;
}

/******************************************************************************
* Read from a register
*****************************************************************************/
Status_t ReadReg (u16_t Reg, pu16_t Data)
{
u8_t Wdata[4];
u8_t Rdata[2];
Status_t rc;

#ifdef VERBOSE
printf("Reading: I2C_addr: 0x%04x, Reg: 0x%04x ", I2C_ADDR, Reg);
#endif

Wdata[0] = (u8_t)(I2C_ADDR);
Wdata[1] = (u8_t)((Reg >> 8) & 0xff);
Wdata[2] = (u8_t)((Reg >> 0) & 0xff);

/* I2C repeated start in between by */
Wdata[3] = (u8_t)(I2C_ADDR | 0x01);

rc = SP7_I2C_Read(4, Wdata, 2, Rdata);

*Data = (u16_t)((Rdata[0] << 8) | Rdata[1]);

#ifdef VERBOSE
printf("==> 0x%04x ", *Data);
if (rc == STS_OK) {
printf("OK\n");
} else {
printf("FAILED\n");
}
#endif

return rc;
}

DATA SHEET

DRX 8872C

Micronas

Nov, 28, 2003; 6251-618-2DS

/******************************************************************************
* Main test program
*****************************************************************************/
int main(void)
{
u16_t value;
int rc = 0;

/* initialize I2C functionality */
SP7_I2C_Init();

if (WriteReg(SP7_SC_MV_MODE, 0) != STS_OK) {
rc = -1;
}

/* write something in SP7_SC_INFO0 */
if (WriteReg(SP7_SC_INFO0, 0x0aaa) != STS_OK) {
rc = -1;
}

/* write something else in SP7_SC_INFO1 */
if (WriteReg(SP7_SC_INFO1, 0x0555) != STS_OK) {
rc = -1;
}

/* read SP7_SC_INFO0 */
if (ReadReg(SP7_SC_INFO0, &value) != STS_OK) {
rc = -1;
}

if (value != 0x0aaa) {
rc = -1;
#ifdef VERBOSE
printf("Read back check FAILED\n");
#endif
} else {
#ifdef VERBOSE
printf("Read back check PASSED\n");
#endif
}

#ifdef VERBOSE
if (rc == -1) {
printf("\nI2C test FAILED\n");
} else {
printf("\nI2C test PASSED\n");
}
#endif

/* Terminate I2C functionality */
SP7_I2C_Term();

return rc;
}

All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.

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Micronas

Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com

Printed in Germany
Order No. 6251-618-2DS

7. Data Sheet History

1. Data Sheet: "DRX 8872C COFDM Demodulator/

FEC", May 28, 2003, 6251-618-1DS. First release

of the data sheet.

2. Data Sheet: "DRX 8872C COFDM Demodulator/

FEC", Nov, 28, 2003, 6251-618-2DS. Second

release of the data sheet.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DRX8872C

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DRX8872C