2
June 30, 2004; 6251-505-1DS
Micronas
Contents
Page
Section
Title
MAS 35x9F
DATA SHEET
5
1.
Introduction
6
1.1.
Features
6
1.2.
Features of the MAS 35x9F Family
7
1.3.
Application Overview
8
2.
Functional Description
8
2.1.
Overview
8
2.2.
Architecture of the MAS 35x9F
8
2.3.
DSP Core
9
2.3.1.
RAM and Registers
9
2.3.2.
Firmware and Software
9
2.3.2.1.
Internal Program ROM and Firmware, MPEG-Decoding
9
2.3.2.2.
Program Download Feature
10
2.4.
Audio Codec
10
2.4.1.
A/D Converter and Microphone Amplifier
10
2.4.2.
Baseband Processing
10
2.4.2.1.
Bass, Treble, and Loudness
10
2.4.2.2.
Micronas Bass (MB)
10
2.4.2.3.
Automatic Volume Control (AVC)
10
2.4.2.4.
Balance and Volume
11
2.4.3.
D/A Converters
11
2.4.4.
Output Amplifiers
11
2.5.
Clock Management
11
2.5.1.
DSP Clock
11
2.5.2.
Clock Output At CLKO
12
2.6.
Power Supply Concept
12
2.6.1.
Power Supply Regions
12
2.6.2.
DC/DC Converters
13
2.6.3.
Power Supply Configurations
15
2.7.
Battery Voltage Supervision
15
2.8.
Interfaces
15
2.8.1.
I2C Control Interface
15
2.8.2.
S/PDIF Input Interface
15
2.8.3.
S/PDIF Output
15
2.8.4.
Multiline Serial Audio Input (SDI, SDIB)
15
2.8.5.
Multiline Serial Output (SDO)
15
2.8.6.
Parallel Input/Output Interface (PIO)
16
2.9.
MPEG Synchronization Output
17
2.10.
MP3 Block Input Mode
17
2.10.1.
Functional Description of the MP3 Block Input Mode
18
2.10.2.
Setup
18
2.10.2.1.
Resync Timeout
18
2.10.2.2.
Detailed Setup
18
2.11.
Default Operation
18
2.11.1.
Stand-by Functions
18
2.11.2.
Power-Up of the DC/DC Converters and Reset
19
2.11.2.1.
Important Advice for Turn-on and Operating Voltage
Contents, continued
Page
Section
Title
Micronas
June 30, 2004; 6251-505-1DS
3
DATA SHEET
MAS 35x9F
20
2.11.3.
Reset Signal Specification
21
2.11.4.
Control of the Signal Processing
21
2.11.5.
Start-up of the Audio Codec
21
2.11.6.
Power-Down
22
3.
Controlling
22
3.1.
I
2
C Interface
22
3.1.1.
Device Address
22
3.1.2.
I
2
C Registers and Subaddresses
22
3.1.3.
Naming Convention
22
3.2.
Direct Configuration Registers
23
3.2.1.
Write Direct Configuration Registers
23
3.2.2.
Read Direct Configuration Register
27
3.3.
DSP Core
27
3.3.1.
Access Protocol
28
3.3.2.
Data Formats
28
3.3.2.1.
Run and Freeze (Codes 0hex to 3hex)
28
3.3.2.2.
Read Register (Code A
hex
)
28
3.3.2.3.
Write Register (Code B
hex
)
29
3.3.2.4.
Read Memory (Codes C
hex
and D
hex
)
29
3.3.2.5.
Short Read Memory (Codes C4
hex
and D4
hex
)
29
3.3.2.6.
Write Memory (Codes Ehex and Fhex)
29
3.3.2.7.
Short Write Memory (Codes E4
hex
and F4
hex
)
29
3.3.2.8.
Clear SYNC Signal (Code 5hex)
30
3.3.2.9.
Default Read
30
3.3.2.10.
Fast Program Download (Code 6
hex
)
30
3.3.2.11.
Serial Program Download
31
3.3.2.12.
Read IC Version (Code 7
hex
)
31
3.3.3.
List of DSP Registers
31
3.3.4.
List of DSP Memory Cells
32
3.3.4.1.
Application Selection and Application Running
32
3.3.4.2.
Application Specific Control
43
3.3.5.
Ancillary Data
43
3.3.6.
Reading of the Memory Cells "Number of Bits in Ancillary Data" and "Ancillary Data"
44
3.3.7.
DSP Volume Control
44
3.3.8.
Explanation of the G.729A Data Format
45
3.4.
Audio Codec Access Protocol
45
3.4.1.
Write Codec Register
45
3.4.2.
Read Codec Register
46
3.4.3.
Codec Registers
52
3.4.4.
Basic MB Configuration
4
June 30, 2004; 6251-505-1DS
Micronas
Contents, continued
Page
Section
Title
MAS 35x9F
DATA SHEET
54
4.
Specifications
54
4.1.
Outline Dimensions
57
4.2.
Pin Connections and Short Descriptions
60
4.3.
Pin Descriptions
60
4.3.1.
Power Supply Pins
60
4.3.2.
Analog Reference Pins
60
4.3.3.
DC/DC Converters and Battery Voltage Supervision
60
4.3.4.
Oscillator Pins and Clocking
60
4.3.5.
Control Lines
60
4.3.6.
Parallel Interface Lines
61
4.3.6.1.
PIO Handshake Lines
61
4.3.7.
Serial Input Interface (SDI)
61
4.3.8.
Serial Input Interface B (SDIB)
61
4.3.9.
Serial Output Interface (SDO)
61
4.3.10.
S/PDIF Input Interface
61
4.3.11.
S/PDIF Output Interface
61
4.3.12.
Analog Input Interfaces
61
4.3.13.
Analog Output Interfaces
62
4.3.14.
Miscellaneous
62
4.4.
Pin Configuration
63
4.5.
Internal Pin Circuits
64
4.5.1.
Reset Pin Configuration for MAS 3529F and MAS 3539F
65
4.6.
Electrical Characteristics
65
4.6.1.
Absolute Maximum Ratings
67
4.6.1.1.
Recommended Operating Conditions
71
4.6.2.
Digital Characteristics
72
4.6.2.1.
I
2
C Characteristics
73
4.6.2.2.
Serial (I
2
S) Input Interface Characteristics (SDI, SDIB)
74
4.6.2.3.
Serial Output Interface Characteristics (SDO)
76
4.6.2.4.
S/PDIF Input Characteristics
77
4.6.2.5.
S/PDIF Output Characteristics
77
4.6.2.6.
PIO as Parallel Input Interface: DMA Mode
79
4.6.2.7.
PIO as Parallel Input Interface:
Program Download Mode
80
4.6.2.8.
PIO as Parallel Output Interface
81
4.6.3.
Analog Characteristics
84
4.6.4.
DC/DC Converter Characteristics
86
4.6.5.
Typical Performance Characteristics
89
5.
Application
89
5.1.
Typical Application in a Portable Player
90
5.2.
Recommended DC/DC Converter Application Circuit
92
6.
Data Sheet History
DATA SHEET
MAS 35x9F
Micronas
June 30, 2004; 6251-505-1DS
5
MPEG Layer 2/3, AAC Audio Decoder,
G.729 Annex A Codec
Release Note: Revision bars indicate significant
changes to the previous edition. This data sheet
applies to the MAS 35x9F version B4.
1. Introduction
The MAS 35x9F is a single-chip, low-power MPEG
layer 2/3 and MPEG2-AAC audio stereo decoder. It
also contains the G.729 Annex A speech compression
and decompression technology for use in memory-
based or broadcast applications. Additional functional-
ity is achievable via download software (e.g., CELP
voice decoder, Micronas SC4 (ADPCM) encoder/
decoder).
The MAS 35x9F decoding block accepts compressed
digital data streams as serial bit streams or in parallel
format, and provides serial PCM and S/PDIF output of
decompressed audio. In addition to the signal process-
ing function, the IC incorporates a high-performance
stereo D/A converter, headphone amplifiers, a stereo
A/D converter, a microphone amplifier, and two DC/DC
converters.
Thus, the MAS 35x9F provides a true
"all-in-one"
solution that is ideally suited for highly optimized mem-
ory-based portable music players with integrated
speech recording and playback function.
In MPEG 1 (ISO 11172-3), three hierarchical layers of
compression have been standardized. The most
sophisticated and complex, layer 3, allows compres-
sion rates of approximately 12:1 for mono and stereo
signals while still maintaining CD audio quality. Layer 2
(widely used, e.g., in DVD) achieves a compression of
8:1 without significant losses in audio quality.
The MAS 35x9F supports the "Advanced Audio Cod-
ing" (AAC) that is defined as a part of MPEG 2. AAC
provides compression rates up to 16:1. It defines sev-
eral profiles for different applications. This IC decodes
the "low complexity profile" that is especially optimized
for portable applications.
The MAS 35x9F also implements a voice encoder and
decoder that is compliant to the ITU Standard G.729
Annex A.
SC4 is a proprietary Micronas speech codec technol-
ogy that can be downloaded to the MAS 35x9F, to
allow recording and playing back speech at various
sampling rates.
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