Document Outline

• MSP34x1G
• Multistandard Sound Processor Family with Virtual Dolby Surround
  • 6 1. Introduction
  • 9 2. Functional Description
  • 17 3. Control Interface
  • 47 4. Specifications
  • 79 5. Appendix A: Overview of TV-Sound Standards
  • 83 6. Appendix B: Manual/Compatibility Mode
  • 99 7. Appendix D: MSP34x1G Version History
  • 100 8. Appendix E: Application Circuit
  • 102 9. Data Sheet History
  • Multistandard Sound Processor Family with Virtual Dolby Surround
• 1. Introduction
  • Fig. 1�1: Simplified functional block diagram of the MSP34x1G
  • 1.1. Features of the MSP34x1G Family and Differences to MSP34xxD
  • 1.2. MSP34x1G Version List
  • 1.3. MSP34x1G Versions and their Application Fields
    • Table 1�1: TV Stereo Sound Standards covered by the MSP34x1G IC Family (details see Appendix A)
    • Fig. 1�2: Typical MSP34x1G application
• 2. Functional Description
  • Fig. 2�1: Signal flow block diagram of the MSP34x1G (input and output names correspond to pin n...
  • 2.1. Architecture of the MSP34x1G Family
  • 2.2. Sound IF Processing
  • 2.2.1. Analog Sound IF Input
  • 2.2.2. Demodulator: Standards and Features
  • 2.2.3. Preprocessing of Demodulator Signals
  • 2.2.4. Automatic Sound Select
  • 2.3. Preprocessing for SCART and I2S Input Signals
    • Fig. 2�2: Source channel assignment of demodulated signals in Manual Mode
    • Fig. 2�3: Source channel assignment of demodulated signals in Automatic Sound Select Mode
    • Table 2�1: Performed actions of the Automatic Sound Selection
    • Table 2�2: Sound modes for the demodulator source channels with Automatic Sound Select
  • 2.4. Source Selection and Output Channel Matrix
  • 2.5. Audio Baseband Processing
  • 2.5.1. Automatic Volume Correction (AVC)
    • Fig. 2�4: Simplified AVC characteristics
  • 2.5.2. Loudspeaker and Headphone Outputs
  • 2.5.3. Subwoofer Output
  • 2.5.4. Quasi-Peak Detector
  • 2.6. Virtual Surround System Application Tips
  • 2.6.1. Sweet Spot
  • 2.6.2. Clipping
  • 2.6.3. Loudspeaker Requirements
  • 2.6.4. Cabinet Requirements
  • 2.7. SCART Signal Routing
  • 2.7.1. SCART DSP In and SCART Out Select
  • 2.7.2. Stand-by Mode
  • 2.8. I2S Bus Interface
    • 1. The SONY format: I2S_WS changes at the word boundaries.
      • 2. The PHILIPS format: I2S_WS changes one I2S_CL period before the word boundaries.
    • 1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16bits) per sampl...
      • 2. I2S_DA_OUT: For output, two channels (2*16bits) per sampling cycle (32kHz) are transmitted.
      • 3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024MHz).
      • 4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.
  • 2.9. ADR Bus Interface
  • 2.10. Digital Control I/O Pins and Status Change Indication
  • 2.11. Clock PLL Oscillator and Crystal Specifications
• 3. Control Interface
  • 3.1. I2C Bus Interface
  • 3.1.1. Device and Subaddresses
    • Internal hardware error handling:
    • Indication and solving of the error status:
    • Indication of reset (only versions from A2 on):
      • Table 3�1: I2C Bus Device Addresses
      • Table 3�2: I2C Bus Subaddresses
  • 3.1.2. Description of CONTROL Register
    • Table 3�3: Control as a Write Register
    • Table 3�4: CONTROL as a Read Register (only MSP34x1G-versions from A2 on)
  • 3.1.3. Protocol Description
    • Fig.3�1: I2C bus protocol (MSB first; data must be stable while clock is high)
  • 3.1.4. Proposals for General MSP34x1G I2C Telegrams
  • 3.1.4.1. Symbols
  • 3.1.4.2. Write Telegrams
  • 3.1.4.3. Read Telegrams
  • 3.1.4.4. Examples
  • 3.2. Start-Up Sequence: Power-Up and I2C Controlling
  • 3.3. MSP34x1G Programming Interface
  • 3.3.1. User Registers Overview
    • Table 3�5: List of MSP34x1G Write Registers
    • Table 3�6: List of MSP34x1G Read Registers
  • 3.3.2. Description of User Registers
    • Table 3�7: Standard Codes for STANDARD SELECT register
  • 3.3.2.1. Standard Select Register
  • 3.3.2.2. Refresh of Standard Select Register
  • 3.3.2.3. Standard RESULT Register
    • Table 3�8: Results of the Automatic Standard Detection
  • 3.3.2.4. Write Registers on I2C Subaddress 10hex
    • Table 3�9: Write Registers on I2C Subaddress 10hex
  • 3.3.2.5. Read Registers on I2C Subaddress 11hex
    • Table 3�10: Read Registers on I2C Subaddress 11hex
  • 3.3.2.6. Write Registers on I2C Subaddress 12hex
    • Table 3�11: Write Registers on I2C Subaddress 12hex
    • 1. MODUS with bit[0] = 0 (Automatic Sound Select off)
      • 2. FM Presc./Matrix with FM Matrix = Sound A Mono (SAP: Sound B Mono)
      • 3. Select FM/AM source channel, with channel matrix set to �Stereo� (transparent)
  • 3.3.2.7. Read Registers on I2C Subaddress 13hex
    • Table 3�12: Read Registers on I2C Subaddress 13hex
  • 3.4. Programming Tips
    • SCART Signal Path
    • 1. Select analog input for the SCART baseband processing (SCART DSP Input Select) by means of th...
      • 2. Select the source for each analog SCART output (SCART Output Select) by means of the ACB regi...
      • Demodulator Input
    • 1. Set MODUS register to the preferred mode and Sound IF input.
      • 2. Choose preferred prescale (FM and NICAM) values.
      • 3. Write STANDARD SELECT register.
      • 4. Choose FM matrix according to the sound mode indicated in the STATUS register.
      • SCART and I2S Inputs
    • 1. Select preferred prescale for SCART.
      • 2. Select preferred prescale for I2S inputs (set to 0dB after RESET).
      • Output Channels
    • 1. Select the source channel and matrix for each output channel.
      • 2. Set audio baseband processing.
      • 3. Select volume for each output channel.
  • 3.5. Examples of Minimum Initialization Codes
    • 1. Perform an I2C controlled reset of the IC.
      • 2. Write MODUS register (with Automatic Sound Select).
      • 3. Set Source Selection for loudspeaker channel (with matrix set to STEREO).
      • 4. Set Prescale (FM and/or NICAM and dummy FMmatrix).
      • 5. Write STANDARD SELECT register.
      • 6. Set Volume loudspeaker channel to 0dB.
  • 3.5.1. SCART1 Input to Loudspeaker in Stereo Sound
  • 3.5.2. SCART1 Input to Loudspeaker in 3D-PANORAMA Sound
  • 3.5.3. Noise Sequencer for 3D-PANORAMA Sound
  • 3.5.4. B/G-FM (A2 or NICAM)
  • 3.5.5. BTSC-Stereo
  • 3.5.6. BTSC-SAP with SAP at Loudspeaker Channel
  • 3.5.7. FM-Stereo Radio
  • 3.5.8. Automatic Standard Detection
  • 3.5.9. Software Flow for Interrupt driven STATUS Check
    • Fig. 3�2: Software flow diagram for a Minimum demodulator setup for a European Multistandard TV ...
• 4. Specifications
  • 4.1. Outline Dimensions
    • Fig. 4�1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensi...
    • Fig. 4�2: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensi...
    • Fig. 4�3: 52-Pin Plastic Shrink Dual-Inline Package (PSDIP52) Weight approximately 5.5 g Dimensi...
    • Fig. 4�4: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 g Dimensions in mm
    • Fig. 4�5: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 3.5 g Dimensi...
  • 4.2. Pin Connections and Short Descriptions
  • 4.3. Pin Descriptions
  • 4.4. Pin Configurations
    • Fig. 4�6: 68-pin PLCC package
    • Fig. 4�7: 64-pin PSDIP package
    • Fig. 4�8: 52-pin PSDIP package
    • Fig. 4�9: 80-pin PQFP package
    • Fig. 4�10: 64-pin PLQFP package
  • 4.5. Pin Circuits
    • Fig. 4�11: Output Pins 6, 8, 9, and 10 (I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL)
    • Fig. 4�12: Input/Output Pins 2 and 3 (I2C_CL, I2C_DA)
    • Fig. 4�13: Input Pins 7, 17, 21, 70, and 80 (I2S_DA_IN1, I2S_DA_IN2, RESETQ, TESTEN, STANDBYQ)
    • Fig. 4�14: Input Pin 79 (ADR_SEL)
    • Fig. 4�15: Input/Output Pins 4, 5, 77, and 78 (I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)
    • Fig. 4�16: Output/Input Pins 71, 72, and 74 (XTAL_IN, XTAL_OUT, AUD_CL_OUT)
    • Fig. 4�17: Input Pins 58, 67, 68, and 69 (VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+)
    • Fig. 4�18: Capacitor Pins 38 and 40 (CAPL_A, CAPL_M)
    • Fig. 4�19: Input Pin 60 (MONO_IN)
    • Fig. 4�20: Input Pins 47, 48, 50, 51, 53, 54, 56, and 57 (SC4-1_IN_L/R)
    • Fig. 4�21: Output Pins 24, 25, 27, 28 and 30 (DACA_R/L, DACM_R/L, DACM_SUB)
    • Fig. 4�22: Pin 45 (AGNDC)
    • Fig. 4�23: Output Pins 33, 34, 36, and 37 (SC_2_OUT_R/L, SC_1_OUT_R/L)
  • 4.6. Electrical Characteristics
  • 4.6.1. Absolute Maximum Ratings
  • 4.6.2. Recommended Operating Conditions (TA = 0 to 70 �C)
  • 4.6.2.1. General Recommended Operating Conditions
  • 4.6.2.2. Analog Input and Output Recommendations
  • 4.6.2.3. Recommendations for Analog Sound IF Input Signal
  • 4.6.2.4. Crystal Recommendations
  • 4.6.3. Characteristics
  • 4.6.3.1. General Characteristics
  • 4.6.3.2. Digital Inputs, Digital Outputs
  • 4.6.3.3. Reset Input and Power-Up
    • Fig. 4�24: Power-up sequence
  • 4.6.3.4. I2C-Bus Characteristics
    • Fig. 4�25: I2C bus timing diagram
  • 4.6.3.5. I2S-Bus Characteristics
    • Fig. 4�26: I2S bus timing diagram
  • 4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
  • 4.6.3.7. Sound IF Inputs
  • 4.6.3.8. Power Supply Rejection
  • 4.6.3.9. Analog Performance
  • 4.6.3.10. Sound Standard Dependent Characteristics
• 5. Appendix A: Overview of TV-Sound Standards
  • 5.1. NICAM 728
    • Table 5�1: Summary of NICAM 728 sound modulation parameters
    • Table 5�2: Summary of NICAM 728 sound coding characteristics
  • 5.2. A2-Systems
    • Table 5�3: Key parameters for A2 Systems of Standards B/G, D/K, and M
  • 5.3. BTSC-Sound System
    • Table 5�4: Key parameters for BTSC-Sound Systems
  • 5.4. Japanese FM Stereo System (EIA-J)
    • Table 5�5: Key parameters for Japanese FM-Stereo Sound System EIA-J
  • 5.5. FM Satellite Sound
    • Table 5�6: Key parameters for FM Satellite Sound
  • 5.6. FM-Stereo Radio
    • Table 5�7: Key parameters for FM-Stereo Radio Systems
• 6. Appendix B: Manual/Compatibility Mode
  • 6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode
    • Table 6�1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable!
    • Table 6�2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable!
  • 6.2. DSP Write and Read Registers for Manual/Compatibility Mode
    • Table 6�3: DSP-Write Registers; Subaddress: 12hex, all registers are readable as well
    • Table 6�4: DSP Read Registers; Subaddress: 13hex, all registers are not writable
  • 6.3. Manual/Compatibility Mode: Description of Demodulator Write Registers
    • 6.3.1. Automatic Switching between NICAM and Analog Sound
  • 6.3.1.1. Function in Automatic Sound Select Mode
  • 6.3.1.2. Function in Manual Mode
    • Fig. 6�1: Hysteresis for Automatic Switching
    • Table 6�5: Coding of Automatic NICAM/Analog Sound Switching; Reset Status: Mode 0
    • 6.3.2. A2 Threshold
    • Table 6�6: Write Register on I2C Subaddress 10hex : A2 Threshold
    • 6.3.3. Carrier-Mute Threshold
    • Table 6�7: Write Register on I2C Subaddress 10hex : Carrier-Mute Threshold
    • 6.3.4. Register AD_CV
    • Table 6�8: AD_CV Register; reset status: all bits are �0�
    • Table 6�9: Reference Values for Active AGC (AD_CV[7] = 1)
    • Table 6�10: AD_CV parameters for Constant Input Gain (AD_CV[7]=0)
    • 6.3.5. Register MODE_REG
    • Table 6�11: Control word �MODE_REG�; reset status: all bits are �0�
    • Table 6�12: Loading sequence for FIRcoefficients
    • 6.3.6. FIRParameter, Registers FIR1 and FIR2
    • 6.3.7. DCORegisters
    • Table 6�13: 8bit FIRcoefficients (decimal integer); reset status: all coefficients are �0�
    • Table 6�14: DCO registers for the MSP34x1G; reset status: DCO_HI/LO = �0000�
  • 6.4. Manual/Compatibility Mode: Description of Demodulator Read Registers
    • 6.4.1. NICAM Mode Control/Additional Data Bits Register
    • Table 6�15: NICAM operation modes as defined by the EBU NICAM 728 specification
    • 6.4.2. Additional Data Bits Register
    • 6.4.3. CIB Bits Register
    • 6.4.4. NICAM Error Rate Register
    • 6.4.5. PLL_CAPS Readback Register
    • 6.4.6. AGC_GAIN Readback Register
    • 6.4.7. Automatic Search Function for FMCarrier Detection in Satellite Mode
  • 6.5. Manual/Compatibility Mode: Description of DSP Write Registers
    • 6.5.1. Additional Channel Matrix Modes
    • 6.5.2. Volume Modes of SCART1/2 Outputs
    • 6.5.3. FM Fixed Deemphasis
    • 6.5.4. FM Adaptive Deemphasis
    • 6.5.5. NICAM Deemphasis
    • 6.5.6. Identification Mode for A2 Stereo Systems
    • 1. Program change
      • 2. Reset identfilter
      • 3. Set identification mode back to standard B/G or M
      • 4. Read stereo detection register
      • 6.5.7. FM DC Notch
  • 6.6. Manual/Compatibility Mode: Description of DSP Read Registers
    • 6.6.1. Stereo Detection Register for A2 Stereo Systems
    • 6.6.2. DC Level Register
  • 6.7. Demodulator Source Channels in Manual Mode
    • 6.7.1. Terrestric Sound Standards
    • 6.7.2. SAT Sound Standards
    • Table 6�16: Manual Sound Select Mode for Terrestric Sound Standards
    • Table 6�17: Manual Sound Select Modes for SAT-Modes (FM Matrix is set automatically)
  • 6.8. Exclusions of Audio Baseband Features
    • 1. NICAM cannot be processed simultaneously with the FM2 channel.
      • 2. FM adaptive deemphasis cannot be processed simultaneously with FMidentification.
  • 6.9. Phase Relationship of Analog Outputs
    • Fig. 6�2: Phase diagram of the MSP34x1G
• 7. Appendix D: MSP34x1G Version History
• 8. Appendix E: Application Circuit
• 9. Data Sheet History
  • 1. Preliminary data sheet: �MSP34x1G Multistandard Sound Processor Family with Virtual Dolby Su...